cyt3bb_a/m0/eth0/
dma_addr_or_mask.rs

1#[doc = "Register `DMA_ADDR_OR_MASK` reader"]
2pub struct R(crate::R<DMA_ADDR_OR_MASK_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<DMA_ADDR_OR_MASK_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<DMA_ADDR_OR_MASK_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<DMA_ADDR_OR_MASK_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `DMA_ADDR_OR_MASK` writer"]
17pub struct W(crate::W<DMA_ADDR_OR_MASK_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<DMA_ADDR_OR_MASK_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<DMA_ADDR_OR_MASK_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<DMA_ADDR_OR_MASK_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `MASK_ENABLE` reader - Data Buffer Address Mask Enable. These bits are associated directly with bits\\[31:28\\].When bit 0 is set, the AXI/AHB address bit 28 used for accessing the receive data buffers will be forced to the value stored in bit 28 of this register. When bit 1 is set, the AXI/AHB address bit 29 used for accessing the receive data buffers will be forced to the value stored in bit 29 of this register. When bit 2 is set, the AXI/AHB address bit 30 used for accessing the receive data buffers will be forced to the value stored in bit 30 of this register. When bit 3 is set, the AXI/AHB address bit 31 used for accessing the receive data buffers will be forced to the value stored in bit 31 of this register. When these bits are clear, the associated value stored in bits 31:28 have no effect on the AXI/AHB address used for receive data buffer accesses. Any changes to this register will be ignored while the DMA is currently processing a receive packet. It will only affect the next full packet to be written to external memory."]
38pub type MASK_ENABLE_R = crate::FieldReader<u8, u8>;
39#[doc = "Field `MASK_ENABLE` writer - Data Buffer Address Mask Enable. These bits are associated directly with bits\\[31:28\\].When bit 0 is set, the AXI/AHB address bit 28 used for accessing the receive data buffers will be forced to the value stored in bit 28 of this register. When bit 1 is set, the AXI/AHB address bit 29 used for accessing the receive data buffers will be forced to the value stored in bit 29 of this register. When bit 2 is set, the AXI/AHB address bit 30 used for accessing the receive data buffers will be forced to the value stored in bit 30 of this register. When bit 3 is set, the AXI/AHB address bit 31 used for accessing the receive data buffers will be forced to the value stored in bit 31 of this register. When these bits are clear, the associated value stored in bits 31:28 have no effect on the AXI/AHB address used for receive data buffer accesses. Any changes to this register will be ignored while the DMA is currently processing a receive packet. It will only affect the next full packet to be written to external memory."]
40pub type MASK_ENABLE_W<'a, const O: u8> =
41    crate::FieldWriter<'a, u32, DMA_ADDR_OR_MASK_SPEC, u8, u8, 4, O>;
42#[doc = "Field `MASK_VALUE_DA` reader - Data Buffer Address Mask Value. Values used to force bits 31:28 of the receive data buffer AHB address to a particular value when the associated enable bits stored in this register \\[3:0\\]
43are set. Any changes to this register will be ignored while the DMA is currently processing a receive packet. It will only affect the next full packet to be written to external system memory."]
44pub type MASK_VALUE_DA_R = crate::FieldReader<u8, u8>;
45#[doc = "Field `MASK_VALUE_DA` writer - Data Buffer Address Mask Value. Values used to force bits 31:28 of the receive data buffer AHB address to a particular value when the associated enable bits stored in this register \\[3:0\\]
46are set. Any changes to this register will be ignored while the DMA is currently processing a receive packet. It will only affect the next full packet to be written to external system memory."]
47pub type MASK_VALUE_DA_W<'a, const O: u8> =
48    crate::FieldWriter<'a, u32, DMA_ADDR_OR_MASK_SPEC, u8, u8, 4, O>;
49impl R {
50    #[doc = "Bits 0:3 - Data Buffer Address Mask Enable. These bits are associated directly with bits\\[31:28\\].When bit 0 is set, the AXI/AHB address bit 28 used for accessing the receive data buffers will be forced to the value stored in bit 28 of this register. When bit 1 is set, the AXI/AHB address bit 29 used for accessing the receive data buffers will be forced to the value stored in bit 29 of this register. When bit 2 is set, the AXI/AHB address bit 30 used for accessing the receive data buffers will be forced to the value stored in bit 30 of this register. When bit 3 is set, the AXI/AHB address bit 31 used for accessing the receive data buffers will be forced to the value stored in bit 31 of this register. When these bits are clear, the associated value stored in bits 31:28 have no effect on the AXI/AHB address used for receive data buffer accesses. Any changes to this register will be ignored while the DMA is currently processing a receive packet. It will only affect the next full packet to be written to external memory."]
51    #[inline(always)]
52    pub fn mask_enable(&self) -> MASK_ENABLE_R {
53        MASK_ENABLE_R::new((self.bits & 0x0f) as u8)
54    }
55    #[doc = "Bits 28:31 - Data Buffer Address Mask Value. Values used to force bits 31:28 of the receive data buffer AHB address to a particular value when the associated enable bits stored in this register \\[3:0\\]
56are set. Any changes to this register will be ignored while the DMA is currently processing a receive packet. It will only affect the next full packet to be written to external system memory."]
57    #[inline(always)]
58    pub fn mask_value_da(&self) -> MASK_VALUE_DA_R {
59        MASK_VALUE_DA_R::new(((self.bits >> 28) & 0x0f) as u8)
60    }
61}
62impl W {
63    #[doc = "Bits 0:3 - Data Buffer Address Mask Enable. These bits are associated directly with bits\\[31:28\\].When bit 0 is set, the AXI/AHB address bit 28 used for accessing the receive data buffers will be forced to the value stored in bit 28 of this register. When bit 1 is set, the AXI/AHB address bit 29 used for accessing the receive data buffers will be forced to the value stored in bit 29 of this register. When bit 2 is set, the AXI/AHB address bit 30 used for accessing the receive data buffers will be forced to the value stored in bit 30 of this register. When bit 3 is set, the AXI/AHB address bit 31 used for accessing the receive data buffers will be forced to the value stored in bit 31 of this register. When these bits are clear, the associated value stored in bits 31:28 have no effect on the AXI/AHB address used for receive data buffer accesses. Any changes to this register will be ignored while the DMA is currently processing a receive packet. It will only affect the next full packet to be written to external memory."]
64    #[inline(always)]
65    #[must_use]
66    pub fn mask_enable(&mut self) -> MASK_ENABLE_W<0> {
67        MASK_ENABLE_W::new(self)
68    }
69    #[doc = "Bits 28:31 - Data Buffer Address Mask Value. Values used to force bits 31:28 of the receive data buffer AHB address to a particular value when the associated enable bits stored in this register \\[3:0\\]
70are set. Any changes to this register will be ignored while the DMA is currently processing a receive packet. It will only affect the next full packet to be written to external system memory."]
71    #[inline(always)]
72    #[must_use]
73    pub fn mask_value_da(&mut self) -> MASK_VALUE_DA_W<28> {
74        MASK_VALUE_DA_W::new(self)
75    }
76    #[doc = "Writes raw bits to the register."]
77    #[inline(always)]
78    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
79        self.0.bits(bits);
80        self
81    }
82}
83#[doc = "Receive DMA Data Buffer Address Mask\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dma_addr_or_mask](index.html) module"]
84pub struct DMA_ADDR_OR_MASK_SPEC;
85impl crate::RegisterSpec for DMA_ADDR_OR_MASK_SPEC {
86    type Ux = u32;
87}
88#[doc = "`read()` method returns [dma_addr_or_mask::R](R) reader structure"]
89impl crate::Readable for DMA_ADDR_OR_MASK_SPEC {
90    type Reader = R;
91}
92#[doc = "`write(|w| ..)` method takes [dma_addr_or_mask::W](W) writer structure"]
93impl crate::Writable for DMA_ADDR_OR_MASK_SPEC {
94    type Writer = W;
95    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
96    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
97}
98#[doc = "`reset()` method sets DMA_ADDR_OR_MASK to value 0"]
99impl crate::Resettable for DMA_ADDR_OR_MASK_SPEC {
100    const RESET_VALUE: Self::Ux = 0;
101}
cyt3bb_a/m0/eth0/dma_addr_or_mask.rs

cyt3bb_a/m0/eth0/
dma_addr_or_mask.rs
