cyt3bb_a/m0/dw0/ch_struct/
ch_status.rs

1#[doc = "Register `CH_STATUS` reader"]
2pub struct R(crate::R<CH_STATUS_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CH_STATUS_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CH_STATUS_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CH_STATUS_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Field `INTR_CAUSE` reader - Specifies the source of the interrupt cause: '0': NO_INTR '1': COMPLETION '2': SRC_BUS_ERROR '3': DST_BUS_ERROR '4': SRC_MISAL '5': DST_MISAL '6': CURR_PTR_NULL '7': ACTIVE_CH_DISABLED '8': DESCR_BUS_ERROR '9'-'15': Not used. For error related interrupt causes (INTR_CAUSE is '2', '3', ..., '8'), the channel is disabled (HW sets CH_CTL.ENABLED to '0')."]
17pub type INTR_CAUSE_R = crate::FieldReader<u8, u8>;
18#[doc = "Field `PENDING` reader - Specifies pending DW channels; i.e. enabled channels whose trigger got activated. This field includes all channels that are in the pending state (not scheduled) or active state (scheduled and performing data transfer(s))."]
19pub type PENDING_R = crate::BitReader<bool>;
20impl R {
21    #[doc = "Bits 0:3 - Specifies the source of the interrupt cause: '0': NO_INTR '1': COMPLETION '2': SRC_BUS_ERROR '3': DST_BUS_ERROR '4': SRC_MISAL '5': DST_MISAL '6': CURR_PTR_NULL '7': ACTIVE_CH_DISABLED '8': DESCR_BUS_ERROR '9'-'15': Not used. For error related interrupt causes (INTR_CAUSE is '2', '3', ..., '8'), the channel is disabled (HW sets CH_CTL.ENABLED to '0')."]
22    #[inline(always)]
23    pub fn intr_cause(&self) -> INTR_CAUSE_R {
24        INTR_CAUSE_R::new((self.bits & 0x0f) as u8)
25    }
26    #[doc = "Bit 31 - Specifies pending DW channels; i.e. enabled channels whose trigger got activated. This field includes all channels that are in the pending state (not scheduled) or active state (scheduled and performing data transfer(s))."]
27    #[inline(always)]
28    pub fn pending(&self) -> PENDING_R {
29        PENDING_R::new(((self.bits >> 31) & 1) != 0)
30    }
31}
32#[doc = "Channel status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ch_status](index.html) module"]
33pub struct CH_STATUS_SPEC;
34impl crate::RegisterSpec for CH_STATUS_SPEC {
35    type Ux = u32;
36}
37#[doc = "`read()` method returns [ch_status::R](R) reader structure"]
38impl crate::Readable for CH_STATUS_SPEC {
39    type Reader = R;
40}
41#[doc = "`reset()` method sets CH_STATUS to value 0"]
42impl crate::Resettable for CH_STATUS_SPEC {
43    const RESET_VALUE: Self::Ux = 0;
44}
cyt3bb_a/m0/dw0/ch_struct/ch_status.rs

cyt3bb_a/m0/dw0/ch_struct/
ch_status.rs
