cyt3bb_a/m0/dmac/ch/
intr_mask.rs

1#[doc = "Register `INTR_MASK` reader"]
2pub struct R(crate::R<INTR_MASK_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<INTR_MASK_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<INTR_MASK_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<INTR_MASK_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `INTR_MASK` writer"]
17pub struct W(crate::W<INTR_MASK_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<INTR_MASK_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<INTR_MASK_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<INTR_MASK_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `COMPLETION` reader - Mask for corresponding field in INTR register."]
38pub type COMPLETION_R = crate::BitReader<bool>;
39#[doc = "Field `COMPLETION` writer - Mask for corresponding field in INTR register."]
40pub type COMPLETION_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTR_MASK_SPEC, bool, O>;
41#[doc = "Field `SRC_BUS_ERROR` reader - N/A"]
42pub type SRC_BUS_ERROR_R = crate::BitReader<bool>;
43#[doc = "Field `SRC_BUS_ERROR` writer - N/A"]
44pub type SRC_BUS_ERROR_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTR_MASK_SPEC, bool, O>;
45#[doc = "Field `DST_BUS_ERROR` reader - N/A"]
46pub type DST_BUS_ERROR_R = crate::BitReader<bool>;
47#[doc = "Field `DST_BUS_ERROR` writer - N/A"]
48pub type DST_BUS_ERROR_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTR_MASK_SPEC, bool, O>;
49#[doc = "Field `SRC_MISAL` reader - N/A"]
50pub type SRC_MISAL_R = crate::BitReader<bool>;
51#[doc = "Field `SRC_MISAL` writer - N/A"]
52pub type SRC_MISAL_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTR_MASK_SPEC, bool, O>;
53#[doc = "Field `DST_MISAL` reader - N/A"]
54pub type DST_MISAL_R = crate::BitReader<bool>;
55#[doc = "Field `DST_MISAL` writer - N/A"]
56pub type DST_MISAL_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTR_MASK_SPEC, bool, O>;
57#[doc = "Field `CURR_PTR_NULL` reader - N/A"]
58pub type CURR_PTR_NULL_R = crate::BitReader<bool>;
59#[doc = "Field `CURR_PTR_NULL` writer - N/A"]
60pub type CURR_PTR_NULL_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTR_MASK_SPEC, bool, O>;
61#[doc = "Field `ACTIVE_CH_DISABLED` reader - N/A"]
62pub type ACTIVE_CH_DISABLED_R = crate::BitReader<bool>;
63#[doc = "Field `ACTIVE_CH_DISABLED` writer - N/A"]
64pub type ACTIVE_CH_DISABLED_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTR_MASK_SPEC, bool, O>;
65#[doc = "Field `DESCR_BUS_ERROR` reader - N/A"]
66pub type DESCR_BUS_ERROR_R = crate::BitReader<bool>;
67#[doc = "Field `DESCR_BUS_ERROR` writer - N/A"]
68pub type DESCR_BUS_ERROR_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTR_MASK_SPEC, bool, O>;
69impl R {
70    #[doc = "Bit 0 - Mask for corresponding field in INTR register."]
71    #[inline(always)]
72    pub fn completion(&self) -> COMPLETION_R {
73        COMPLETION_R::new((self.bits & 1) != 0)
74    }
75    #[doc = "Bit 1 - N/A"]
76    #[inline(always)]
77    pub fn src_bus_error(&self) -> SRC_BUS_ERROR_R {
78        SRC_BUS_ERROR_R::new(((self.bits >> 1) & 1) != 0)
79    }
80    #[doc = "Bit 2 - N/A"]
81    #[inline(always)]
82    pub fn dst_bus_error(&self) -> DST_BUS_ERROR_R {
83        DST_BUS_ERROR_R::new(((self.bits >> 2) & 1) != 0)
84    }
85    #[doc = "Bit 3 - N/A"]
86    #[inline(always)]
87    pub fn src_misal(&self) -> SRC_MISAL_R {
88        SRC_MISAL_R::new(((self.bits >> 3) & 1) != 0)
89    }
90    #[doc = "Bit 4 - N/A"]
91    #[inline(always)]
92    pub fn dst_misal(&self) -> DST_MISAL_R {
93        DST_MISAL_R::new(((self.bits >> 4) & 1) != 0)
94    }
95    #[doc = "Bit 5 - N/A"]
96    #[inline(always)]
97    pub fn curr_ptr_null(&self) -> CURR_PTR_NULL_R {
98        CURR_PTR_NULL_R::new(((self.bits >> 5) & 1) != 0)
99    }
100    #[doc = "Bit 6 - N/A"]
101    #[inline(always)]
102    pub fn active_ch_disabled(&self) -> ACTIVE_CH_DISABLED_R {
103        ACTIVE_CH_DISABLED_R::new(((self.bits >> 6) & 1) != 0)
104    }
105    #[doc = "Bit 7 - N/A"]
106    #[inline(always)]
107    pub fn descr_bus_error(&self) -> DESCR_BUS_ERROR_R {
108        DESCR_BUS_ERROR_R::new(((self.bits >> 7) & 1) != 0)
109    }
110}
111impl W {
112    #[doc = "Bit 0 - Mask for corresponding field in INTR register."]
113    #[inline(always)]
114    #[must_use]
115    pub fn completion(&mut self) -> COMPLETION_W<0> {
116        COMPLETION_W::new(self)
117    }
118    #[doc = "Bit 1 - N/A"]
119    #[inline(always)]
120    #[must_use]
121    pub fn src_bus_error(&mut self) -> SRC_BUS_ERROR_W<1> {
122        SRC_BUS_ERROR_W::new(self)
123    }
124    #[doc = "Bit 2 - N/A"]
125    #[inline(always)]
126    #[must_use]
127    pub fn dst_bus_error(&mut self) -> DST_BUS_ERROR_W<2> {
128        DST_BUS_ERROR_W::new(self)
129    }
130    #[doc = "Bit 3 - N/A"]
131    #[inline(always)]
132    #[must_use]
133    pub fn src_misal(&mut self) -> SRC_MISAL_W<3> {
134        SRC_MISAL_W::new(self)
135    }
136    #[doc = "Bit 4 - N/A"]
137    #[inline(always)]
138    #[must_use]
139    pub fn dst_misal(&mut self) -> DST_MISAL_W<4> {
140        DST_MISAL_W::new(self)
141    }
142    #[doc = "Bit 5 - N/A"]
143    #[inline(always)]
144    #[must_use]
145    pub fn curr_ptr_null(&mut self) -> CURR_PTR_NULL_W<5> {
146        CURR_PTR_NULL_W::new(self)
147    }
148    #[doc = "Bit 6 - N/A"]
149    #[inline(always)]
150    #[must_use]
151    pub fn active_ch_disabled(&mut self) -> ACTIVE_CH_DISABLED_W<6> {
152        ACTIVE_CH_DISABLED_W::new(self)
153    }
154    #[doc = "Bit 7 - N/A"]
155    #[inline(always)]
156    #[must_use]
157    pub fn descr_bus_error(&mut self) -> DESCR_BUS_ERROR_W<7> {
158        DESCR_BUS_ERROR_W::new(self)
159    }
160    #[doc = "Writes raw bits to the register."]
161    #[inline(always)]
162    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
163        self.0.bits(bits);
164        self
165    }
166}
167#[doc = "Interrupt mask\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intr_mask](index.html) module"]
168pub struct INTR_MASK_SPEC;
169impl crate::RegisterSpec for INTR_MASK_SPEC {
170    type Ux = u32;
171}
172#[doc = "`read()` method returns [intr_mask::R](R) reader structure"]
173impl crate::Readable for INTR_MASK_SPEC {
174    type Reader = R;
175}
176#[doc = "`write(|w| ..)` method takes [intr_mask::W](W) writer structure"]
177impl crate::Writable for INTR_MASK_SPEC {
178    type Writer = W;
179    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
180    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
181}
182#[doc = "`reset()` method sets INTR_MASK to value 0"]
183impl crate::Resettable for INTR_MASK_SPEC {
184    const RESET_VALUE: Self::Ux = 0;
185}
cyt3bb_a/m0/dmac/ch/intr_mask.rs

cyt3bb_a/m0/dmac/ch/
intr_mask.rs
