cyt3bb_a/m0/cpuss/
trim_ram200_ctl.rs

1#[doc = "Register `TRIM_RAM200_CTL` reader"]
2pub struct R(crate::R<TRIM_RAM200_CTL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<TRIM_RAM200_CTL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<TRIM_RAM200_CTL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<TRIM_RAM200_CTL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `TRIM_RAM200_CTL` writer"]
17pub struct W(crate::W<TRIM_RAM200_CTL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<TRIM_RAM200_CTL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<TRIM_RAM200_CTL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<TRIM_RAM200_CTL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `TRIM` reader - See TRIM_RAM_CTL for description. System SRAM memories (SRAM0,1,2) are connected to this register. System SRAM0 uses bias control power switch,so bits \\[7:5\\]
38of this register controls the bias pins of the SRAM0 power switch."]
39pub type TRIM_R = crate::FieldReader<u32, u32>;
40#[doc = "Field `TRIM` writer - See TRIM_RAM_CTL for description. System SRAM memories (SRAM0,1,2) are connected to this register. System SRAM0 uses bias control power switch,so bits \\[7:5\\]
41of this register controls the bias pins of the SRAM0 power switch."]
42pub type TRIM_W<'a, const O: u8> =
43    crate::FieldWriter<'a, u32, TRIM_RAM200_CTL_SPEC, u32, u32, 32, O>;
44impl R {
45    #[doc = "Bits 0:31 - See TRIM_RAM_CTL for description. System SRAM memories (SRAM0,1,2) are connected to this register. System SRAM0 uses bias control power switch,so bits \\[7:5\\]
46of this register controls the bias pins of the SRAM0 power switch."]
47    #[inline(always)]
48    pub fn trim(&self) -> TRIM_R {
49        TRIM_R::new(self.bits)
50    }
51}
52impl W {
53    #[doc = "Bits 0:31 - See TRIM_RAM_CTL for description. System SRAM memories (SRAM0,1,2) are connected to this register. System SRAM0 uses bias control power switch,so bits \\[7:5\\]
54of this register controls the bias pins of the SRAM0 power switch."]
55    #[inline(always)]
56    #[must_use]
57    pub fn trim(&mut self) -> TRIM_W<0> {
58        TRIM_W::new(self)
59    }
60    #[doc = "Writes raw bits to the register."]
61    #[inline(always)]
62    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
63        self.0.bits(bits);
64        self
65    }
66}
67#[doc = "RAM trim control for 100MHz - 200MHz SRAMs\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [trim_ram200_ctl](index.html) module"]
68pub struct TRIM_RAM200_CTL_SPEC;
69impl crate::RegisterSpec for TRIM_RAM200_CTL_SPEC {
70    type Ux = u32;
71}
72#[doc = "`read()` method returns [trim_ram200_ctl::R](R) reader structure"]
73impl crate::Readable for TRIM_RAM200_CTL_SPEC {
74    type Reader = R;
75}
76#[doc = "`write(|w| ..)` method takes [trim_ram200_ctl::W](W) writer structure"]
77impl crate::Writable for TRIM_RAM200_CTL_SPEC {
78    type Writer = W;
79    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
80    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
81}
82#[doc = "`reset()` method sets TRIM_RAM200_CTL to value 0"]
83impl crate::Resettable for TRIM_RAM200_CTL_SPEC {
84    const RESET_VALUE: Self::Ux = 0;
85}
cyt3bb_a/m0/cpuss/trim_ram200_ctl.rs

cyt3bb_a/m0/cpuss/
trim_ram200_ctl.rs
