cyt3bb_a/m0/cpuss/
cm7_1_ctl.rs

1#[doc = "Register `CM7_1_CTL` reader"]
2pub struct R(crate::R<CM7_1_CTL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CM7_1_CTL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CM7_1_CTL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CM7_1_CTL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `CM7_1_CTL` writer"]
17pub struct W(crate::W<CM7_1_CTL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CM7_1_CTL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CM7_1_CTL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CM7_1_CTL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `PPB_LOCK` reader - Refer CM7_0_CTL description."]
38pub type PPB_LOCK_R = crate::FieldReader<u8, u8>;
39#[doc = "Field `PPB_LOCK` writer - Refer CM7_0_CTL description."]
40pub type PPB_LOCK_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CM7_1_CTL_SPEC, u8, u8, 4, O>;
41#[doc = "Field `CPU_WAIT` reader - Refer CM7_0_CTL description."]
42pub type CPU_WAIT_R = crate::BitReader<bool>;
43#[doc = "Field `CPU_WAIT` writer - Refer CM7_0_CTL description."]
44pub type CPU_WAIT_W<'a, const O: u8> = crate::BitWriter<'a, u32, CM7_1_CTL_SPEC, bool, O>;
45#[doc = "Field `INIT_TCM_EN` reader - Refer CM7_0_CTL description."]
46pub type INIT_TCM_EN_R = crate::FieldReader<u8, u8>;
47#[doc = "Field `INIT_TCM_EN` writer - Refer CM7_0_CTL description."]
48pub type INIT_TCM_EN_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CM7_1_CTL_SPEC, u8, u8, 2, O>;
49#[doc = "Field `INIT_RMW_EN` reader - Refer CM7_0_CTL description."]
50pub type INIT_RMW_EN_R = crate::FieldReader<u8, u8>;
51#[doc = "Field `INIT_RMW_EN` writer - Refer CM7_0_CTL description."]
52pub type INIT_RMW_EN_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CM7_1_CTL_SPEC, u8, u8, 2, O>;
53#[doc = "Field `ITCM_ECC_EN` reader - Refer CM7_0_CTL description."]
54pub type ITCM_ECC_EN_R = crate::BitReader<bool>;
55#[doc = "Field `ITCM_ECC_EN` writer - Refer CM7_0_CTL description."]
56pub type ITCM_ECC_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CM7_1_CTL_SPEC, bool, O>;
57#[doc = "Field `ITCM_ECC_INJ_EN` reader - Refer CM7_0_CTL description."]
58pub type ITCM_ECC_INJ_EN_R = crate::BitReader<bool>;
59#[doc = "Field `ITCM_ECC_INJ_EN` writer - Refer CM7_0_CTL description."]
60pub type ITCM_ECC_INJ_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CM7_1_CTL_SPEC, bool, O>;
61#[doc = "Field `ITCM_READ_WS` reader - Refer CM7_0_CTL description."]
62pub type ITCM_READ_WS_R = crate::BitReader<bool>;
63#[doc = "Field `ITCM_READ_WS` writer - Refer CM7_0_CTL description."]
64pub type ITCM_READ_WS_W<'a, const O: u8> = crate::BitWriter<'a, u32, CM7_1_CTL_SPEC, bool, O>;
65#[doc = "Field `ITCM_ECC_CHECK_DIS` reader - Disable ECC checking and thus fault reports. This also disables ECC correction (required to enable initialization). Intended usage is initialization. This bit is ignored when TCM_ECC_EN=0."]
66pub type ITCM_ECC_CHECK_DIS_R = crate::BitReader<bool>;
67#[doc = "Field `ITCM_ECC_CHECK_DIS` writer - Disable ECC checking and thus fault reports. This also disables ECC correction (required to enable initialization). Intended usage is initialization. This bit is ignored when TCM_ECC_EN=0."]
68pub type ITCM_ECC_CHECK_DIS_W<'a, const O: u8> = crate::BitWriter<'a, u32, CM7_1_CTL_SPEC, bool, O>;
69#[doc = "Field `DTCM_ECC_EN` reader - Refer CM7_0_CTL description."]
70pub type DTCM_ECC_EN_R = crate::BitReader<bool>;
71#[doc = "Field `DTCM_ECC_EN` writer - Refer CM7_0_CTL description."]
72pub type DTCM_ECC_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CM7_1_CTL_SPEC, bool, O>;
73#[doc = "Field `DTCM_ECC_INJ_EN` reader - Refer CM7_0_CTL description."]
74pub type DTCM_ECC_INJ_EN_R = crate::BitReader<bool>;
75#[doc = "Field `DTCM_ECC_INJ_EN` writer - Refer CM7_0_CTL description."]
76pub type DTCM_ECC_INJ_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CM7_1_CTL_SPEC, bool, O>;
77#[doc = "Field `DTCM_READ_WS` reader - Refer CM7_0_CTL description."]
78pub type DTCM_READ_WS_R = crate::BitReader<bool>;
79#[doc = "Field `DTCM_READ_WS` writer - Refer CM7_0_CTL description."]
80pub type DTCM_READ_WS_W<'a, const O: u8> = crate::BitWriter<'a, u32, CM7_1_CTL_SPEC, bool, O>;
81#[doc = "Field `TCMC_EN` reader - Refer CM7_0_CTL description."]
82pub type TCMC_EN_R = crate::BitReader<bool>;
83#[doc = "Field `TCMC_EN` writer - Refer CM7_0_CTL description."]
84pub type TCMC_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CM7_1_CTL_SPEC, bool, O>;
85#[doc = "Field `IOC_MASK` reader - Refer CM7_0_CTL description."]
86pub type IOC_MASK_R = crate::BitReader<bool>;
87#[doc = "Field `IOC_MASK` writer - Refer CM7_0_CTL description."]
88pub type IOC_MASK_W<'a, const O: u8> = crate::BitWriter<'a, u32, CM7_1_CTL_SPEC, bool, O>;
89#[doc = "Field `DZC_MASK` reader - Refer CM7_0_CTL description."]
90pub type DZC_MASK_R = crate::BitReader<bool>;
91#[doc = "Field `DZC_MASK` writer - Refer CM7_0_CTL description."]
92pub type DZC_MASK_W<'a, const O: u8> = crate::BitWriter<'a, u32, CM7_1_CTL_SPEC, bool, O>;
93#[doc = "Field `OFC_MASK` reader - Refer CM7_0_CTL description."]
94pub type OFC_MASK_R = crate::BitReader<bool>;
95#[doc = "Field `OFC_MASK` writer - Refer CM7_0_CTL description."]
96pub type OFC_MASK_W<'a, const O: u8> = crate::BitWriter<'a, u32, CM7_1_CTL_SPEC, bool, O>;
97#[doc = "Field `UFC_MASK` reader - Refer CM7_0_CTL description."]
98pub type UFC_MASK_R = crate::BitReader<bool>;
99#[doc = "Field `UFC_MASK` writer - Refer CM7_0_CTL description."]
100pub type UFC_MASK_W<'a, const O: u8> = crate::BitWriter<'a, u32, CM7_1_CTL_SPEC, bool, O>;
101#[doc = "Field `IXC_MASK` reader - Refer CM7_0_CTL description."]
102pub type IXC_MASK_R = crate::BitReader<bool>;
103#[doc = "Field `IXC_MASK` writer - Refer CM7_0_CTL description."]
104pub type IXC_MASK_W<'a, const O: u8> = crate::BitWriter<'a, u32, CM7_1_CTL_SPEC, bool, O>;
105#[doc = "Field `IDC_MASK` reader - Refer CM7_0_CTL description."]
106pub type IDC_MASK_R = crate::BitReader<bool>;
107#[doc = "Field `IDC_MASK` writer - Refer CM7_0_CTL description."]
108pub type IDC_MASK_W<'a, const O: u8> = crate::BitWriter<'a, u32, CM7_1_CTL_SPEC, bool, O>;
109impl R {
110    #[doc = "Bits 0:3 - Refer CM7_0_CTL description."]
111    #[inline(always)]
112    pub fn ppb_lock(&self) -> PPB_LOCK_R {
113        PPB_LOCK_R::new((self.bits & 0x0f) as u8)
114    }
115    #[doc = "Bit 4 - Refer CM7_0_CTL description."]
116    #[inline(always)]
117    pub fn cpu_wait(&self) -> CPU_WAIT_R {
118        CPU_WAIT_R::new(((self.bits >> 4) & 1) != 0)
119    }
120    #[doc = "Bits 8:9 - Refer CM7_0_CTL description."]
121    #[inline(always)]
122    pub fn init_tcm_en(&self) -> INIT_TCM_EN_R {
123        INIT_TCM_EN_R::new(((self.bits >> 8) & 3) as u8)
124    }
125    #[doc = "Bits 10:11 - Refer CM7_0_CTL description."]
126    #[inline(always)]
127    pub fn init_rmw_en(&self) -> INIT_RMW_EN_R {
128        INIT_RMW_EN_R::new(((self.bits >> 10) & 3) as u8)
129    }
130    #[doc = "Bit 16 - Refer CM7_0_CTL description."]
131    #[inline(always)]
132    pub fn itcm_ecc_en(&self) -> ITCM_ECC_EN_R {
133        ITCM_ECC_EN_R::new(((self.bits >> 16) & 1) != 0)
134    }
135    #[doc = "Bit 17 - Refer CM7_0_CTL description."]
136    #[inline(always)]
137    pub fn itcm_ecc_inj_en(&self) -> ITCM_ECC_INJ_EN_R {
138        ITCM_ECC_INJ_EN_R::new(((self.bits >> 17) & 1) != 0)
139    }
140    #[doc = "Bit 18 - Refer CM7_0_CTL description."]
141    #[inline(always)]
142    pub fn itcm_read_ws(&self) -> ITCM_READ_WS_R {
143        ITCM_READ_WS_R::new(((self.bits >> 18) & 1) != 0)
144    }
145    #[doc = "Bit 19 - Disable ECC checking and thus fault reports. This also disables ECC correction (required to enable initialization). Intended usage is initialization. This bit is ignored when TCM_ECC_EN=0."]
146    #[inline(always)]
147    pub fn itcm_ecc_check_dis(&self) -> ITCM_ECC_CHECK_DIS_R {
148        ITCM_ECC_CHECK_DIS_R::new(((self.bits >> 19) & 1) != 0)
149    }
150    #[doc = "Bit 20 - Refer CM7_0_CTL description."]
151    #[inline(always)]
152    pub fn dtcm_ecc_en(&self) -> DTCM_ECC_EN_R {
153        DTCM_ECC_EN_R::new(((self.bits >> 20) & 1) != 0)
154    }
155    #[doc = "Bit 21 - Refer CM7_0_CTL description."]
156    #[inline(always)]
157    pub fn dtcm_ecc_inj_en(&self) -> DTCM_ECC_INJ_EN_R {
158        DTCM_ECC_INJ_EN_R::new(((self.bits >> 21) & 1) != 0)
159    }
160    #[doc = "Bit 22 - Refer CM7_0_CTL description."]
161    #[inline(always)]
162    pub fn dtcm_read_ws(&self) -> DTCM_READ_WS_R {
163        DTCM_READ_WS_R::new(((self.bits >> 22) & 1) != 0)
164    }
165    #[doc = "Bit 23 - Refer CM7_0_CTL description."]
166    #[inline(always)]
167    pub fn tcmc_en(&self) -> TCMC_EN_R {
168        TCMC_EN_R::new(((self.bits >> 23) & 1) != 0)
169    }
170    #[doc = "Bit 24 - Refer CM7_0_CTL description."]
171    #[inline(always)]
172    pub fn ioc_mask(&self) -> IOC_MASK_R {
173        IOC_MASK_R::new(((self.bits >> 24) & 1) != 0)
174    }
175    #[doc = "Bit 25 - Refer CM7_0_CTL description."]
176    #[inline(always)]
177    pub fn dzc_mask(&self) -> DZC_MASK_R {
178        DZC_MASK_R::new(((self.bits >> 25) & 1) != 0)
179    }
180    #[doc = "Bit 26 - Refer CM7_0_CTL description."]
181    #[inline(always)]
182    pub fn ofc_mask(&self) -> OFC_MASK_R {
183        OFC_MASK_R::new(((self.bits >> 26) & 1) != 0)
184    }
185    #[doc = "Bit 27 - Refer CM7_0_CTL description."]
186    #[inline(always)]
187    pub fn ufc_mask(&self) -> UFC_MASK_R {
188        UFC_MASK_R::new(((self.bits >> 27) & 1) != 0)
189    }
190    #[doc = "Bit 28 - Refer CM7_0_CTL description."]
191    #[inline(always)]
192    pub fn ixc_mask(&self) -> IXC_MASK_R {
193        IXC_MASK_R::new(((self.bits >> 28) & 1) != 0)
194    }
195    #[doc = "Bit 31 - Refer CM7_0_CTL description."]
196    #[inline(always)]
197    pub fn idc_mask(&self) -> IDC_MASK_R {
198        IDC_MASK_R::new(((self.bits >> 31) & 1) != 0)
199    }
200}
201impl W {
202    #[doc = "Bits 0:3 - Refer CM7_0_CTL description."]
203    #[inline(always)]
204    #[must_use]
205    pub fn ppb_lock(&mut self) -> PPB_LOCK_W<0> {
206        PPB_LOCK_W::new(self)
207    }
208    #[doc = "Bit 4 - Refer CM7_0_CTL description."]
209    #[inline(always)]
210    #[must_use]
211    pub fn cpu_wait(&mut self) -> CPU_WAIT_W<4> {
212        CPU_WAIT_W::new(self)
213    }
214    #[doc = "Bits 8:9 - Refer CM7_0_CTL description."]
215    #[inline(always)]
216    #[must_use]
217    pub fn init_tcm_en(&mut self) -> INIT_TCM_EN_W<8> {
218        INIT_TCM_EN_W::new(self)
219    }
220    #[doc = "Bits 10:11 - Refer CM7_0_CTL description."]
221    #[inline(always)]
222    #[must_use]
223    pub fn init_rmw_en(&mut self) -> INIT_RMW_EN_W<10> {
224        INIT_RMW_EN_W::new(self)
225    }
226    #[doc = "Bit 16 - Refer CM7_0_CTL description."]
227    #[inline(always)]
228    #[must_use]
229    pub fn itcm_ecc_en(&mut self) -> ITCM_ECC_EN_W<16> {
230        ITCM_ECC_EN_W::new(self)
231    }
232    #[doc = "Bit 17 - Refer CM7_0_CTL description."]
233    #[inline(always)]
234    #[must_use]
235    pub fn itcm_ecc_inj_en(&mut self) -> ITCM_ECC_INJ_EN_W<17> {
236        ITCM_ECC_INJ_EN_W::new(self)
237    }
238    #[doc = "Bit 18 - Refer CM7_0_CTL description."]
239    #[inline(always)]
240    #[must_use]
241    pub fn itcm_read_ws(&mut self) -> ITCM_READ_WS_W<18> {
242        ITCM_READ_WS_W::new(self)
243    }
244    #[doc = "Bit 19 - Disable ECC checking and thus fault reports. This also disables ECC correction (required to enable initialization). Intended usage is initialization. This bit is ignored when TCM_ECC_EN=0."]
245    #[inline(always)]
246    #[must_use]
247    pub fn itcm_ecc_check_dis(&mut self) -> ITCM_ECC_CHECK_DIS_W<19> {
248        ITCM_ECC_CHECK_DIS_W::new(self)
249    }
250    #[doc = "Bit 20 - Refer CM7_0_CTL description."]
251    #[inline(always)]
252    #[must_use]
253    pub fn dtcm_ecc_en(&mut self) -> DTCM_ECC_EN_W<20> {
254        DTCM_ECC_EN_W::new(self)
255    }
256    #[doc = "Bit 21 - Refer CM7_0_CTL description."]
257    #[inline(always)]
258    #[must_use]
259    pub fn dtcm_ecc_inj_en(&mut self) -> DTCM_ECC_INJ_EN_W<21> {
260        DTCM_ECC_INJ_EN_W::new(self)
261    }
262    #[doc = "Bit 22 - Refer CM7_0_CTL description."]
263    #[inline(always)]
264    #[must_use]
265    pub fn dtcm_read_ws(&mut self) -> DTCM_READ_WS_W<22> {
266        DTCM_READ_WS_W::new(self)
267    }
268    #[doc = "Bit 23 - Refer CM7_0_CTL description."]
269    #[inline(always)]
270    #[must_use]
271    pub fn tcmc_en(&mut self) -> TCMC_EN_W<23> {
272        TCMC_EN_W::new(self)
273    }
274    #[doc = "Bit 24 - Refer CM7_0_CTL description."]
275    #[inline(always)]
276    #[must_use]
277    pub fn ioc_mask(&mut self) -> IOC_MASK_W<24> {
278        IOC_MASK_W::new(self)
279    }
280    #[doc = "Bit 25 - Refer CM7_0_CTL description."]
281    #[inline(always)]
282    #[must_use]
283    pub fn dzc_mask(&mut self) -> DZC_MASK_W<25> {
284        DZC_MASK_W::new(self)
285    }
286    #[doc = "Bit 26 - Refer CM7_0_CTL description."]
287    #[inline(always)]
288    #[must_use]
289    pub fn ofc_mask(&mut self) -> OFC_MASK_W<26> {
290        OFC_MASK_W::new(self)
291    }
292    #[doc = "Bit 27 - Refer CM7_0_CTL description."]
293    #[inline(always)]
294    #[must_use]
295    pub fn ufc_mask(&mut self) -> UFC_MASK_W<27> {
296        UFC_MASK_W::new(self)
297    }
298    #[doc = "Bit 28 - Refer CM7_0_CTL description."]
299    #[inline(always)]
300    #[must_use]
301    pub fn ixc_mask(&mut self) -> IXC_MASK_W<28> {
302        IXC_MASK_W::new(self)
303    }
304    #[doc = "Bit 31 - Refer CM7_0_CTL description."]
305    #[inline(always)]
306    #[must_use]
307    pub fn idc_mask(&mut self) -> IDC_MASK_W<31> {
308        IDC_MASK_W::new(self)
309    }
310    #[doc = "Writes raw bits to the register."]
311    #[inline(always)]
312    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
313        self.0.bits(bits);
314        self
315    }
316}
317#[doc = "CM7 1 control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cm7_1_ctl](index.html) module"]
318pub struct CM7_1_CTL_SPEC;
319impl crate::RegisterSpec for CM7_1_CTL_SPEC {
320    type Ux = u32;
321}
322#[doc = "`read()` method returns [cm7_1_ctl::R](R) reader structure"]
323impl crate::Readable for CM7_1_CTL_SPEC {
324    type Reader = R;
325}
326#[doc = "`write(|w| ..)` method takes [cm7_1_ctl::W](W) writer structure"]
327impl crate::Writable for CM7_1_CTL_SPEC {
328    type Writer = W;
329    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
330    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
331}
332#[doc = "`reset()` method sets CM7_1_CTL to value 0x1f"]
333impl crate::Resettable for CM7_1_CTL_SPEC {
334    const RESET_VALUE: Self::Ux = 0x1f;
335}
cyt3bb_a/m0/cpuss/cm7_1_ctl.rs

cyt3bb_a/m0/cpuss/
cm7_1_ctl.rs
