cyt3bb_a/m0/cpuss/
cm0_system_int_ctl.rs

1#[doc = "Register `CM0_SYSTEM_INT_CTL[%s]` reader"]
2pub struct R(crate::R<CM0_SYSTEM_INT_CTL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CM0_SYSTEM_INT_CTL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CM0_SYSTEM_INT_CTL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CM0_SYSTEM_INT_CTL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `CM0_SYSTEM_INT_CTL[%s]` writer"]
17pub struct W(crate::W<CM0_SYSTEM_INT_CTL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CM0_SYSTEM_INT_CTL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CM0_SYSTEM_INT_CTL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CM0_SYSTEM_INT_CTL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `CM0_CPU_INT_IDX` reader - CPU interrupt index (legal range \\[0, 7\\]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly."]
38pub type CM0_CPU_INT_IDX_R = crate::FieldReader<u8, u8>;
39#[doc = "Field `CM0_CPU_INT_IDX` writer - CPU interrupt index (legal range \\[0, 7\\]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly."]
40pub type CM0_CPU_INT_IDX_W<'a, const O: u8> =
41    crate::FieldWriter<'a, u32, CM0_SYSTEM_INT_CTL_SPEC, u8, u8, 3, O>;
42#[doc = "Field `CPU_INT_VALID` reader - Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'."]
43pub type CPU_INT_VALID_R = crate::BitReader<bool>;
44#[doc = "Field `CPU_INT_VALID` writer - Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'."]
45pub type CPU_INT_VALID_W<'a, const O: u8> =
46    crate::BitWriter<'a, u32, CM0_SYSTEM_INT_CTL_SPEC, bool, O>;
47impl R {
48    #[doc = "Bits 0:2 - CPU interrupt index (legal range \\[0, 7\\]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly."]
49    #[inline(always)]
50    pub fn cm0_cpu_int_idx(&self) -> CM0_CPU_INT_IDX_R {
51        CM0_CPU_INT_IDX_R::new((self.bits & 7) as u8)
52    }
53    #[doc = "Bit 31 - Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'."]
54    #[inline(always)]
55    pub fn cpu_int_valid(&self) -> CPU_INT_VALID_R {
56        CPU_INT_VALID_R::new(((self.bits >> 31) & 1) != 0)
57    }
58}
59impl W {
60    #[doc = "Bits 0:2 - CPU interrupt index (legal range \\[0, 7\\]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'. Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly."]
61    #[inline(always)]
62    #[must_use]
63    pub fn cm0_cpu_int_idx(&mut self) -> CM0_CPU_INT_IDX_W<0> {
64        CM0_CPU_INT_IDX_W::new(self)
65    }
66    #[doc = "Bit 31 - Interrupt enable: '0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt. '1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX. Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'."]
67    #[inline(always)]
68    #[must_use]
69    pub fn cpu_int_valid(&mut self) -> CPU_INT_VALID_W<31> {
70        CPU_INT_VALID_W::new(self)
71    }
72    #[doc = "Writes raw bits to the register."]
73    #[inline(always)]
74    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
75        self.0.bits(bits);
76        self
77    }
78}
79#[doc = "CM0+ system interrupt control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cm0_system_int_ctl](index.html) module"]
80pub struct CM0_SYSTEM_INT_CTL_SPEC;
81impl crate::RegisterSpec for CM0_SYSTEM_INT_CTL_SPEC {
82    type Ux = u32;
83}
84#[doc = "`read()` method returns [cm0_system_int_ctl::R](R) reader structure"]
85impl crate::Readable for CM0_SYSTEM_INT_CTL_SPEC {
86    type Reader = R;
87}
88#[doc = "`write(|w| ..)` method takes [cm0_system_int_ctl::W](W) writer structure"]
89impl crate::Writable for CM0_SYSTEM_INT_CTL_SPEC {
90    type Writer = W;
91    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
92    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
93}
94#[doc = "`reset()` method sets CM0_SYSTEM_INT_CTL[%s]
95to value 0"]
96impl crate::Resettable for CM0_SYSTEM_INT_CTL_SPEC {
97    const RESET_VALUE: Self::Ux = 0;
98}
cyt3bb_a/m0/cpuss/cm0_system_int_ctl.rs

cyt3bb_a/m0/cpuss/
cm0_system_int_ctl.rs
