cyt2cl_a/m0/tdm0/tdm_struct/
tdm_tx_struct.rs

1#[doc = r"Register block"]
2#[repr(C)]
3pub struct TDM_TX_STRUCT {
4    #[doc = "0x00 - TX control"]
5    pub tx_ctl: TX_CTL,
6    _reserved1: [u8; 0x0c],
7    #[doc = "0x10 - TX interface control"]
8    pub tx_if_ctl: TX_IF_CTL,
9    #[doc = "0x14 - TX channel control"]
10    pub tx_ch_ctl: TX_CH_CTL,
11    _reserved3: [u8; 0x08],
12    #[doc = "0x20 - TX test control"]
13    pub tx_test_ctl: TX_TEST_CTL,
14    #[doc = "0x24 - TX route control"]
15    pub tx_route_ctl: TX_ROUTE_CTL,
16    _reserved5: [u8; 0x58],
17    #[doc = "0x80 - TX FIFO control"]
18    pub tx_fifo_ctl: TX_FIFO_CTL,
19    #[doc = "0x84 - TX FIFO status"]
20    pub tx_fifo_status: TX_FIFO_STATUS,
21    #[doc = "0x88 - TX FIFO write"]
22    pub tx_fifo_wr: TX_FIFO_WR,
23    _reserved8: [u8; 0x34],
24    #[doc = "0xc0 - Interrupt"]
25    pub intr_tx: INTR_TX,
26    #[doc = "0xc4 - Interrupt set"]
27    pub intr_tx_set: INTR_TX_SET,
28    #[doc = "0xc8 - Interrupt mask"]
29    pub intr_tx_mask: INTR_TX_MASK,
30    #[doc = "0xcc - Interrupt masked"]
31    pub intr_tx_masked: INTR_TX_MASKED,
32}
33#[doc = "TX_CTL (rw) register accessor: an alias for `Reg<TX_CTL_SPEC>`"]
34pub type TX_CTL = crate::Reg<tx_ctl::TX_CTL_SPEC>;
35#[doc = "TX control"]
36pub mod tx_ctl;
37#[doc = "TX_IF_CTL (rw) register accessor: an alias for `Reg<TX_IF_CTL_SPEC>`"]
38pub type TX_IF_CTL = crate::Reg<tx_if_ctl::TX_IF_CTL_SPEC>;
39#[doc = "TX interface control"]
40pub mod tx_if_ctl;
41#[doc = "TX_CH_CTL (rw) register accessor: an alias for `Reg<TX_CH_CTL_SPEC>`"]
42pub type TX_CH_CTL = crate::Reg<tx_ch_ctl::TX_CH_CTL_SPEC>;
43#[doc = "TX channel control"]
44pub mod tx_ch_ctl;
45#[doc = "TX_TEST_CTL (rw) register accessor: an alias for `Reg<TX_TEST_CTL_SPEC>`"]
46pub type TX_TEST_CTL = crate::Reg<tx_test_ctl::TX_TEST_CTL_SPEC>;
47#[doc = "TX test control"]
48pub mod tx_test_ctl;
49#[doc = "TX_ROUTE_CTL (rw) register accessor: an alias for `Reg<TX_ROUTE_CTL_SPEC>`"]
50pub type TX_ROUTE_CTL = crate::Reg<tx_route_ctl::TX_ROUTE_CTL_SPEC>;
51#[doc = "TX route control"]
52pub mod tx_route_ctl;
53#[doc = "TX_FIFO_CTL (rw) register accessor: an alias for `Reg<TX_FIFO_CTL_SPEC>`"]
54pub type TX_FIFO_CTL = crate::Reg<tx_fifo_ctl::TX_FIFO_CTL_SPEC>;
55#[doc = "TX FIFO control"]
56pub mod tx_fifo_ctl;
57#[doc = "TX_FIFO_STATUS (r) register accessor: an alias for `Reg<TX_FIFO_STATUS_SPEC>`"]
58pub type TX_FIFO_STATUS = crate::Reg<tx_fifo_status::TX_FIFO_STATUS_SPEC>;
59#[doc = "TX FIFO status"]
60pub mod tx_fifo_status;
61#[doc = "TX_FIFO_WR (w) register accessor: an alias for `Reg<TX_FIFO_WR_SPEC>`"]
62pub type TX_FIFO_WR = crate::Reg<tx_fifo_wr::TX_FIFO_WR_SPEC>;
63#[doc = "TX FIFO write"]
64pub mod tx_fifo_wr;
65#[doc = "INTR_TX (rw) register accessor: an alias for `Reg<INTR_TX_SPEC>`"]
66pub type INTR_TX = crate::Reg<intr_tx::INTR_TX_SPEC>;
67#[doc = "Interrupt"]
68pub mod intr_tx;
69#[doc = "INTR_TX_SET (rw) register accessor: an alias for `Reg<INTR_TX_SET_SPEC>`"]
70pub type INTR_TX_SET = crate::Reg<intr_tx_set::INTR_TX_SET_SPEC>;
71#[doc = "Interrupt set"]
72pub mod intr_tx_set;
73#[doc = "INTR_TX_MASK (rw) register accessor: an alias for `Reg<INTR_TX_MASK_SPEC>`"]
74pub type INTR_TX_MASK = crate::Reg<intr_tx_mask::INTR_TX_MASK_SPEC>;
75#[doc = "Interrupt mask"]
76pub mod intr_tx_mask;
77#[doc = "INTR_TX_MASKED (r) register accessor: an alias for `Reg<INTR_TX_MASKED_SPEC>`"]
78pub type INTR_TX_MASKED = crate::Reg<intr_tx_masked::INTR_TX_MASKED_SPEC>;
79#[doc = "Interrupt masked"]
80pub mod intr_tx_masked;
cyt2cl_a/m0/tdm0/tdm_struct/tdm_tx_struct.rs

cyt2cl_a/m0/tdm0/tdm_struct/
tdm_tx_struct.rs
