cyt2cl_a/m0/scb0/
uart_flow_ctrl.rs

1#[doc = "Register `UART_FLOW_CTRL` reader"]
2pub struct R(crate::R<UART_FLOW_CTRL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<UART_FLOW_CTRL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<UART_FLOW_CTRL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<UART_FLOW_CTRL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `UART_FLOW_CTRL` writer"]
17pub struct W(crate::W<UART_FLOW_CTRL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<UART_FLOW_CTRL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<UART_FLOW_CTRL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<UART_FLOW_CTRL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `TRIGGER_LEVEL` reader - Trigger level. When the receiver FIFO has less entries than the amount of this field, a Ready To Send (RTS) output signal is activated. By setting this field to '0', flow control is effectively disabled (may be useful for debug purposes)."]
38pub type TRIGGER_LEVEL_R = crate::FieldReader<u8, u8>;
39#[doc = "Field `TRIGGER_LEVEL` writer - Trigger level. When the receiver FIFO has less entries than the amount of this field, a Ready To Send (RTS) output signal is activated. By setting this field to '0', flow control is effectively disabled (may be useful for debug purposes)."]
40pub type TRIGGER_LEVEL_W<'a, const O: u8> =
41    crate::FieldWriter<'a, u32, UART_FLOW_CTRL_SPEC, u8, u8, 8, O>;
42#[doc = "Field `RTS_POLARITY` reader - Polarity of the RTS output signal: '0': RTS is active low; '1': RTS is active high; During SCB reset (Hibernate system power mode), RTS output signal is '1'. This represents an inactive state assuming an active low polarity."]
43pub type RTS_POLARITY_R = crate::BitReader<bool>;
44#[doc = "Field `RTS_POLARITY` writer - Polarity of the RTS output signal: '0': RTS is active low; '1': RTS is active high; During SCB reset (Hibernate system power mode), RTS output signal is '1'. This represents an inactive state assuming an active low polarity."]
45pub type RTS_POLARITY_W<'a, const O: u8> = crate::BitWriter<'a, u32, UART_FLOW_CTRL_SPEC, bool, O>;
46#[doc = "Field `CTS_POLARITY` reader - Polarity of the CTS input signal '0': CTS is active low ; '1': CTS is active high;"]
47pub type CTS_POLARITY_R = crate::BitReader<bool>;
48#[doc = "Field `CTS_POLARITY` writer - Polarity of the CTS input signal '0': CTS is active low ; '1': CTS is active high;"]
49pub type CTS_POLARITY_W<'a, const O: u8> = crate::BitWriter<'a, u32, UART_FLOW_CTRL_SPEC, bool, O>;
50#[doc = "Field `CTS_ENABLED` reader - Enable use of CTS input signal by the UART transmitter: '0': Disabled. The UART transmitter ignores the CTS input signal and transmits when a data frame is available for transmission in the TX FIFO or the TX shift register. '1': Enabled. The UART transmitter uses CTS input signal to qualify the transmission of data. It transmits when CTS input signal is active and a data frame is available for transmission in the TX FIFO or the TX shift register. If UART_CTRL.LOOPBACK is '1', the CTS input signal is driven by the RTS output signal locally in SCB (both signals are subjected to signal polarity changes are indicated by RTS_POLARITY and CTS_POLARITY)."]
51pub type CTS_ENABLED_R = crate::BitReader<bool>;
52#[doc = "Field `CTS_ENABLED` writer - Enable use of CTS input signal by the UART transmitter: '0': Disabled. The UART transmitter ignores the CTS input signal and transmits when a data frame is available for transmission in the TX FIFO or the TX shift register. '1': Enabled. The UART transmitter uses CTS input signal to qualify the transmission of data. It transmits when CTS input signal is active and a data frame is available for transmission in the TX FIFO or the TX shift register. If UART_CTRL.LOOPBACK is '1', the CTS input signal is driven by the RTS output signal locally in SCB (both signals are subjected to signal polarity changes are indicated by RTS_POLARITY and CTS_POLARITY)."]
53pub type CTS_ENABLED_W<'a, const O: u8> = crate::BitWriter<'a, u32, UART_FLOW_CTRL_SPEC, bool, O>;
54impl R {
55    #[doc = "Bits 0:7 - Trigger level. When the receiver FIFO has less entries than the amount of this field, a Ready To Send (RTS) output signal is activated. By setting this field to '0', flow control is effectively disabled (may be useful for debug purposes)."]
56    #[inline(always)]
57    pub fn trigger_level(&self) -> TRIGGER_LEVEL_R {
58        TRIGGER_LEVEL_R::new((self.bits & 0xff) as u8)
59    }
60    #[doc = "Bit 16 - Polarity of the RTS output signal: '0': RTS is active low; '1': RTS is active high; During SCB reset (Hibernate system power mode), RTS output signal is '1'. This represents an inactive state assuming an active low polarity."]
61    #[inline(always)]
62    pub fn rts_polarity(&self) -> RTS_POLARITY_R {
63        RTS_POLARITY_R::new(((self.bits >> 16) & 1) != 0)
64    }
65    #[doc = "Bit 24 - Polarity of the CTS input signal '0': CTS is active low ; '1': CTS is active high;"]
66    #[inline(always)]
67    pub fn cts_polarity(&self) -> CTS_POLARITY_R {
68        CTS_POLARITY_R::new(((self.bits >> 24) & 1) != 0)
69    }
70    #[doc = "Bit 25 - Enable use of CTS input signal by the UART transmitter: '0': Disabled. The UART transmitter ignores the CTS input signal and transmits when a data frame is available for transmission in the TX FIFO or the TX shift register. '1': Enabled. The UART transmitter uses CTS input signal to qualify the transmission of data. It transmits when CTS input signal is active and a data frame is available for transmission in the TX FIFO or the TX shift register. If UART_CTRL.LOOPBACK is '1', the CTS input signal is driven by the RTS output signal locally in SCB (both signals are subjected to signal polarity changes are indicated by RTS_POLARITY and CTS_POLARITY)."]
71    #[inline(always)]
72    pub fn cts_enabled(&self) -> CTS_ENABLED_R {
73        CTS_ENABLED_R::new(((self.bits >> 25) & 1) != 0)
74    }
75}
76impl W {
77    #[doc = "Bits 0:7 - Trigger level. When the receiver FIFO has less entries than the amount of this field, a Ready To Send (RTS) output signal is activated. By setting this field to '0', flow control is effectively disabled (may be useful for debug purposes)."]
78    #[inline(always)]
79    #[must_use]
80    pub fn trigger_level(&mut self) -> TRIGGER_LEVEL_W<0> {
81        TRIGGER_LEVEL_W::new(self)
82    }
83    #[doc = "Bit 16 - Polarity of the RTS output signal: '0': RTS is active low; '1': RTS is active high; During SCB reset (Hibernate system power mode), RTS output signal is '1'. This represents an inactive state assuming an active low polarity."]
84    #[inline(always)]
85    #[must_use]
86    pub fn rts_polarity(&mut self) -> RTS_POLARITY_W<16> {
87        RTS_POLARITY_W::new(self)
88    }
89    #[doc = "Bit 24 - Polarity of the CTS input signal '0': CTS is active low ; '1': CTS is active high;"]
90    #[inline(always)]
91    #[must_use]
92    pub fn cts_polarity(&mut self) -> CTS_POLARITY_W<24> {
93        CTS_POLARITY_W::new(self)
94    }
95    #[doc = "Bit 25 - Enable use of CTS input signal by the UART transmitter: '0': Disabled. The UART transmitter ignores the CTS input signal and transmits when a data frame is available for transmission in the TX FIFO or the TX shift register. '1': Enabled. The UART transmitter uses CTS input signal to qualify the transmission of data. It transmits when CTS input signal is active and a data frame is available for transmission in the TX FIFO or the TX shift register. If UART_CTRL.LOOPBACK is '1', the CTS input signal is driven by the RTS output signal locally in SCB (both signals are subjected to signal polarity changes are indicated by RTS_POLARITY and CTS_POLARITY)."]
96    #[inline(always)]
97    #[must_use]
98    pub fn cts_enabled(&mut self) -> CTS_ENABLED_W<25> {
99        CTS_ENABLED_W::new(self)
100    }
101    #[doc = "Writes raw bits to the register."]
102    #[inline(always)]
103    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
104        self.0.bits(bits);
105        self
106    }
107}
108#[doc = "UART flow control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [uart_flow_ctrl](index.html) module"]
109pub struct UART_FLOW_CTRL_SPEC;
110impl crate::RegisterSpec for UART_FLOW_CTRL_SPEC {
111    type Ux = u32;
112}
113#[doc = "`read()` method returns [uart_flow_ctrl::R](R) reader structure"]
114impl crate::Readable for UART_FLOW_CTRL_SPEC {
115    type Reader = R;
116}
117#[doc = "`write(|w| ..)` method takes [uart_flow_ctrl::W](W) writer structure"]
118impl crate::Writable for UART_FLOW_CTRL_SPEC {
119    type Writer = W;
120    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
121    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
122}
123#[doc = "`reset()` method sets UART_FLOW_CTRL to value 0"]
124impl crate::Resettable for UART_FLOW_CTRL_SPEC {
125    const RESET_VALUE: Self::Ux = 0;
126}
cyt2cl_a/m0/scb0/uart_flow_ctrl.rs

cyt2cl_a/m0/scb0/
uart_flow_ctrl.rs
