cyt2cl_a/m0/flashc/
ecc_ctl.rs

1#[doc = "Register `ECC_CTL` reader"]
2pub struct R(crate::R<ECC_CTL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<ECC_CTL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<ECC_CTL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<ECC_CTL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `ECC_CTL` writer"]
17pub struct W(crate::W<ECC_CTL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<ECC_CTL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<ECC_CTL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<ECC_CTL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `WORD_ADDR` reader - Specifies the word address where an error will be injected. - For cache SRAM ECC, the word address WORD_ADDR\\[23:0\\]
38is device address A\\[25:2\\]. On a FLASH macro refill to this word address and when the corresponding CM0/4_CA_CTL.RAM_ECC_INJ_EN bit is '1', the parity (PARITY\\[6:0\\]) is injected and stored in the cache. - For FLASH main interface ECC, the word address WORD_ADDR\\[23:0\\]
39is device address A\\[26:3\\]. On a FLASH main interface read and when FLASH_CTL.MAIN_ECC_INJ_EN bit is '1', the parity (PARITY\\[7:0\\]) replaces the FLASH macro parity (FLASH main interface read path is manipulated). - For FLASH work interface ECC, the word address WORD_ADDR\\[23:0\\]
40is device address A\\[24:2\\]. On a FLASH work interface read and when FLASH_CTL.WORK_ECC_INJ_EN bit is '1', the parity (PARITY\\[6:0\\]) replaces the FLASH macro parity (FLASH work interface read path is manipulated)."]
41pub type WORD_ADDR_R = crate::FieldReader<u32, u32>;
42#[doc = "Field `WORD_ADDR` writer - Specifies the word address where an error will be injected. - For cache SRAM ECC, the word address WORD_ADDR\\[23:0\\]
43is device address A\\[25:2\\]. On a FLASH macro refill to this word address and when the corresponding CM0/4_CA_CTL.RAM_ECC_INJ_EN bit is '1', the parity (PARITY\\[6:0\\]) is injected and stored in the cache. - For FLASH main interface ECC, the word address WORD_ADDR\\[23:0\\]
44is device address A\\[26:3\\]. On a FLASH main interface read and when FLASH_CTL.MAIN_ECC_INJ_EN bit is '1', the parity (PARITY\\[7:0\\]) replaces the FLASH macro parity (FLASH main interface read path is manipulated). - For FLASH work interface ECC, the word address WORD_ADDR\\[23:0\\]
45is device address A\\[24:2\\]. On a FLASH work interface read and when FLASH_CTL.WORK_ECC_INJ_EN bit is '1', the parity (PARITY\\[6:0\\]) replaces the FLASH macro parity (FLASH work interface read path is manipulated)."]
46pub type WORD_ADDR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, ECC_CTL_SPEC, u32, u32, 24, O>;
47#[doc = "Field `PARITY` reader - ECC parity to use for ECC error injection at address WORD_ADDR. - For cache SRAM ECC, the 7-bit parity PARITY\\[6:0\\]
48is for a 32-bit word. - For FLASH main interface ECC, the 8-bit parity PARITY\\[7:0\\]
49is for a 64-bit word. - For FLASH work interface ECC, the 7-bit parity PARITY\\[6:0\\]
50is for a 32-bit word."]
51pub type PARITY_R = crate::FieldReader<u8, u8>;
52#[doc = "Field `PARITY` writer - ECC parity to use for ECC error injection at address WORD_ADDR. - For cache SRAM ECC, the 7-bit parity PARITY\\[6:0\\]
53is for a 32-bit word. - For FLASH main interface ECC, the 8-bit parity PARITY\\[7:0\\]
54is for a 64-bit word. - For FLASH work interface ECC, the 7-bit parity PARITY\\[6:0\\]
55is for a 32-bit word."]
56pub type PARITY_W<'a, const O: u8> = crate::FieldWriter<'a, u32, ECC_CTL_SPEC, u8, u8, 8, O>;
57impl R {
58    #[doc = "Bits 0:23 - Specifies the word address where an error will be injected. - For cache SRAM ECC, the word address WORD_ADDR\\[23:0\\]
59is device address A\\[25:2\\]. On a FLASH macro refill to this word address and when the corresponding CM0/4_CA_CTL.RAM_ECC_INJ_EN bit is '1', the parity (PARITY\\[6:0\\]) is injected and stored in the cache. - For FLASH main interface ECC, the word address WORD_ADDR\\[23:0\\]
60is device address A\\[26:3\\]. On a FLASH main interface read and when FLASH_CTL.MAIN_ECC_INJ_EN bit is '1', the parity (PARITY\\[7:0\\]) replaces the FLASH macro parity (FLASH main interface read path is manipulated). - For FLASH work interface ECC, the word address WORD_ADDR\\[23:0\\]
61is device address A\\[24:2\\]. On a FLASH work interface read and when FLASH_CTL.WORK_ECC_INJ_EN bit is '1', the parity (PARITY\\[6:0\\]) replaces the FLASH macro parity (FLASH work interface read path is manipulated)."]
62    #[inline(always)]
63    pub fn word_addr(&self) -> WORD_ADDR_R {
64        WORD_ADDR_R::new(self.bits & 0x00ff_ffff)
65    }
66    #[doc = "Bits 24:31 - ECC parity to use for ECC error injection at address WORD_ADDR. - For cache SRAM ECC, the 7-bit parity PARITY\\[6:0\\]
67is for a 32-bit word. - For FLASH main interface ECC, the 8-bit parity PARITY\\[7:0\\]
68is for a 64-bit word. - For FLASH work interface ECC, the 7-bit parity PARITY\\[6:0\\]
69is for a 32-bit word."]
70    #[inline(always)]
71    pub fn parity(&self) -> PARITY_R {
72        PARITY_R::new(((self.bits >> 24) & 0xff) as u8)
73    }
74}
75impl W {
76    #[doc = "Bits 0:23 - Specifies the word address where an error will be injected. - For cache SRAM ECC, the word address WORD_ADDR\\[23:0\\]
77is device address A\\[25:2\\]. On a FLASH macro refill to this word address and when the corresponding CM0/4_CA_CTL.RAM_ECC_INJ_EN bit is '1', the parity (PARITY\\[6:0\\]) is injected and stored in the cache. - For FLASH main interface ECC, the word address WORD_ADDR\\[23:0\\]
78is device address A\\[26:3\\]. On a FLASH main interface read and when FLASH_CTL.MAIN_ECC_INJ_EN bit is '1', the parity (PARITY\\[7:0\\]) replaces the FLASH macro parity (FLASH main interface read path is manipulated). - For FLASH work interface ECC, the word address WORD_ADDR\\[23:0\\]
79is device address A\\[24:2\\]. On a FLASH work interface read and when FLASH_CTL.WORK_ECC_INJ_EN bit is '1', the parity (PARITY\\[6:0\\]) replaces the FLASH macro parity (FLASH work interface read path is manipulated)."]
80    #[inline(always)]
81    #[must_use]
82    pub fn word_addr(&mut self) -> WORD_ADDR_W<0> {
83        WORD_ADDR_W::new(self)
84    }
85    #[doc = "Bits 24:31 - ECC parity to use for ECC error injection at address WORD_ADDR. - For cache SRAM ECC, the 7-bit parity PARITY\\[6:0\\]
86is for a 32-bit word. - For FLASH main interface ECC, the 8-bit parity PARITY\\[7:0\\]
87is for a 64-bit word. - For FLASH work interface ECC, the 7-bit parity PARITY\\[6:0\\]
88is for a 32-bit word."]
89    #[inline(always)]
90    #[must_use]
91    pub fn parity(&mut self) -> PARITY_W<24> {
92        PARITY_W::new(self)
93    }
94    #[doc = "Writes raw bits to the register."]
95    #[inline(always)]
96    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
97        self.0.bits(bits);
98        self
99    }
100}
101#[doc = "ECC control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ecc_ctl](index.html) module"]
102pub struct ECC_CTL_SPEC;
103impl crate::RegisterSpec for ECC_CTL_SPEC {
104    type Ux = u32;
105}
106#[doc = "`read()` method returns [ecc_ctl::R](R) reader structure"]
107impl crate::Readable for ECC_CTL_SPEC {
108    type Reader = R;
109}
110#[doc = "`write(|w| ..)` method takes [ecc_ctl::W](W) writer structure"]
111impl crate::Writable for ECC_CTL_SPEC {
112    type Writer = W;
113    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
114    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
115}
116#[doc = "`reset()` method sets ECC_CTL to value 0"]
117impl crate::Resettable for ECC_CTL_SPEC {
118    const RESET_VALUE: Self::Ux = 0;
119}
cyt2cl_a/m0/flashc/ecc_ctl.rs

cyt2cl_a/m0/flashc/
ecc_ctl.rs
