Crate cyt2cl
Source - backup
- SRSS Backup Domain (ver3p3)
- canfd0
- CAN Controller
- cpuss
- CPU subsystem (CPUSS)
- crypto
- Cryptography component
- cxpi0
- CXPI
- dmac
- DMAC
- dw0
- Datawire Controller
- efuse
- EFUSE MXS40 registers
- efuse_data
- eFUSE memory
- evtgen0
- Event generator
- fault
- Fault structures
- flashc
- Flash controller
- generic
- Common register and bit access and modify traits
- gpio
- GPIO port control/configuration
- hsiom
- High Speed IO Matrix (HSIOM)
- ipc
- IPC
- lcd0
- LCD Controller Block
- lin0
- LIN
- mixer0
- MIXER
- pass0
- Programmable Analog Subsystem for S40E
- peri
- Peripheral interconnect
- peri_ms
- Peripheral interconnect, master interface
- prot
- Protection
- pwm0
- PWM
- scb0
- Serial Communications Block (SPI/UART/I2C)
- sg0
- SG
- smartio
- Programmable IO configuration
- smif0
- Serial Memory Interface
- srss
- SRSS Core Registers (ver3p3)
- tcpwm0
- Timer/Counter/PWM
- tdm0
- TDM
- BACKUP
- SRSS Backup Domain (ver3p3)
- CANFD0
- CAN Controller
- CANFD1
- CAN Controller
- CBP
- Cache and branch predictor maintenance operations
- CPUID
- CPUID
- CPUSS
- CPU subsystem (CPUSS)
- CRYPTO
- Cryptography component
- CXPI0
- CXPI
- CorePeripherals
- Core peripherals
- DCB
- Debug Control Block
- DMAC
- DMAC
- DW0
- Datawire Controller
- DW1
- Datawire Controller
- DWT
- Data Watchpoint and Trace unit
- EFUSE
- EFUSE MXS40 registers
- EFUSE_DATA
- eFUSE memory
- EVTGEN0
- Event generator
- FAULT
- Fault structures
- FLASHC
- Flash controller
- FPB
- Flash Patch and Breakpoint unit
- GPIO
- GPIO port control/configuration
- HSIOM
- High Speed IO Matrix (HSIOM)
- IPC
- IPC
- ITM
- Instrumentation Trace Macrocell
- LCD0
- LCD Controller Block
- LIN0
- LIN
- MIXER0
- MIXER
- MPU
- Memory Protection Unit
- NVIC
- Nested Vector Interrupt Controller
- PASS0
- Programmable Analog Subsystem for S40E
- PERI
- Peripheral interconnect
- PERI_MS
- Peripheral interconnect, master interface
- PROT
- Protection
- PWM0
- PWM
- Peripherals
- All the peripherals.
- SCB
- System Control Block
- SCB0
- Serial Communications Block (SPI/UART/I2C)
- SCB1
- Serial Communications Block (SPI/UART/I2C)
- SCB2
- Serial Communications Block (SPI/UART/I2C)
- SCB3
- Serial Communications Block (SPI/UART/I2C)
- SCB4
- Serial Communications Block (SPI/UART/I2C)
- SCB5
- Serial Communications Block (SPI/UART/I2C)
- SCB6
- Serial Communications Block (SPI/UART/I2C)
- SCB7
- Serial Communications Block (SPI/UART/I2C)
- SCB8
- Serial Communications Block (SPI/UART/I2C)
- SCB9
- Serial Communications Block (SPI/UART/I2C)
- SCB10
- Serial Communications Block (SPI/UART/I2C)
- SCB11
- Serial Communications Block (SPI/UART/I2C)
- SG0
- SG
- SMARTIO
- Programmable IO configuration
- SMIF0
- Serial Memory Interface
- SRSS
- SRSS Core Registers (ver3p3)
- SYST
- SysTick: System Timer
- TCPWM0
- Timer/Counter/PWM
- TDM0
- TDM
- TPIU
- Trace Port Interface Unit
- Interrupt
- Enumeration of all the interrupts.
- interrupt
- Enumeration of all the interrupts.
- NVIC_PRIO_BITS
- Number available in the NVIC for configuring priority
- interrupt