cyt2bl_a/m4/flashc/
cm4_ca_ctl0.rs

1#[doc = "Register `CM4_CA_CTL0` reader"]
2pub struct R(crate::R<CM4_CA_CTL0_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CM4_CA_CTL0_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CM4_CA_CTL0_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CM4_CA_CTL0_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `CM4_CA_CTL0` writer"]
17pub struct W(crate::W<CM4_CA_CTL0_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CM4_CA_CTL0_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CM4_CA_CTL0_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CM4_CA_CTL0_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `RAM_ECC_EN` reader - See CM0_CA_CTL."]
38pub type RAM_ECC_EN_R = crate::BitReader<bool>;
39#[doc = "Field `RAM_ECC_EN` writer - See CM0_CA_CTL."]
40pub type RAM_ECC_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CM4_CA_CTL0_SPEC, bool, O>;
41#[doc = "Field `RAM_ECC_INJ_EN` reader - See CM0_CA_CTL."]
42pub type RAM_ECC_INJ_EN_R = crate::BitReader<bool>;
43#[doc = "Field `RAM_ECC_INJ_EN` writer - See CM0_CA_CTL."]
44pub type RAM_ECC_INJ_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CM4_CA_CTL0_SPEC, bool, O>;
45#[doc = "Field `WAY` reader - See CM0_CA_CTL."]
46pub type WAY_R = crate::FieldReader<u8, u8>;
47#[doc = "Field `WAY` writer - See CM0_CA_CTL."]
48pub type WAY_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CM4_CA_CTL0_SPEC, u8, u8, 2, O>;
49#[doc = "Field `SET_ADDR` reader - See CM0_CA_CTL."]
50pub type SET_ADDR_R = crate::FieldReader<u8, u8>;
51#[doc = "Field `SET_ADDR` writer - See CM0_CA_CTL."]
52pub type SET_ADDR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CM4_CA_CTL0_SPEC, u8, u8, 3, O>;
53#[doc = "Field `PREF_EN` reader - See CM0_CA_CTL."]
54pub type PREF_EN_R = crate::BitReader<bool>;
55#[doc = "Field `PREF_EN` writer - See CM0_CA_CTL."]
56pub type PREF_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CM4_CA_CTL0_SPEC, bool, O>;
57#[doc = "Field `CA_EN` reader - See CM0_CA_CTL."]
58pub type CA_EN_R = crate::BitReader<bool>;
59#[doc = "Field `CA_EN` writer - See CM0_CA_CTL."]
60pub type CA_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CM4_CA_CTL0_SPEC, bool, O>;
61impl R {
62    #[doc = "Bit 0 - See CM0_CA_CTL."]
63    #[inline(always)]
64    pub fn ram_ecc_en(&self) -> RAM_ECC_EN_R {
65        RAM_ECC_EN_R::new((self.bits & 1) != 0)
66    }
67    #[doc = "Bit 1 - See CM0_CA_CTL."]
68    #[inline(always)]
69    pub fn ram_ecc_inj_en(&self) -> RAM_ECC_INJ_EN_R {
70        RAM_ECC_INJ_EN_R::new(((self.bits >> 1) & 1) != 0)
71    }
72    #[doc = "Bits 16:17 - See CM0_CA_CTL."]
73    #[inline(always)]
74    pub fn way(&self) -> WAY_R {
75        WAY_R::new(((self.bits >> 16) & 3) as u8)
76    }
77    #[doc = "Bits 24:26 - See CM0_CA_CTL."]
78    #[inline(always)]
79    pub fn set_addr(&self) -> SET_ADDR_R {
80        SET_ADDR_R::new(((self.bits >> 24) & 7) as u8)
81    }
82    #[doc = "Bit 30 - See CM0_CA_CTL."]
83    #[inline(always)]
84    pub fn pref_en(&self) -> PREF_EN_R {
85        PREF_EN_R::new(((self.bits >> 30) & 1) != 0)
86    }
87    #[doc = "Bit 31 - See CM0_CA_CTL."]
88    #[inline(always)]
89    pub fn ca_en(&self) -> CA_EN_R {
90        CA_EN_R::new(((self.bits >> 31) & 1) != 0)
91    }
92}
93impl W {
94    #[doc = "Bit 0 - See CM0_CA_CTL."]
95    #[inline(always)]
96    #[must_use]
97    pub fn ram_ecc_en(&mut self) -> RAM_ECC_EN_W<0> {
98        RAM_ECC_EN_W::new(self)
99    }
100    #[doc = "Bit 1 - See CM0_CA_CTL."]
101    #[inline(always)]
102    #[must_use]
103    pub fn ram_ecc_inj_en(&mut self) -> RAM_ECC_INJ_EN_W<1> {
104        RAM_ECC_INJ_EN_W::new(self)
105    }
106    #[doc = "Bits 16:17 - See CM0_CA_CTL."]
107    #[inline(always)]
108    #[must_use]
109    pub fn way(&mut self) -> WAY_W<16> {
110        WAY_W::new(self)
111    }
112    #[doc = "Bits 24:26 - See CM0_CA_CTL."]
113    #[inline(always)]
114    #[must_use]
115    pub fn set_addr(&mut self) -> SET_ADDR_W<24> {
116        SET_ADDR_W::new(self)
117    }
118    #[doc = "Bit 30 - See CM0_CA_CTL."]
119    #[inline(always)]
120    #[must_use]
121    pub fn pref_en(&mut self) -> PREF_EN_W<30> {
122        PREF_EN_W::new(self)
123    }
124    #[doc = "Bit 31 - See CM0_CA_CTL."]
125    #[inline(always)]
126    #[must_use]
127    pub fn ca_en(&mut self) -> CA_EN_W<31> {
128        CA_EN_W::new(self)
129    }
130    #[doc = "Writes raw bits to the register."]
131    #[inline(always)]
132    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
133        self.0.bits(bits);
134        self
135    }
136}
137#[doc = "CM4 cache control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cm4_ca_ctl0](index.html) module"]
138pub struct CM4_CA_CTL0_SPEC;
139impl crate::RegisterSpec for CM4_CA_CTL0_SPEC {
140    type Ux = u32;
141}
142#[doc = "`read()` method returns [cm4_ca_ctl0::R](R) reader structure"]
143impl crate::Readable for CM4_CA_CTL0_SPEC {
144    type Reader = R;
145}
146#[doc = "`write(|w| ..)` method takes [cm4_ca_ctl0::W](W) writer structure"]
147impl crate::Writable for CM4_CA_CTL0_SPEC {
148    type Writer = W;
149    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
150    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
151}
152#[doc = "`reset()` method sets CM4_CA_CTL0 to value 0xc000_0001"]
153impl crate::Resettable for CM4_CA_CTL0_SPEC {
154    const RESET_VALUE: Self::Ux = 0xc000_0001;
155}
cyt2bl_a/m4/flashc/cm4_ca_ctl0.rs

cyt2bl_a/m4/flashc/
cm4_ca_ctl0.rs
