1#[doc = "Register `INTR_S` reader"]
2pub struct R(crate::R<INTR_S_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<INTR_S_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<INTR_S_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<INTR_S_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `INTR_S` writer"]
17pub struct W(crate::W<INTR_S_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<INTR_S_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<INTR_S_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<INTR_S_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Field `I2C_ARB_LOST` reader - I2C slave lost arbitration: the value driven on the SDA line is not the same as the value observed on the SDA line (while the SCL line is '1'). This should not occur, it represents erroneous I2C bus behavior. In case of lost arbitration, the I2C slave state machine aborts the ongoing transfer. The Firmware may decide to clear the TX and RX FIFOs in case of this error."]
38pub type I2C_ARB_LOST_R = crate::BitReader<bool>;
39#[doc = "Field `I2C_ARB_LOST` writer - I2C slave lost arbitration: the value driven on the SDA line is not the same as the value observed on the SDA line (while the SCL line is '1'). This should not occur, it represents erroneous I2C bus behavior. In case of lost arbitration, the I2C slave state machine aborts the ongoing transfer. The Firmware may decide to clear the TX and RX FIFOs in case of this error."]
40pub type I2C_ARB_LOST_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTR_S_SPEC, bool, O>;
41#[doc = "Field `I2C_NACK` reader - I2C slave negative acknowledgement received. Set to '1', when the slave receives a NACK (typically after the slave transmitted TX data)."]
42pub type I2C_NACK_R = crate::BitReader<bool>;
43#[doc = "Field `I2C_NACK` writer - I2C slave negative acknowledgement received. Set to '1', when the slave receives a NACK (typically after the slave transmitted TX data)."]
44pub type I2C_NACK_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTR_S_SPEC, bool, O>;
45#[doc = "Field `I2C_ACK` reader - I2C slave acknowledgement received. Set to '1', when the slave receives a ACK (typically after the slave transmitted TX data)."]
46pub type I2C_ACK_R = crate::BitReader<bool>;
47#[doc = "Field `I2C_ACK` writer - I2C slave acknowledgement received. Set to '1', when the slave receives a ACK (typically after the slave transmitted TX data)."]
48pub type I2C_ACK_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTR_S_SPEC, bool, O>;
49#[doc = "Field `I2C_WRITE_STOP` reader - I2C STOP event for I2C write transfer intended for this slave (address matching is performed). Set to '1', when STOP or REPEATED START event is detected. The REPEATED START event is included in this interrupt cause such that the I2C transfers separated by a REPEATED START can be distinguished and potentially treated separately by the Firmware. Note that the second I2C transfer (after a REPEATED START) may be to a different slave address. In non EZ mode, the event is detected on any I2C write transfer intended for this slave. Note that a I2C write address intended for the slave (address is matching and a it is a write transfer) will result in a I2C_WRITE_STOP event independent of whether the I2C address is ACK'd or NACK'd. In EZ mode, the event is detected only on I2C write transfers that have EZ data written to the memory structure (an I2C write transfer that only communicates an I2C address and EZ address, will not result in this event being detected)."]
50pub type I2C_WRITE_STOP_R = crate::BitReader<bool>;
51#[doc = "Field `I2C_WRITE_STOP` writer - I2C STOP event for I2C write transfer intended for this slave (address matching is performed). Set to '1', when STOP or REPEATED START event is detected. The REPEATED START event is included in this interrupt cause such that the I2C transfers separated by a REPEATED START can be distinguished and potentially treated separately by the Firmware. Note that the second I2C transfer (after a REPEATED START) may be to a different slave address. In non EZ mode, the event is detected on any I2C write transfer intended for this slave. Note that a I2C write address intended for the slave (address is matching and a it is a write transfer) will result in a I2C_WRITE_STOP event independent of whether the I2C address is ACK'd or NACK'd. In EZ mode, the event is detected only on I2C write transfers that have EZ data written to the memory structure (an I2C write transfer that only communicates an I2C address and EZ address, will not result in this event being detected)."]
52pub type I2C_WRITE_STOP_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTR_S_SPEC, bool, O>;
53#[doc = "Field `I2C_STOP` reader - I2C STOP event for I2C (read or write) transfer intended for this slave (address matching is performed). Set to '1', when STOP or REPEATED START event is detected. The REPEATED START event is included in this interrupt cause such that the I2C transfers separated by a REPEATED START can be distinguished and potentially treated separately by the Firmware. Note that the second I2C transfer (after a REPEATED START) may be to a different slave address. The event is detected on any I2C transfer intended for this slave. Note that a I2C address intended for the slave (address is matching) will result in a I2C_STOP event independent of whether the I2C address is ACK'd or NACK'd."]
54pub type I2C_STOP_R = crate::BitReader<bool>;
55#[doc = "Field `I2C_STOP` writer - I2C STOP event for I2C (read or write) transfer intended for this slave (address matching is performed). Set to '1', when STOP or REPEATED START event is detected. The REPEATED START event is included in this interrupt cause such that the I2C transfers separated by a REPEATED START can be distinguished and potentially treated separately by the Firmware. Note that the second I2C transfer (after a REPEATED START) may be to a different slave address. The event is detected on any I2C transfer intended for this slave. Note that a I2C address intended for the slave (address is matching) will result in a I2C_STOP event independent of whether the I2C address is ACK'd or NACK'd."]
56pub type I2C_STOP_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTR_S_SPEC, bool, O>;
57#[doc = "Field `I2C_START` reader - I2C slave START received. Set to '1', when START or REPEATED START event is detected. In the case of externally clocked address matching (CTRL.EC_AM_MODE is '1') AND clock stretching is performed (I2C_CTRL.S_NOT_READY_ADDR_NACK is '0'), this field is NOT set. The Firmware should use INTR_S_EC.WAKE_UP, INTR_S.I2C_ADDR_MATCH and INTR_S.I2C_GENERAL."]
58pub type I2C_START_R = crate::BitReader<bool>;
59#[doc = "Field `I2C_START` writer - I2C slave START received. Set to '1', when START or REPEATED START event is detected. In the case of externally clocked address matching (CTRL.EC_AM_MODE is '1') AND clock stretching is performed (I2C_CTRL.S_NOT_READY_ADDR_NACK is '0'), this field is NOT set. The Firmware should use INTR_S_EC.WAKE_UP, INTR_S.I2C_ADDR_MATCH and INTR_S.I2C_GENERAL."]
60pub type I2C_START_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTR_S_SPEC, bool, O>;
61#[doc = "Field `I2C_ADDR_MATCH` reader - I2C slave matching address received. If CTRL.ADDR_ACCEPT, the received address (including the R/W bit) is available in the RX FIFO. In the case of externally clocked address matching (CTRL.EC_AM_MODE is '1') and internally clocked operation (CTRL.EC_OP_MODE is '0'), this field is set when the event is detected."]
62pub type I2C_ADDR_MATCH_R = crate::BitReader<bool>;
63#[doc = "Field `I2C_ADDR_MATCH` writer - I2C slave matching address received. If CTRL.ADDR_ACCEPT, the received address (including the R/W bit) is available in the RX FIFO. In the case of externally clocked address matching (CTRL.EC_AM_MODE is '1') and internally clocked operation (CTRL.EC_OP_MODE is '0'), this field is set when the event is detected."]
64pub type I2C_ADDR_MATCH_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTR_S_SPEC, bool, O>;
65#[doc = "Field `I2C_GENERAL` reader - I2C slave general call address received. If CTRL.ADDR_ACCEPT, the received address 0x00 (including the R/W bit) is available in the RX FIFO. In the case of externally clocked address matching (CTRL.EC_AM_MODE is '1') and internally clocked operation (CTRL.EC_OP_MODE is '0'), this field is set when the event is detected."]
66pub type I2C_GENERAL_R = crate::BitReader<bool>;
67#[doc = "Field `I2C_GENERAL` writer - I2C slave general call address received. If CTRL.ADDR_ACCEPT, the received address 0x00 (including the R/W bit) is available in the RX FIFO. In the case of externally clocked address matching (CTRL.EC_AM_MODE is '1') and internally clocked operation (CTRL.EC_OP_MODE is '0'), this field is set when the event is detected."]
68pub type I2C_GENERAL_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTR_S_SPEC, bool, O>;
69#[doc = "Field `I2C_BUS_ERROR` reader - I2C slave bus error (unexpected detection of START or STOP condition). This should not occur, it represents erroneous I2C bus behavior. In case of a bus error, the I2C slave state machine abort the ongoing transfer. The Firmware may decide to clear the TX and RX FIFOs in case of this error."]
70pub type I2C_BUS_ERROR_R = crate::BitReader<bool>;
71#[doc = "Field `I2C_BUS_ERROR` writer - I2C slave bus error (unexpected detection of START or STOP condition). This should not occur, it represents erroneous I2C bus behavior. In case of a bus error, the I2C slave state machine abort the ongoing transfer. The Firmware may decide to clear the TX and RX FIFOs in case of this error."]
72pub type I2C_BUS_ERROR_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTR_S_SPEC, bool, O>;
73#[doc = "Field `SPI_EZ_WRITE_STOP` reader - SPI slave deselected after a write EZ SPI transfer occurred."]
74pub type SPI_EZ_WRITE_STOP_R = crate::BitReader<bool>;
75#[doc = "Field `SPI_EZ_WRITE_STOP` writer - SPI slave deselected after a write EZ SPI transfer occurred."]
76pub type SPI_EZ_WRITE_STOP_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTR_S_SPEC, bool, O>;
77#[doc = "Field `SPI_EZ_STOP` reader - SPI slave deselected after any EZ SPI transfer occurred."]
78pub type SPI_EZ_STOP_R = crate::BitReader<bool>;
79#[doc = "Field `SPI_EZ_STOP` writer - SPI slave deselected after any EZ SPI transfer occurred."]
80pub type SPI_EZ_STOP_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTR_S_SPEC, bool, O>;
81#[doc = "Field `SPI_BUS_ERROR` reader - SPI slave deselected at an unexpected time in the SPI transfer. The Firmware may decide to clear the TX and RX FIFOs in case of this error."]
82pub type SPI_BUS_ERROR_R = crate::BitReader<bool>;
83#[doc = "Field `SPI_BUS_ERROR` writer - SPI slave deselected at an unexpected time in the SPI transfer. The Firmware may decide to clear the TX and RX FIFOs in case of this error."]
84pub type SPI_BUS_ERROR_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTR_S_SPEC, bool, O>;
85impl R {
86 #[doc = "Bit 0 - I2C slave lost arbitration: the value driven on the SDA line is not the same as the value observed on the SDA line (while the SCL line is '1'). This should not occur, it represents erroneous I2C bus behavior. In case of lost arbitration, the I2C slave state machine aborts the ongoing transfer. The Firmware may decide to clear the TX and RX FIFOs in case of this error."]
87 #[inline(always)]
88 pub fn i2c_arb_lost(&self) -> I2C_ARB_LOST_R {
89 I2C_ARB_LOST_R::new((self.bits & 1) != 0)
90 }
91 #[doc = "Bit 1 - I2C slave negative acknowledgement received. Set to '1', when the slave receives a NACK (typically after the slave transmitted TX data)."]
92 #[inline(always)]
93 pub fn i2c_nack(&self) -> I2C_NACK_R {
94 I2C_NACK_R::new(((self.bits >> 1) & 1) != 0)
95 }
96 #[doc = "Bit 2 - I2C slave acknowledgement received. Set to '1', when the slave receives a ACK (typically after the slave transmitted TX data)."]
97 #[inline(always)]
98 pub fn i2c_ack(&self) -> I2C_ACK_R {
99 I2C_ACK_R::new(((self.bits >> 2) & 1) != 0)
100 }
101 #[doc = "Bit 3 - I2C STOP event for I2C write transfer intended for this slave (address matching is performed). Set to '1', when STOP or REPEATED START event is detected. The REPEATED START event is included in this interrupt cause such that the I2C transfers separated by a REPEATED START can be distinguished and potentially treated separately by the Firmware. Note that the second I2C transfer (after a REPEATED START) may be to a different slave address. In non EZ mode, the event is detected on any I2C write transfer intended for this slave. Note that a I2C write address intended for the slave (address is matching and a it is a write transfer) will result in a I2C_WRITE_STOP event independent of whether the I2C address is ACK'd or NACK'd. In EZ mode, the event is detected only on I2C write transfers that have EZ data written to the memory structure (an I2C write transfer that only communicates an I2C address and EZ address, will not result in this event being detected)."]
102 #[inline(always)]
103 pub fn i2c_write_stop(&self) -> I2C_WRITE_STOP_R {
104 I2C_WRITE_STOP_R::new(((self.bits >> 3) & 1) != 0)
105 }
106 #[doc = "Bit 4 - I2C STOP event for I2C (read or write) transfer intended for this slave (address matching is performed). Set to '1', when STOP or REPEATED START event is detected. The REPEATED START event is included in this interrupt cause such that the I2C transfers separated by a REPEATED START can be distinguished and potentially treated separately by the Firmware. Note that the second I2C transfer (after a REPEATED START) may be to a different slave address. The event is detected on any I2C transfer intended for this slave. Note that a I2C address intended for the slave (address is matching) will result in a I2C_STOP event independent of whether the I2C address is ACK'd or NACK'd."]
107 #[inline(always)]
108 pub fn i2c_stop(&self) -> I2C_STOP_R {
109 I2C_STOP_R::new(((self.bits >> 4) & 1) != 0)
110 }
111 #[doc = "Bit 5 - I2C slave START received. Set to '1', when START or REPEATED START event is detected. In the case of externally clocked address matching (CTRL.EC_AM_MODE is '1') AND clock stretching is performed (I2C_CTRL.S_NOT_READY_ADDR_NACK is '0'), this field is NOT set. The Firmware should use INTR_S_EC.WAKE_UP, INTR_S.I2C_ADDR_MATCH and INTR_S.I2C_GENERAL."]
112 #[inline(always)]
113 pub fn i2c_start(&self) -> I2C_START_R {
114 I2C_START_R::new(((self.bits >> 5) & 1) != 0)
115 }
116 #[doc = "Bit 6 - I2C slave matching address received. If CTRL.ADDR_ACCEPT, the received address (including the R/W bit) is available in the RX FIFO. In the case of externally clocked address matching (CTRL.EC_AM_MODE is '1') and internally clocked operation (CTRL.EC_OP_MODE is '0'), this field is set when the event is detected."]
117 #[inline(always)]
118 pub fn i2c_addr_match(&self) -> I2C_ADDR_MATCH_R {
119 I2C_ADDR_MATCH_R::new(((self.bits >> 6) & 1) != 0)
120 }
121 #[doc = "Bit 7 - I2C slave general call address received. If CTRL.ADDR_ACCEPT, the received address 0x00 (including the R/W bit) is available in the RX FIFO. In the case of externally clocked address matching (CTRL.EC_AM_MODE is '1') and internally clocked operation (CTRL.EC_OP_MODE is '0'), this field is set when the event is detected."]
122 #[inline(always)]
123 pub fn i2c_general(&self) -> I2C_GENERAL_R {
124 I2C_GENERAL_R::new(((self.bits >> 7) & 1) != 0)
125 }
126 #[doc = "Bit 8 - I2C slave bus error (unexpected detection of START or STOP condition). This should not occur, it represents erroneous I2C bus behavior. In case of a bus error, the I2C slave state machine abort the ongoing transfer. The Firmware may decide to clear the TX and RX FIFOs in case of this error."]
127 #[inline(always)]
128 pub fn i2c_bus_error(&self) -> I2C_BUS_ERROR_R {
129 I2C_BUS_ERROR_R::new(((self.bits >> 8) & 1) != 0)
130 }
131 #[doc = "Bit 9 - SPI slave deselected after a write EZ SPI transfer occurred."]
132 #[inline(always)]
133 pub fn spi_ez_write_stop(&self) -> SPI_EZ_WRITE_STOP_R {
134 SPI_EZ_WRITE_STOP_R::new(((self.bits >> 9) & 1) != 0)
135 }
136 #[doc = "Bit 10 - SPI slave deselected after any EZ SPI transfer occurred."]
137 #[inline(always)]
138 pub fn spi_ez_stop(&self) -> SPI_EZ_STOP_R {
139 SPI_EZ_STOP_R::new(((self.bits >> 10) & 1) != 0)
140 }
141 #[doc = "Bit 11 - SPI slave deselected at an unexpected time in the SPI transfer. The Firmware may decide to clear the TX and RX FIFOs in case of this error."]
142 #[inline(always)]
143 pub fn spi_bus_error(&self) -> SPI_BUS_ERROR_R {
144 SPI_BUS_ERROR_R::new(((self.bits >> 11) & 1) != 0)
145 }
146}
147impl W {
148 #[doc = "Bit 0 - I2C slave lost arbitration: the value driven on the SDA line is not the same as the value observed on the SDA line (while the SCL line is '1'). This should not occur, it represents erroneous I2C bus behavior. In case of lost arbitration, the I2C slave state machine aborts the ongoing transfer. The Firmware may decide to clear the TX and RX FIFOs in case of this error."]
149 #[inline(always)]
150 #[must_use]
151 pub fn i2c_arb_lost(&mut self) -> I2C_ARB_LOST_W<0> {
152 I2C_ARB_LOST_W::new(self)
153 }
154 #[doc = "Bit 1 - I2C slave negative acknowledgement received. Set to '1', when the slave receives a NACK (typically after the slave transmitted TX data)."]
155 #[inline(always)]
156 #[must_use]
157 pub fn i2c_nack(&mut self) -> I2C_NACK_W<1> {
158 I2C_NACK_W::new(self)
159 }
160 #[doc = "Bit 2 - I2C slave acknowledgement received. Set to '1', when the slave receives a ACK (typically after the slave transmitted TX data)."]
161 #[inline(always)]
162 #[must_use]
163 pub fn i2c_ack(&mut self) -> I2C_ACK_W<2> {
164 I2C_ACK_W::new(self)
165 }
166 #[doc = "Bit 3 - I2C STOP event for I2C write transfer intended for this slave (address matching is performed). Set to '1', when STOP or REPEATED START event is detected. The REPEATED START event is included in this interrupt cause such that the I2C transfers separated by a REPEATED START can be distinguished and potentially treated separately by the Firmware. Note that the second I2C transfer (after a REPEATED START) may be to a different slave address. In non EZ mode, the event is detected on any I2C write transfer intended for this slave. Note that a I2C write address intended for the slave (address is matching and a it is a write transfer) will result in a I2C_WRITE_STOP event independent of whether the I2C address is ACK'd or NACK'd. In EZ mode, the event is detected only on I2C write transfers that have EZ data written to the memory structure (an I2C write transfer that only communicates an I2C address and EZ address, will not result in this event being detected)."]
167 #[inline(always)]
168 #[must_use]
169 pub fn i2c_write_stop(&mut self) -> I2C_WRITE_STOP_W<3> {
170 I2C_WRITE_STOP_W::new(self)
171 }
172 #[doc = "Bit 4 - I2C STOP event for I2C (read or write) transfer intended for this slave (address matching is performed). Set to '1', when STOP or REPEATED START event is detected. The REPEATED START event is included in this interrupt cause such that the I2C transfers separated by a REPEATED START can be distinguished and potentially treated separately by the Firmware. Note that the second I2C transfer (after a REPEATED START) may be to a different slave address. The event is detected on any I2C transfer intended for this slave. Note that a I2C address intended for the slave (address is matching) will result in a I2C_STOP event independent of whether the I2C address is ACK'd or NACK'd."]
173 #[inline(always)]
174 #[must_use]
175 pub fn i2c_stop(&mut self) -> I2C_STOP_W<4> {
176 I2C_STOP_W::new(self)
177 }
178 #[doc = "Bit 5 - I2C slave START received. Set to '1', when START or REPEATED START event is detected. In the case of externally clocked address matching (CTRL.EC_AM_MODE is '1') AND clock stretching is performed (I2C_CTRL.S_NOT_READY_ADDR_NACK is '0'), this field is NOT set. The Firmware should use INTR_S_EC.WAKE_UP, INTR_S.I2C_ADDR_MATCH and INTR_S.I2C_GENERAL."]
179 #[inline(always)]
180 #[must_use]
181 pub fn i2c_start(&mut self) -> I2C_START_W<5> {
182 I2C_START_W::new(self)
183 }
184 #[doc = "Bit 6 - I2C slave matching address received. If CTRL.ADDR_ACCEPT, the received address (including the R/W bit) is available in the RX FIFO. In the case of externally clocked address matching (CTRL.EC_AM_MODE is '1') and internally clocked operation (CTRL.EC_OP_MODE is '0'), this field is set when the event is detected."]
185 #[inline(always)]
186 #[must_use]
187 pub fn i2c_addr_match(&mut self) -> I2C_ADDR_MATCH_W<6> {
188 I2C_ADDR_MATCH_W::new(self)
189 }
190 #[doc = "Bit 7 - I2C slave general call address received. If CTRL.ADDR_ACCEPT, the received address 0x00 (including the R/W bit) is available in the RX FIFO. In the case of externally clocked address matching (CTRL.EC_AM_MODE is '1') and internally clocked operation (CTRL.EC_OP_MODE is '0'), this field is set when the event is detected."]
191 #[inline(always)]
192 #[must_use]
193 pub fn i2c_general(&mut self) -> I2C_GENERAL_W<7> {
194 I2C_GENERAL_W::new(self)
195 }
196 #[doc = "Bit 8 - I2C slave bus error (unexpected detection of START or STOP condition). This should not occur, it represents erroneous I2C bus behavior. In case of a bus error, the I2C slave state machine abort the ongoing transfer. The Firmware may decide to clear the TX and RX FIFOs in case of this error."]
197 #[inline(always)]
198 #[must_use]
199 pub fn i2c_bus_error(&mut self) -> I2C_BUS_ERROR_W<8> {
200 I2C_BUS_ERROR_W::new(self)
201 }
202 #[doc = "Bit 9 - SPI slave deselected after a write EZ SPI transfer occurred."]
203 #[inline(always)]
204 #[must_use]
205 pub fn spi_ez_write_stop(&mut self) -> SPI_EZ_WRITE_STOP_W<9> {
206 SPI_EZ_WRITE_STOP_W::new(self)
207 }
208 #[doc = "Bit 10 - SPI slave deselected after any EZ SPI transfer occurred."]
209 #[inline(always)]
210 #[must_use]
211 pub fn spi_ez_stop(&mut self) -> SPI_EZ_STOP_W<10> {
212 SPI_EZ_STOP_W::new(self)
213 }
214 #[doc = "Bit 11 - SPI slave deselected at an unexpected time in the SPI transfer. The Firmware may decide to clear the TX and RX FIFOs in case of this error."]
215 #[inline(always)]
216 #[must_use]
217 pub fn spi_bus_error(&mut self) -> SPI_BUS_ERROR_W<11> {
218 SPI_BUS_ERROR_W::new(self)
219 }
220 #[doc = "Writes raw bits to the register."]
221 #[inline(always)]
222 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
223 self.0.bits(bits);
224 self
225 }
226}
227#[doc = "Slave interrupt request\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intr_s](index.html) module"]
228pub struct INTR_S_SPEC;
229impl crate::RegisterSpec for INTR_S_SPEC {
230 type Ux = u32;
231}
232#[doc = "`read()` method returns [intr_s::R](R) reader structure"]
233impl crate::Readable for INTR_S_SPEC {
234 type Reader = R;
235}
236#[doc = "`write(|w| ..)` method takes [intr_s::W](W) writer structure"]
237impl crate::Writable for INTR_S_SPEC {
238 type Writer = W;
239 const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
240 const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
241}
242#[doc = "`reset()` method sets INTR_S to value 0"]
243impl crate::Resettable for INTR_S_SPEC {
244 const RESET_VALUE: Self::Ux = 0;
245}