cyt2b9_c/m0/canfd0/
ctl.rs

1#[doc = "Register `CTL` reader"]
2pub struct R(crate::R<CTL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CTL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CTL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CTL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `CTL` writer"]
17pub struct W(crate::W<CTL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CTL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CTL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CTL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `STOP_REQ` reader - Clock Stop Request for each TTCAN IP . The m_ttcan_clkstop_req of each TTCAN IP is directly driven by these bits."]
38pub type STOP_REQ_R = crate::FieldReader<u8, u8>;
39#[doc = "Field `STOP_REQ` writer - Clock Stop Request for each TTCAN IP . The m_ttcan_clkstop_req of each TTCAN IP is directly driven by these bits."]
40pub type STOP_REQ_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CTL_SPEC, u8, u8, 8, O>;
41#[doc = "Field `MRAM_OFF` reader - MRAM off 0= Default MRAM on (with MRAM retained in DeepSleep). 1= Switch MRAM off (not retained) to save power. Before setting this bit all the CAN channels have to be powered down using the STOP_REQ/ACK bits. When the MRAM is off any access attempt to it is considered an address error (as if MRAM_SIZE=0). After switching the MRAM on again software needs to allow for a certain power up time before MRAM can be used, i.e. before STOP_REQ can be de-asserted. The power up time is equivalent to the system SRAM power up time specified in the CPUSS.RAM_PWR_DELAY_CTL register. MRAM_OFF should be set to 0 prior to transitioning to Hibernate mode."]
42pub type MRAM_OFF_R = crate::BitReader<bool>;
43#[doc = "Field `MRAM_OFF` writer - MRAM off 0= Default MRAM on (with MRAM retained in DeepSleep). 1= Switch MRAM off (not retained) to save power. Before setting this bit all the CAN channels have to be powered down using the STOP_REQ/ACK bits. When the MRAM is off any access attempt to it is considered an address error (as if MRAM_SIZE=0). After switching the MRAM on again software needs to allow for a certain power up time before MRAM can be used, i.e. before STOP_REQ can be de-asserted. The power up time is equivalent to the system SRAM power up time specified in the CPUSS.RAM_PWR_DELAY_CTL register. MRAM_OFF should be set to 0 prior to transitioning to Hibernate mode."]
44pub type MRAM_OFF_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTL_SPEC, bool, O>;
45impl R {
46    #[doc = "Bits 0:7 - Clock Stop Request for each TTCAN IP . The m_ttcan_clkstop_req of each TTCAN IP is directly driven by these bits."]
47    #[inline(always)]
48    pub fn stop_req(&self) -> STOP_REQ_R {
49        STOP_REQ_R::new((self.bits & 0xff) as u8)
50    }
51    #[doc = "Bit 31 - MRAM off 0= Default MRAM on (with MRAM retained in DeepSleep). 1= Switch MRAM off (not retained) to save power. Before setting this bit all the CAN channels have to be powered down using the STOP_REQ/ACK bits. When the MRAM is off any access attempt to it is considered an address error (as if MRAM_SIZE=0). After switching the MRAM on again software needs to allow for a certain power up time before MRAM can be used, i.e. before STOP_REQ can be de-asserted. The power up time is equivalent to the system SRAM power up time specified in the CPUSS.RAM_PWR_DELAY_CTL register. MRAM_OFF should be set to 0 prior to transitioning to Hibernate mode."]
52    #[inline(always)]
53    pub fn mram_off(&self) -> MRAM_OFF_R {
54        MRAM_OFF_R::new(((self.bits >> 31) & 1) != 0)
55    }
56}
57impl W {
58    #[doc = "Bits 0:7 - Clock Stop Request for each TTCAN IP . The m_ttcan_clkstop_req of each TTCAN IP is directly driven by these bits."]
59    #[inline(always)]
60    #[must_use]
61    pub fn stop_req(&mut self) -> STOP_REQ_W<0> {
62        STOP_REQ_W::new(self)
63    }
64    #[doc = "Bit 31 - MRAM off 0= Default MRAM on (with MRAM retained in DeepSleep). 1= Switch MRAM off (not retained) to save power. Before setting this bit all the CAN channels have to be powered down using the STOP_REQ/ACK bits. When the MRAM is off any access attempt to it is considered an address error (as if MRAM_SIZE=0). After switching the MRAM on again software needs to allow for a certain power up time before MRAM can be used, i.e. before STOP_REQ can be de-asserted. The power up time is equivalent to the system SRAM power up time specified in the CPUSS.RAM_PWR_DELAY_CTL register. MRAM_OFF should be set to 0 prior to transitioning to Hibernate mode."]
65    #[inline(always)]
66    #[must_use]
67    pub fn mram_off(&mut self) -> MRAM_OFF_W<31> {
68        MRAM_OFF_W::new(self)
69    }
70    #[doc = "Writes raw bits to the register."]
71    #[inline(always)]
72    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
73        self.0.bits(bits);
74        self
75    }
76}
77#[doc = "Global CAN control register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctl](index.html) module"]
78pub struct CTL_SPEC;
79impl crate::RegisterSpec for CTL_SPEC {
80    type Ux = u32;
81}
82#[doc = "`read()` method returns [ctl::R](R) reader structure"]
83impl crate::Readable for CTL_SPEC {
84    type Reader = R;
85}
86#[doc = "`write(|w| ..)` method takes [ctl::W](W) writer structure"]
87impl crate::Writable for CTL_SPEC {
88    type Writer = W;
89    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
90    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
91}
92#[doc = "`reset()` method sets CTL to value 0"]
93impl crate::Resettable for CTL_SPEC {
94    const RESET_VALUE: Self::Ux = 0;
95}
cyt2b9_c/m0/canfd0/ctl.rs

cyt2b9_c/m0/canfd0/
ctl.rs
