1#[doc = "Register `CTL` reader"]
2pub struct R(crate::R<CTL_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<CTL_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<CTL_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<CTL_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `CTL` writer"]
17pub struct W(crate::W<CTL_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<CTL_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<CTL_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<CTL_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Field `WCO_EN` reader - Watch-crystal oscillator (WCO) enable. If there is a write in progress when this bit is cleared, the WCO will be internally kept on until the write completes. After enabling the WCO software must wait until STATUS.WCO_OK=1 before configuring any component that depends on clk_lf/clk_bak, like for example RTC or WDTs. Follow the procedure in BACKUP_RTC_RW to access this bit."]
38pub type WCO_EN_R = crate::BitReader<bool>;
39#[doc = "Field `WCO_EN` writer - Watch-crystal oscillator (WCO) enable. If there is a write in progress when this bit is cleared, the WCO will be internally kept on until the write completes. After enabling the WCO software must wait until STATUS.WCO_OK=1 before configuring any component that depends on clk_lf/clk_bak, like for example RTC or WDTs. Follow the procedure in BACKUP_RTC_RW to access this bit."]
40pub type WCO_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTL_SPEC, bool, O>;
41#[doc = "Field `CLK_SEL` reader - Clock select for RTC clock"]
42pub type CLK_SEL_R = crate::FieldReader<u8, CLK_SEL_A>;
43#[doc = "Clock select for RTC clock\n\nValue on reset: 0"]
44#[derive(Clone, Copy, Debug, PartialEq, Eq)]
45#[repr(u8)]
46pub enum CLK_SEL_A {
47 #[doc = "0: Watch-crystal oscillator input, available in Active, DeepSleep and Hibernate"]
48 WCO = 0,
49 #[doc = "1: This allows to use the LFCLK selection as an alternate backup domain clock. Note that LFCLK is only available in Active and DeepSleep power modes. Note that LFCLK clock glitches can propagate into the backup logic when the clock is stopped. For this reason, if the WCO or ILO is intended as the clock source then choose it directly instead of routing through LFCLK."]
50 ALTBAK = 1,
51 #[doc = "2: Internal Low frequency Oscillator, available in Active, DeepSleep and Hibernate. For Hibernate operation CLK_ILO_CONFIG. ILO_BACKUP must be set."]
52 ILO = 2,
53 #[doc = "3: N/A"]
54 RSVD = 3,
55}
56impl From<CLK_SEL_A> for u8 {
57 #[inline(always)]
58 fn from(variant: CLK_SEL_A) -> Self {
59 variant as _
60 }
61}
62impl CLK_SEL_R {
63 #[doc = "Get enumerated values variant"]
64 #[inline(always)]
65 pub fn variant(&self) -> CLK_SEL_A {
66 match self.bits {
67 0 => CLK_SEL_A::WCO,
68 1 => CLK_SEL_A::ALTBAK,
69 2 => CLK_SEL_A::ILO,
70 3 => CLK_SEL_A::RSVD,
71 _ => unreachable!(),
72 }
73 }
74 #[doc = "Checks if the value of the field is `WCO`"]
75 #[inline(always)]
76 pub fn is_wco(&self) -> bool {
77 *self == CLK_SEL_A::WCO
78 }
79 #[doc = "Checks if the value of the field is `ALTBAK`"]
80 #[inline(always)]
81 pub fn is_altbak(&self) -> bool {
82 *self == CLK_SEL_A::ALTBAK
83 }
84 #[doc = "Checks if the value of the field is `ILO`"]
85 #[inline(always)]
86 pub fn is_ilo(&self) -> bool {
87 *self == CLK_SEL_A::ILO
88 }
89 #[doc = "Checks if the value of the field is `RSVD`"]
90 #[inline(always)]
91 pub fn is_rsvd(&self) -> bool {
92 *self == CLK_SEL_A::RSVD
93 }
94}
95#[doc = "Field `CLK_SEL` writer - Clock select for RTC clock"]
96pub type CLK_SEL_W<'a, const O: u8> =
97 crate::FieldWriterSafe<'a, u32, CTL_SPEC, u8, CLK_SEL_A, 2, O>;
98impl<'a, const O: u8> CLK_SEL_W<'a, O> {
99 #[doc = "Watch-crystal oscillator input, available in Active, DeepSleep and Hibernate"]
100 #[inline(always)]
101 pub fn wco(self) -> &'a mut W {
102 self.variant(CLK_SEL_A::WCO)
103 }
104 #[doc = "This allows to use the LFCLK selection as an alternate backup domain clock. Note that LFCLK is only available in Active and DeepSleep power modes. Note that LFCLK clock glitches can propagate into the backup logic when the clock is stopped. For this reason, if the WCO or ILO is intended as the clock source then choose it directly instead of routing through LFCLK."]
105 #[inline(always)]
106 pub fn altbak(self) -> &'a mut W {
107 self.variant(CLK_SEL_A::ALTBAK)
108 }
109 #[doc = "Internal Low frequency Oscillator, available in Active, DeepSleep and Hibernate. For Hibernate operation CLK_ILO_CONFIG. ILO_BACKUP must be set."]
110 #[inline(always)]
111 pub fn ilo(self) -> &'a mut W {
112 self.variant(CLK_SEL_A::ILO)
113 }
114 #[doc = "N/A"]
115 #[inline(always)]
116 pub fn rsvd(self) -> &'a mut W {
117 self.variant(CLK_SEL_A::RSVD)
118 }
119}
120#[doc = "Field `PRESCALER` reader - N/A"]
121pub type PRESCALER_R = crate::FieldReader<u8, u8>;
122#[doc = "Field `PRESCALER` writer - N/A"]
123pub type PRESCALER_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CTL_SPEC, u8, u8, 2, O>;
124#[doc = "Field `WCO_BYPASS` reader - Configures the WCO for different board-level connections to the WCO pins. For example, this can be used to connect an external watch crystal oscillator instead of a watch crystal. In all cases, the two related GPIO pins (WCO input and output pins) must be configured as analog connections using GPIO registers, and they must be hooked at the board level as described below. Configure this field before enabling the WCO, and do not change this setting when WCO_EN=1. 0: Watch crystal. Connect a 32.768 kHz watch crystal between WCO input and output pins. 1: Clock signal, either a square wave or sine wave. See PRESCALER field for connection information."]
125pub type WCO_BYPASS_R = crate::BitReader<bool>;
126#[doc = "Field `WCO_BYPASS` writer - Configures the WCO for different board-level connections to the WCO pins. For example, this can be used to connect an external watch crystal oscillator instead of a watch crystal. In all cases, the two related GPIO pins (WCO input and output pins) must be configured as analog connections using GPIO registers, and they must be hooked at the board level as described below. Configure this field before enabling the WCO, and do not change this setting when WCO_EN=1. 0: Watch crystal. Connect a 32.768 kHz watch crystal between WCO input and output pins. 1: Clock signal, either a square wave or sine wave. See PRESCALER field for connection information."]
127pub type WCO_BYPASS_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTL_SPEC, bool, O>;
128#[doc = "Field `VDDBAK_CTL` reader - Controls the behavior of the switch that generates vddbak from vbackup or vddd. 0: automatically select vddd if its brownout detector says it is valid. If the brownout says its not valid, then use vmax which is the highest of vddd or vbackup. 1,2,3: force vddbak and vmax to select vbackup, regardless of its voltage."]
129pub type VDDBAK_CTL_R = crate::FieldReader<u8, u8>;
130#[doc = "Field `VDDBAK_CTL` writer - Controls the behavior of the switch that generates vddbak from vbackup or vddd. 0: automatically select vddd if its brownout detector says it is valid. If the brownout says its not valid, then use vmax which is the highest of vddd or vbackup. 1,2,3: force vddbak and vmax to select vbackup, regardless of its voltage."]
131pub type VDDBAK_CTL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CTL_SPEC, u8, u8, 2, O>;
132#[doc = "Field `VBACKUP_MEAS` reader - Connect vbackup supply to the vbackup_meas output for measurement by an ADC attached to amuxbusa_adft_vddd. The vbackup_meas signal is scaled to 10 percent of vbackup, so it is within the supply range of the ADC."]
133pub type VBACKUP_MEAS_R = crate::BitReader<bool>;
134#[doc = "Field `VBACKUP_MEAS` writer - Connect vbackup supply to the vbackup_meas output for measurement by an ADC attached to amuxbusa_adft_vddd. The vbackup_meas signal is scaled to 10 percent of vbackup, so it is within the supply range of the ADC."]
135pub type VBACKUP_MEAS_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTL_SPEC, bool, O>;
136#[doc = "Field `EN_CHARGE_KEY` reader - When set to 3C, the supercap charger circuit is enabled. Any other code disables the supercap charger. THIS CHARGING CIRCUIT IS FOR A SUPERCAP ONLY AND CANNOT SAFELY CHARGE A BATTERY. DO NOT WRITE THIS KEY WHEN VBACKUP IS CONNECTED TO A BATTERY."]
137pub type EN_CHARGE_KEY_R = crate::FieldReader<u8, u8>;
138#[doc = "Field `EN_CHARGE_KEY` writer - When set to 3C, the supercap charger circuit is enabled. Any other code disables the supercap charger. THIS CHARGING CIRCUIT IS FOR A SUPERCAP ONLY AND CANNOT SAFELY CHARGE A BATTERY. DO NOT WRITE THIS KEY WHEN VBACKUP IS CONNECTED TO A BATTERY."]
139pub type EN_CHARGE_KEY_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CTL_SPEC, u8, u8, 8, O>;
140impl R {
141 #[doc = "Bit 3 - Watch-crystal oscillator (WCO) enable. If there is a write in progress when this bit is cleared, the WCO will be internally kept on until the write completes. After enabling the WCO software must wait until STATUS.WCO_OK=1 before configuring any component that depends on clk_lf/clk_bak, like for example RTC or WDTs. Follow the procedure in BACKUP_RTC_RW to access this bit."]
142 #[inline(always)]
143 pub fn wco_en(&self) -> WCO_EN_R {
144 WCO_EN_R::new(((self.bits >> 3) & 1) != 0)
145 }
146 #[doc = "Bits 8:9 - Clock select for RTC clock"]
147 #[inline(always)]
148 pub fn clk_sel(&self) -> CLK_SEL_R {
149 CLK_SEL_R::new(((self.bits >> 8) & 3) as u8)
150 }
151 #[doc = "Bits 12:13 - N/A"]
152 #[inline(always)]
153 pub fn prescaler(&self) -> PRESCALER_R {
154 PRESCALER_R::new(((self.bits >> 12) & 3) as u8)
155 }
156 #[doc = "Bit 16 - Configures the WCO for different board-level connections to the WCO pins. For example, this can be used to connect an external watch crystal oscillator instead of a watch crystal. In all cases, the two related GPIO pins (WCO input and output pins) must be configured as analog connections using GPIO registers, and they must be hooked at the board level as described below. Configure this field before enabling the WCO, and do not change this setting when WCO_EN=1. 0: Watch crystal. Connect a 32.768 kHz watch crystal between WCO input and output pins. 1: Clock signal, either a square wave or sine wave. See PRESCALER field for connection information."]
157 #[inline(always)]
158 pub fn wco_bypass(&self) -> WCO_BYPASS_R {
159 WCO_BYPASS_R::new(((self.bits >> 16) & 1) != 0)
160 }
161 #[doc = "Bits 17:18 - Controls the behavior of the switch that generates vddbak from vbackup or vddd. 0: automatically select vddd if its brownout detector says it is valid. If the brownout says its not valid, then use vmax which is the highest of vddd or vbackup. 1,2,3: force vddbak and vmax to select vbackup, regardless of its voltage."]
162 #[inline(always)]
163 pub fn vddbak_ctl(&self) -> VDDBAK_CTL_R {
164 VDDBAK_CTL_R::new(((self.bits >> 17) & 3) as u8)
165 }
166 #[doc = "Bit 19 - Connect vbackup supply to the vbackup_meas output for measurement by an ADC attached to amuxbusa_adft_vddd. The vbackup_meas signal is scaled to 10 percent of vbackup, so it is within the supply range of the ADC."]
167 #[inline(always)]
168 pub fn vbackup_meas(&self) -> VBACKUP_MEAS_R {
169 VBACKUP_MEAS_R::new(((self.bits >> 19) & 1) != 0)
170 }
171 #[doc = "Bits 24:31 - When set to 3C, the supercap charger circuit is enabled. Any other code disables the supercap charger. THIS CHARGING CIRCUIT IS FOR A SUPERCAP ONLY AND CANNOT SAFELY CHARGE A BATTERY. DO NOT WRITE THIS KEY WHEN VBACKUP IS CONNECTED TO A BATTERY."]
172 #[inline(always)]
173 pub fn en_charge_key(&self) -> EN_CHARGE_KEY_R {
174 EN_CHARGE_KEY_R::new(((self.bits >> 24) & 0xff) as u8)
175 }
176}
177impl W {
178 #[doc = "Bit 3 - Watch-crystal oscillator (WCO) enable. If there is a write in progress when this bit is cleared, the WCO will be internally kept on until the write completes. After enabling the WCO software must wait until STATUS.WCO_OK=1 before configuring any component that depends on clk_lf/clk_bak, like for example RTC or WDTs. Follow the procedure in BACKUP_RTC_RW to access this bit."]
179 #[inline(always)]
180 #[must_use]
181 pub fn wco_en(&mut self) -> WCO_EN_W<3> {
182 WCO_EN_W::new(self)
183 }
184 #[doc = "Bits 8:9 - Clock select for RTC clock"]
185 #[inline(always)]
186 #[must_use]
187 pub fn clk_sel(&mut self) -> CLK_SEL_W<8> {
188 CLK_SEL_W::new(self)
189 }
190 #[doc = "Bits 12:13 - N/A"]
191 #[inline(always)]
192 #[must_use]
193 pub fn prescaler(&mut self) -> PRESCALER_W<12> {
194 PRESCALER_W::new(self)
195 }
196 #[doc = "Bit 16 - Configures the WCO for different board-level connections to the WCO pins. For example, this can be used to connect an external watch crystal oscillator instead of a watch crystal. In all cases, the two related GPIO pins (WCO input and output pins) must be configured as analog connections using GPIO registers, and they must be hooked at the board level as described below. Configure this field before enabling the WCO, and do not change this setting when WCO_EN=1. 0: Watch crystal. Connect a 32.768 kHz watch crystal between WCO input and output pins. 1: Clock signal, either a square wave or sine wave. See PRESCALER field for connection information."]
197 #[inline(always)]
198 #[must_use]
199 pub fn wco_bypass(&mut self) -> WCO_BYPASS_W<16> {
200 WCO_BYPASS_W::new(self)
201 }
202 #[doc = "Bits 17:18 - Controls the behavior of the switch that generates vddbak from vbackup or vddd. 0: automatically select vddd if its brownout detector says it is valid. If the brownout says its not valid, then use vmax which is the highest of vddd or vbackup. 1,2,3: force vddbak and vmax to select vbackup, regardless of its voltage."]
203 #[inline(always)]
204 #[must_use]
205 pub fn vddbak_ctl(&mut self) -> VDDBAK_CTL_W<17> {
206 VDDBAK_CTL_W::new(self)
207 }
208 #[doc = "Bit 19 - Connect vbackup supply to the vbackup_meas output for measurement by an ADC attached to amuxbusa_adft_vddd. The vbackup_meas signal is scaled to 10 percent of vbackup, so it is within the supply range of the ADC."]
209 #[inline(always)]
210 #[must_use]
211 pub fn vbackup_meas(&mut self) -> VBACKUP_MEAS_W<19> {
212 VBACKUP_MEAS_W::new(self)
213 }
214 #[doc = "Bits 24:31 - When set to 3C, the supercap charger circuit is enabled. Any other code disables the supercap charger. THIS CHARGING CIRCUIT IS FOR A SUPERCAP ONLY AND CANNOT SAFELY CHARGE A BATTERY. DO NOT WRITE THIS KEY WHEN VBACKUP IS CONNECTED TO A BATTERY."]
215 #[inline(always)]
216 #[must_use]
217 pub fn en_charge_key(&mut self) -> EN_CHARGE_KEY_W<24> {
218 EN_CHARGE_KEY_W::new(self)
219 }
220 #[doc = "Writes raw bits to the register."]
221 #[inline(always)]
222 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
223 self.0.bits(bits);
224 self
225 }
226}
227#[doc = "Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctl](index.html) module"]
228pub struct CTL_SPEC;
229impl crate::RegisterSpec for CTL_SPEC {
230 type Ux = u32;
231}
232#[doc = "`read()` method returns [ctl::R](R) reader structure"]
233impl crate::Readable for CTL_SPEC {
234 type Reader = R;
235}
236#[doc = "`write(|w| ..)` method takes [ctl::W](W) writer structure"]
237impl crate::Writable for CTL_SPEC {
238 type Writer = W;
239 const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
240 const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
241}
242#[doc = "`reset()` method sets CTL to value 0"]
243impl crate::Resettable for CTL_SPEC {
244 const RESET_VALUE: Self::Ux = 0;
245}