1#[doc = "Register `ERROR_CTL` reader"]
2pub struct R(crate::R<ERROR_CTL_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<ERROR_CTL_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<ERROR_CTL_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<ERROR_CTL_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `ERROR_CTL` writer"]
17pub struct W(crate::W<ERROR_CTL_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<ERROR_CTL_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<ERROR_CTL_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<ERROR_CTL_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Field `CH_IDX` reader - Specifies the channel index of the channel to which HW injected channel transmitter errors applies."]
38pub type CH_IDX_R = crate::FieldReader<u8, u8>;
39#[doc = "Field `CH_IDX` writer - Specifies the channel index of the channel to which HW injected channel transmitter errors applies."]
40pub type CH_IDX_W<'a, const O: u8> = crate::FieldWriter<'a, u32, ERROR_CTL_SPEC, u8, u8, 5, O>;
41#[doc = "Field `TX_SYNC_ERROR` reader - The synchronization field is changed from 0x55 to 0x00. At the receiver, this should result in INTR.RX_HEADER_SYNC_ERROR activation."]
42pub type TX_SYNC_ERROR_R = crate::BitReader<bool>;
43#[doc = "Field `TX_SYNC_ERROR` writer - The synchronization field is changed from 0x55 to 0x00. At the receiver, this should result in INTR.RX_HEADER_SYNC_ERROR activation."]
44pub type TX_SYNC_ERROR_W<'a, const O: u8> = crate::BitWriter<'a, u32, ERROR_CTL_SPEC, bool, O>;
45#[doc = "Field `TX_SYNC_STOP_ERROR` reader - The synchronization field STOP bits are inverted to '0'. At the receiver, this should result in INTR.RX_HEADER_SYNC_ERROR or INTR.RX_HEADER_FRAME_ERROR activation."]
46pub type TX_SYNC_STOP_ERROR_R = crate::BitReader<bool>;
47#[doc = "Field `TX_SYNC_STOP_ERROR` writer - The synchronization field STOP bits are inverted to '0'. At the receiver, this should result in INTR.RX_HEADER_SYNC_ERROR or INTR.RX_HEADER_FRAME_ERROR activation."]
48pub type TX_SYNC_STOP_ERROR_W<'a, const O: u8> = crate::BitWriter<'a, u32, ERROR_CTL_SPEC, bool, O>;
49#[doc = "Field `TX_PARITY_ERROR` reader - In LIN mode, the PID parity bit P\\[1\\]
50is inverted from !(ID\\[5\\]
51^ ID\\[4\\]
52^ ID\\[3\\]
53^ ID\\[1\\]) to (ID\\[5\\]
54^ ID\\[4\\]
55^ ID\\[3\\]
56^ ID\\[1\\]). At the receiver, this should result in INTR.RX_HEADER_PARITY_ERROR activation. In UART mode, a data field's parity bit is inverted."]
57pub type TX_PARITY_ERROR_R = crate::BitReader<bool>;
58#[doc = "Field `TX_PARITY_ERROR` writer - In LIN mode, the PID parity bit P\\[1\\]
59is inverted from !(ID\\[5\\]
60^ ID\\[4\\]
61^ ID\\[3\\]
62^ ID\\[1\\]) to (ID\\[5\\]
63^ ID\\[4\\]
64^ ID\\[3\\]
65^ ID\\[1\\]). At the receiver, this should result in INTR.RX_HEADER_PARITY_ERROR activation. In UART mode, a data field's parity bit is inverted."]
66pub type TX_PARITY_ERROR_W<'a, const O: u8> = crate::BitWriter<'a, u32, ERROR_CTL_SPEC, bool, O>;
67#[doc = "Field `TX_PID_STOP_ERROR` reader - The PID field STOP bits are inverted to '0'. At the receiver, this should result in INTR.RX_HEADER_FRAME_ERROR activation."]
68pub type TX_PID_STOP_ERROR_R = crate::BitReader<bool>;
69#[doc = "Field `TX_PID_STOP_ERROR` writer - The PID field STOP bits are inverted to '0'. At the receiver, this should result in INTR.RX_HEADER_FRAME_ERROR activation."]
70pub type TX_PID_STOP_ERROR_W<'a, const O: u8> = crate::BitWriter<'a, u32, ERROR_CTL_SPEC, bool, O>;
71#[doc = "Field `TX_DATA_STOP_ERROR` reader - The data field STOP bits are inverted to '0'. At the receiver, this should result in INTR.RX_RESPONSE_FRAME_ERROR activation. Note: Used in UART mode."]
72pub type TX_DATA_STOP_ERROR_R = crate::BitReader<bool>;
73#[doc = "Field `TX_DATA_STOP_ERROR` writer - The data field STOP bits are inverted to '0'. At the receiver, this should result in INTR.RX_RESPONSE_FRAME_ERROR activation. Note: Used in UART mode."]
74pub type TX_DATA_STOP_ERROR_W<'a, const O: u8> = crate::BitWriter<'a, u32, ERROR_CTL_SPEC, bool, O>;
75#[doc = "Field `TX_CHECKSUM_ERROR` reader - The checksum field is inverted. At the receiver, this should result in INTR.RX_RESPONSE_CHECKSUM_ERROR activation."]
76pub type TX_CHECKSUM_ERROR_R = crate::BitReader<bool>;
77#[doc = "Field `TX_CHECKSUM_ERROR` writer - The checksum field is inverted. At the receiver, this should result in INTR.RX_RESPONSE_CHECKSUM_ERROR activation."]
78pub type TX_CHECKSUM_ERROR_W<'a, const O: u8> = crate::BitWriter<'a, u32, ERROR_CTL_SPEC, bool, O>;
79#[doc = "Field `TX_CHECKSUM_STOP_ERROR` reader - The checksum field STOP bits are inverted to '0'. At the receiver, this should result in INTR.RX_RESPONSE_FRAME_ERROR activation."]
80pub type TX_CHECKSUM_STOP_ERROR_R = crate::BitReader<bool>;
81#[doc = "Field `TX_CHECKSUM_STOP_ERROR` writer - The checksum field STOP bits are inverted to '0'. At the receiver, this should result in INTR.RX_RESPONSE_FRAME_ERROR activation."]
82pub type TX_CHECKSUM_STOP_ERROR_W<'a, const O: u8> =
83 crate::BitWriter<'a, u32, ERROR_CTL_SPEC, bool, O>;
84#[doc = "Field `ENABLED` reader - Error injection enable: '0': Disabled. '1': Enabled."]
85pub type ENABLED_R = crate::BitReader<bool>;
86#[doc = "Field `ENABLED` writer - Error injection enable: '0': Disabled. '1': Enabled."]
87pub type ENABLED_W<'a, const O: u8> = crate::BitWriter<'a, u32, ERROR_CTL_SPEC, bool, O>;
88impl R {
89 #[doc = "Bits 0:4 - Specifies the channel index of the channel to which HW injected channel transmitter errors applies."]
90 #[inline(always)]
91 pub fn ch_idx(&self) -> CH_IDX_R {
92 CH_IDX_R::new((self.bits & 0x1f) as u8)
93 }
94 #[doc = "Bit 16 - The synchronization field is changed from 0x55 to 0x00. At the receiver, this should result in INTR.RX_HEADER_SYNC_ERROR activation."]
95 #[inline(always)]
96 pub fn tx_sync_error(&self) -> TX_SYNC_ERROR_R {
97 TX_SYNC_ERROR_R::new(((self.bits >> 16) & 1) != 0)
98 }
99 #[doc = "Bit 17 - The synchronization field STOP bits are inverted to '0'. At the receiver, this should result in INTR.RX_HEADER_SYNC_ERROR or INTR.RX_HEADER_FRAME_ERROR activation."]
100 #[inline(always)]
101 pub fn tx_sync_stop_error(&self) -> TX_SYNC_STOP_ERROR_R {
102 TX_SYNC_STOP_ERROR_R::new(((self.bits >> 17) & 1) != 0)
103 }
104 #[doc = "Bit 18 - In LIN mode, the PID parity bit P\\[1\\]
105is inverted from !(ID\\[5\\]
106^ ID\\[4\\]
107^ ID\\[3\\]
108^ ID\\[1\\]) to (ID\\[5\\]
109^ ID\\[4\\]
110^ ID\\[3\\]
111^ ID\\[1\\]). At the receiver, this should result in INTR.RX_HEADER_PARITY_ERROR activation. In UART mode, a data field's parity bit is inverted."]
112 #[inline(always)]
113 pub fn tx_parity_error(&self) -> TX_PARITY_ERROR_R {
114 TX_PARITY_ERROR_R::new(((self.bits >> 18) & 1) != 0)
115 }
116 #[doc = "Bit 19 - The PID field STOP bits are inverted to '0'. At the receiver, this should result in INTR.RX_HEADER_FRAME_ERROR activation."]
117 #[inline(always)]
118 pub fn tx_pid_stop_error(&self) -> TX_PID_STOP_ERROR_R {
119 TX_PID_STOP_ERROR_R::new(((self.bits >> 19) & 1) != 0)
120 }
121 #[doc = "Bit 21 - The data field STOP bits are inverted to '0'. At the receiver, this should result in INTR.RX_RESPONSE_FRAME_ERROR activation. Note: Used in UART mode."]
122 #[inline(always)]
123 pub fn tx_data_stop_error(&self) -> TX_DATA_STOP_ERROR_R {
124 TX_DATA_STOP_ERROR_R::new(((self.bits >> 21) & 1) != 0)
125 }
126 #[doc = "Bit 22 - The checksum field is inverted. At the receiver, this should result in INTR.RX_RESPONSE_CHECKSUM_ERROR activation."]
127 #[inline(always)]
128 pub fn tx_checksum_error(&self) -> TX_CHECKSUM_ERROR_R {
129 TX_CHECKSUM_ERROR_R::new(((self.bits >> 22) & 1) != 0)
130 }
131 #[doc = "Bit 23 - The checksum field STOP bits are inverted to '0'. At the receiver, this should result in INTR.RX_RESPONSE_FRAME_ERROR activation."]
132 #[inline(always)]
133 pub fn tx_checksum_stop_error(&self) -> TX_CHECKSUM_STOP_ERROR_R {
134 TX_CHECKSUM_STOP_ERROR_R::new(((self.bits >> 23) & 1) != 0)
135 }
136 #[doc = "Bit 31 - Error injection enable: '0': Disabled. '1': Enabled."]
137 #[inline(always)]
138 pub fn enabled(&self) -> ENABLED_R {
139 ENABLED_R::new(((self.bits >> 31) & 1) != 0)
140 }
141}
142impl W {
143 #[doc = "Bits 0:4 - Specifies the channel index of the channel to which HW injected channel transmitter errors applies."]
144 #[inline(always)]
145 #[must_use]
146 pub fn ch_idx(&mut self) -> CH_IDX_W<0> {
147 CH_IDX_W::new(self)
148 }
149 #[doc = "Bit 16 - The synchronization field is changed from 0x55 to 0x00. At the receiver, this should result in INTR.RX_HEADER_SYNC_ERROR activation."]
150 #[inline(always)]
151 #[must_use]
152 pub fn tx_sync_error(&mut self) -> TX_SYNC_ERROR_W<16> {
153 TX_SYNC_ERROR_W::new(self)
154 }
155 #[doc = "Bit 17 - The synchronization field STOP bits are inverted to '0'. At the receiver, this should result in INTR.RX_HEADER_SYNC_ERROR or INTR.RX_HEADER_FRAME_ERROR activation."]
156 #[inline(always)]
157 #[must_use]
158 pub fn tx_sync_stop_error(&mut self) -> TX_SYNC_STOP_ERROR_W<17> {
159 TX_SYNC_STOP_ERROR_W::new(self)
160 }
161 #[doc = "Bit 18 - In LIN mode, the PID parity bit P\\[1\\]
162is inverted from !(ID\\[5\\]
163^ ID\\[4\\]
164^ ID\\[3\\]
165^ ID\\[1\\]) to (ID\\[5\\]
166^ ID\\[4\\]
167^ ID\\[3\\]
168^ ID\\[1\\]). At the receiver, this should result in INTR.RX_HEADER_PARITY_ERROR activation. In UART mode, a data field's parity bit is inverted."]
169 #[inline(always)]
170 #[must_use]
171 pub fn tx_parity_error(&mut self) -> TX_PARITY_ERROR_W<18> {
172 TX_PARITY_ERROR_W::new(self)
173 }
174 #[doc = "Bit 19 - The PID field STOP bits are inverted to '0'. At the receiver, this should result in INTR.RX_HEADER_FRAME_ERROR activation."]
175 #[inline(always)]
176 #[must_use]
177 pub fn tx_pid_stop_error(&mut self) -> TX_PID_STOP_ERROR_W<19> {
178 TX_PID_STOP_ERROR_W::new(self)
179 }
180 #[doc = "Bit 21 - The data field STOP bits are inverted to '0'. At the receiver, this should result in INTR.RX_RESPONSE_FRAME_ERROR activation. Note: Used in UART mode."]
181 #[inline(always)]
182 #[must_use]
183 pub fn tx_data_stop_error(&mut self) -> TX_DATA_STOP_ERROR_W<21> {
184 TX_DATA_STOP_ERROR_W::new(self)
185 }
186 #[doc = "Bit 22 - The checksum field is inverted. At the receiver, this should result in INTR.RX_RESPONSE_CHECKSUM_ERROR activation."]
187 #[inline(always)]
188 #[must_use]
189 pub fn tx_checksum_error(&mut self) -> TX_CHECKSUM_ERROR_W<22> {
190 TX_CHECKSUM_ERROR_W::new(self)
191 }
192 #[doc = "Bit 23 - The checksum field STOP bits are inverted to '0'. At the receiver, this should result in INTR.RX_RESPONSE_FRAME_ERROR activation."]
193 #[inline(always)]
194 #[must_use]
195 pub fn tx_checksum_stop_error(&mut self) -> TX_CHECKSUM_STOP_ERROR_W<23> {
196 TX_CHECKSUM_STOP_ERROR_W::new(self)
197 }
198 #[doc = "Bit 31 - Error injection enable: '0': Disabled. '1': Enabled."]
199 #[inline(always)]
200 #[must_use]
201 pub fn enabled(&mut self) -> ENABLED_W<31> {
202 ENABLED_W::new(self)
203 }
204 #[doc = "Writes raw bits to the register."]
205 #[inline(always)]
206 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
207 self.0.bits(bits);
208 self
209 }
210}
211#[doc = "Error control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [error_ctl](index.html) module"]
212pub struct ERROR_CTL_SPEC;
213impl crate::RegisterSpec for ERROR_CTL_SPEC {
214 type Ux = u32;
215}
216#[doc = "`read()` method returns [error_ctl::R](R) reader structure"]
217impl crate::Readable for ERROR_CTL_SPEC {
218 type Reader = R;
219}
220#[doc = "`write(|w| ..)` method takes [error_ctl::W](W) writer structure"]
221impl crate::Writable for ERROR_CTL_SPEC {
222 type Writer = W;
223 const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
224 const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
225}
226#[doc = "`reset()` method sets ERROR_CTL to value 0"]
227impl crate::Resettable for ERROR_CTL_SPEC {
228 const RESET_VALUE: Self::Ux = 0;
229}