cyt2b7_d/m0/srss/
clk_dsi_select.rs

1#[doc = "Register `CLK_DSI_SELECT[%s]` reader"]
2pub struct R(crate::R<CLK_DSI_SELECT_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CLK_DSI_SELECT_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CLK_DSI_SELECT_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CLK_DSI_SELECT_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `CLK_DSI_SELECT[%s]` writer"]
17pub struct W(crate::W<CLK_DSI_SELECT_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CLK_DSI_SELECT_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CLK_DSI_SELECT_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CLK_DSI_SELECT_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `DSI_MUX` reader - Selects a DSI source or low frequency clock for use in a clock path. The output of this mux can be selected for clock PATH&lt;i> using CLK_SELECT_PATH register. Using the output of this mux as HFCLK source will result in undefined behavior. It can be used to clocks to DSI or as reference inputs for the FLL/PLL, subject to the frequency limits of those circuits. This mux is not glitch free, so do not change the selection while it is an actively selected clock."]
38pub type DSI_MUX_R = crate::FieldReader<u8, DSI_MUX_A>;
39#[doc = "Selects a DSI source or low frequency clock for use in a clock path. The output of this mux can be selected for clock PATH&lt;i> using CLK_SELECT_PATH register. Using the output of this mux as HFCLK source will result in undefined behavior. It can be used to clocks to DSI or as reference inputs for the FLL/PLL, subject to the frequency limits of those circuits. This mux is not glitch free, so do not change the selection while it is an actively selected clock.\n\nValue on reset: 0"]
40#[derive(Clone, Copy, Debug, PartialEq, Eq)]
41#[repr(u8)]
42pub enum DSI_MUX_A {
43    #[doc = "0: DSI0 - dsi_out\\[0\\]"]
44    DSI_OUT0 = 0,
45    #[doc = "1: DSI1 - dsi_out\\[1\\]"]
46    DSI_OUT1 = 1,
47    #[doc = "2: DSI2 - dsi_out\\[2\\]"]
48    DSI_OUT2 = 2,
49    #[doc = "3: DSI3 - dsi_out\\[3\\]"]
50    DSI_OUT3 = 3,
51    #[doc = "4: DSI4 - dsi_out\\[4\\]"]
52    DSI_OUT4 = 4,
53    #[doc = "5: DSI5 - dsi_out\\[5\\]"]
54    DSI_OUT5 = 5,
55    #[doc = "6: DSI6 - dsi_out\\[6\\]"]
56    DSI_OUT6 = 6,
57    #[doc = "7: DSI7 - dsi_out\\[7\\]"]
58    DSI_OUT7 = 7,
59    #[doc = "8: DSI8 - dsi_out\\[8\\]"]
60    DSI_OUT8 = 8,
61    #[doc = "9: DSI9 - dsi_out\\[9\\]"]
62    DSI_OUT9 = 9,
63    #[doc = "10: DSI10 - dsi_out\\[10\\]"]
64    DSI_OUT10 = 10,
65    #[doc = "11: DSI11 - dsi_out\\[11\\]"]
66    DSI_OUT11 = 11,
67    #[doc = "12: DSI12 - dsi_out\\[12\\]"]
68    DSI_OUT12 = 12,
69    #[doc = "13: DSI13 - dsi_out\\[13\\]"]
70    DSI_OUT13 = 13,
71    #[doc = "14: DSI14 - dsi_out\\[14\\]"]
72    DSI_OUT14 = 14,
73    #[doc = "15: DSI15 - dsi_out\\[15\\]"]
74    DSI_OUT15 = 15,
75    #[doc = "16: ILO0 - Internal Low-speed Oscillator #0"]
76    ILO0 = 16,
77    #[doc = "17: WCO - Watch-Crystal Oscillator"]
78    WCO = 17,
79    #[doc = "18: ALTLF - Alternate Low-Frequency Clock"]
80    ALTLF = 18,
81    #[doc = "19: PILO - Precision Internal Low-speed Oscillator"]
82    PILO = 19,
83    #[doc = "20: ILO1 - Internal Low-speed Oscillator #1, if present."]
84    ILO1 = 20,
85}
86impl From<DSI_MUX_A> for u8 {
87    #[inline(always)]
88    fn from(variant: DSI_MUX_A) -> Self {
89        variant as _
90    }
91}
92impl DSI_MUX_R {
93    #[doc = "Get enumerated values variant"]
94    #[inline(always)]
95    pub fn variant(&self) -> Option<DSI_MUX_A> {
96        match self.bits {
97            0 => Some(DSI_MUX_A::DSI_OUT0),
98            1 => Some(DSI_MUX_A::DSI_OUT1),
99            2 => Some(DSI_MUX_A::DSI_OUT2),
100            3 => Some(DSI_MUX_A::DSI_OUT3),
101            4 => Some(DSI_MUX_A::DSI_OUT4),
102            5 => Some(DSI_MUX_A::DSI_OUT5),
103            6 => Some(DSI_MUX_A::DSI_OUT6),
104            7 => Some(DSI_MUX_A::DSI_OUT7),
105            8 => Some(DSI_MUX_A::DSI_OUT8),
106            9 => Some(DSI_MUX_A::DSI_OUT9),
107            10 => Some(DSI_MUX_A::DSI_OUT10),
108            11 => Some(DSI_MUX_A::DSI_OUT11),
109            12 => Some(DSI_MUX_A::DSI_OUT12),
110            13 => Some(DSI_MUX_A::DSI_OUT13),
111            14 => Some(DSI_MUX_A::DSI_OUT14),
112            15 => Some(DSI_MUX_A::DSI_OUT15),
113            16 => Some(DSI_MUX_A::ILO0),
114            17 => Some(DSI_MUX_A::WCO),
115            18 => Some(DSI_MUX_A::ALTLF),
116            19 => Some(DSI_MUX_A::PILO),
117            20 => Some(DSI_MUX_A::ILO1),
118            _ => None,
119        }
120    }
121    #[doc = "Checks if the value of the field is `DSI_OUT0`"]
122    #[inline(always)]
123    pub fn is_dsi_out0(&self) -> bool {
124        *self == DSI_MUX_A::DSI_OUT0
125    }
126    #[doc = "Checks if the value of the field is `DSI_OUT1`"]
127    #[inline(always)]
128    pub fn is_dsi_out1(&self) -> bool {
129        *self == DSI_MUX_A::DSI_OUT1
130    }
131    #[doc = "Checks if the value of the field is `DSI_OUT2`"]
132    #[inline(always)]
133    pub fn is_dsi_out2(&self) -> bool {
134        *self == DSI_MUX_A::DSI_OUT2
135    }
136    #[doc = "Checks if the value of the field is `DSI_OUT3`"]
137    #[inline(always)]
138    pub fn is_dsi_out3(&self) -> bool {
139        *self == DSI_MUX_A::DSI_OUT3
140    }
141    #[doc = "Checks if the value of the field is `DSI_OUT4`"]
142    #[inline(always)]
143    pub fn is_dsi_out4(&self) -> bool {
144        *self == DSI_MUX_A::DSI_OUT4
145    }
146    #[doc = "Checks if the value of the field is `DSI_OUT5`"]
147    #[inline(always)]
148    pub fn is_dsi_out5(&self) -> bool {
149        *self == DSI_MUX_A::DSI_OUT5
150    }
151    #[doc = "Checks if the value of the field is `DSI_OUT6`"]
152    #[inline(always)]
153    pub fn is_dsi_out6(&self) -> bool {
154        *self == DSI_MUX_A::DSI_OUT6
155    }
156    #[doc = "Checks if the value of the field is `DSI_OUT7`"]
157    #[inline(always)]
158    pub fn is_dsi_out7(&self) -> bool {
159        *self == DSI_MUX_A::DSI_OUT7
160    }
161    #[doc = "Checks if the value of the field is `DSI_OUT8`"]
162    #[inline(always)]
163    pub fn is_dsi_out8(&self) -> bool {
164        *self == DSI_MUX_A::DSI_OUT8
165    }
166    #[doc = "Checks if the value of the field is `DSI_OUT9`"]
167    #[inline(always)]
168    pub fn is_dsi_out9(&self) -> bool {
169        *self == DSI_MUX_A::DSI_OUT9
170    }
171    #[doc = "Checks if the value of the field is `DSI_OUT10`"]
172    #[inline(always)]
173    pub fn is_dsi_out10(&self) -> bool {
174        *self == DSI_MUX_A::DSI_OUT10
175    }
176    #[doc = "Checks if the value of the field is `DSI_OUT11`"]
177    #[inline(always)]
178    pub fn is_dsi_out11(&self) -> bool {
179        *self == DSI_MUX_A::DSI_OUT11
180    }
181    #[doc = "Checks if the value of the field is `DSI_OUT12`"]
182    #[inline(always)]
183    pub fn is_dsi_out12(&self) -> bool {
184        *self == DSI_MUX_A::DSI_OUT12
185    }
186    #[doc = "Checks if the value of the field is `DSI_OUT13`"]
187    #[inline(always)]
188    pub fn is_dsi_out13(&self) -> bool {
189        *self == DSI_MUX_A::DSI_OUT13
190    }
191    #[doc = "Checks if the value of the field is `DSI_OUT14`"]
192    #[inline(always)]
193    pub fn is_dsi_out14(&self) -> bool {
194        *self == DSI_MUX_A::DSI_OUT14
195    }
196    #[doc = "Checks if the value of the field is `DSI_OUT15`"]
197    #[inline(always)]
198    pub fn is_dsi_out15(&self) -> bool {
199        *self == DSI_MUX_A::DSI_OUT15
200    }
201    #[doc = "Checks if the value of the field is `ILO0`"]
202    #[inline(always)]
203    pub fn is_ilo0(&self) -> bool {
204        *self == DSI_MUX_A::ILO0
205    }
206    #[doc = "Checks if the value of the field is `WCO`"]
207    #[inline(always)]
208    pub fn is_wco(&self) -> bool {
209        *self == DSI_MUX_A::WCO
210    }
211    #[doc = "Checks if the value of the field is `ALTLF`"]
212    #[inline(always)]
213    pub fn is_altlf(&self) -> bool {
214        *self == DSI_MUX_A::ALTLF
215    }
216    #[doc = "Checks if the value of the field is `PILO`"]
217    #[inline(always)]
218    pub fn is_pilo(&self) -> bool {
219        *self == DSI_MUX_A::PILO
220    }
221    #[doc = "Checks if the value of the field is `ILO1`"]
222    #[inline(always)]
223    pub fn is_ilo1(&self) -> bool {
224        *self == DSI_MUX_A::ILO1
225    }
226}
227#[doc = "Field `DSI_MUX` writer - Selects a DSI source or low frequency clock for use in a clock path. The output of this mux can be selected for clock PATH&lt;i> using CLK_SELECT_PATH register. Using the output of this mux as HFCLK source will result in undefined behavior. It can be used to clocks to DSI or as reference inputs for the FLL/PLL, subject to the frequency limits of those circuits. This mux is not glitch free, so do not change the selection while it is an actively selected clock."]
228pub type DSI_MUX_W<'a, const O: u8> =
229    crate::FieldWriter<'a, u32, CLK_DSI_SELECT_SPEC, u8, DSI_MUX_A, 5, O>;
230impl<'a, const O: u8> DSI_MUX_W<'a, O> {
231    #[doc = "DSI0 - dsi_out\\[0\\]"]
232    #[inline(always)]
233    pub fn dsi_out0(self) -> &'a mut W {
234        self.variant(DSI_MUX_A::DSI_OUT0)
235    }
236    #[doc = "DSI1 - dsi_out\\[1\\]"]
237    #[inline(always)]
238    pub fn dsi_out1(self) -> &'a mut W {
239        self.variant(DSI_MUX_A::DSI_OUT1)
240    }
241    #[doc = "DSI2 - dsi_out\\[2\\]"]
242    #[inline(always)]
243    pub fn dsi_out2(self) -> &'a mut W {
244        self.variant(DSI_MUX_A::DSI_OUT2)
245    }
246    #[doc = "DSI3 - dsi_out\\[3\\]"]
247    #[inline(always)]
248    pub fn dsi_out3(self) -> &'a mut W {
249        self.variant(DSI_MUX_A::DSI_OUT3)
250    }
251    #[doc = "DSI4 - dsi_out\\[4\\]"]
252    #[inline(always)]
253    pub fn dsi_out4(self) -> &'a mut W {
254        self.variant(DSI_MUX_A::DSI_OUT4)
255    }
256    #[doc = "DSI5 - dsi_out\\[5\\]"]
257    #[inline(always)]
258    pub fn dsi_out5(self) -> &'a mut W {
259        self.variant(DSI_MUX_A::DSI_OUT5)
260    }
261    #[doc = "DSI6 - dsi_out\\[6\\]"]
262    #[inline(always)]
263    pub fn dsi_out6(self) -> &'a mut W {
264        self.variant(DSI_MUX_A::DSI_OUT6)
265    }
266    #[doc = "DSI7 - dsi_out\\[7\\]"]
267    #[inline(always)]
268    pub fn dsi_out7(self) -> &'a mut W {
269        self.variant(DSI_MUX_A::DSI_OUT7)
270    }
271    #[doc = "DSI8 - dsi_out\\[8\\]"]
272    #[inline(always)]
273    pub fn dsi_out8(self) -> &'a mut W {
274        self.variant(DSI_MUX_A::DSI_OUT8)
275    }
276    #[doc = "DSI9 - dsi_out\\[9\\]"]
277    #[inline(always)]
278    pub fn dsi_out9(self) -> &'a mut W {
279        self.variant(DSI_MUX_A::DSI_OUT9)
280    }
281    #[doc = "DSI10 - dsi_out\\[10\\]"]
282    #[inline(always)]
283    pub fn dsi_out10(self) -> &'a mut W {
284        self.variant(DSI_MUX_A::DSI_OUT10)
285    }
286    #[doc = "DSI11 - dsi_out\\[11\\]"]
287    #[inline(always)]
288    pub fn dsi_out11(self) -> &'a mut W {
289        self.variant(DSI_MUX_A::DSI_OUT11)
290    }
291    #[doc = "DSI12 - dsi_out\\[12\\]"]
292    #[inline(always)]
293    pub fn dsi_out12(self) -> &'a mut W {
294        self.variant(DSI_MUX_A::DSI_OUT12)
295    }
296    #[doc = "DSI13 - dsi_out\\[13\\]"]
297    #[inline(always)]
298    pub fn dsi_out13(self) -> &'a mut W {
299        self.variant(DSI_MUX_A::DSI_OUT13)
300    }
301    #[doc = "DSI14 - dsi_out\\[14\\]"]
302    #[inline(always)]
303    pub fn dsi_out14(self) -> &'a mut W {
304        self.variant(DSI_MUX_A::DSI_OUT14)
305    }
306    #[doc = "DSI15 - dsi_out\\[15\\]"]
307    #[inline(always)]
308    pub fn dsi_out15(self) -> &'a mut W {
309        self.variant(DSI_MUX_A::DSI_OUT15)
310    }
311    #[doc = "ILO0 - Internal Low-speed Oscillator #0"]
312    #[inline(always)]
313    pub fn ilo0(self) -> &'a mut W {
314        self.variant(DSI_MUX_A::ILO0)
315    }
316    #[doc = "WCO - Watch-Crystal Oscillator"]
317    #[inline(always)]
318    pub fn wco(self) -> &'a mut W {
319        self.variant(DSI_MUX_A::WCO)
320    }
321    #[doc = "ALTLF - Alternate Low-Frequency Clock"]
322    #[inline(always)]
323    pub fn altlf(self) -> &'a mut W {
324        self.variant(DSI_MUX_A::ALTLF)
325    }
326    #[doc = "PILO - Precision Internal Low-speed Oscillator"]
327    #[inline(always)]
328    pub fn pilo(self) -> &'a mut W {
329        self.variant(DSI_MUX_A::PILO)
330    }
331    #[doc = "ILO1 - Internal Low-speed Oscillator #1, if present."]
332    #[inline(always)]
333    pub fn ilo1(self) -> &'a mut W {
334        self.variant(DSI_MUX_A::ILO1)
335    }
336}
337impl R {
338    #[doc = "Bits 0:4 - Selects a DSI source or low frequency clock for use in a clock path. The output of this mux can be selected for clock PATH&lt;i> using CLK_SELECT_PATH register. Using the output of this mux as HFCLK source will result in undefined behavior. It can be used to clocks to DSI or as reference inputs for the FLL/PLL, subject to the frequency limits of those circuits. This mux is not glitch free, so do not change the selection while it is an actively selected clock."]
339    #[inline(always)]
340    pub fn dsi_mux(&self) -> DSI_MUX_R {
341        DSI_MUX_R::new((self.bits & 0x1f) as u8)
342    }
343}
344impl W {
345    #[doc = "Bits 0:4 - Selects a DSI source or low frequency clock for use in a clock path. The output of this mux can be selected for clock PATH&lt;i> using CLK_SELECT_PATH register. Using the output of this mux as HFCLK source will result in undefined behavior. It can be used to clocks to DSI or as reference inputs for the FLL/PLL, subject to the frequency limits of those circuits. This mux is not glitch free, so do not change the selection while it is an actively selected clock."]
346    #[inline(always)]
347    #[must_use]
348    pub fn dsi_mux(&mut self) -> DSI_MUX_W<0> {
349        DSI_MUX_W::new(self)
350    }
351    #[doc = "Writes raw bits to the register."]
352    #[inline(always)]
353    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
354        self.0.bits(bits);
355        self
356    }
357}
358#[doc = "Clock DSI Select Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clk_dsi_select](index.html) module"]
359pub struct CLK_DSI_SELECT_SPEC;
360impl crate::RegisterSpec for CLK_DSI_SELECT_SPEC {
361    type Ux = u32;
362}
363#[doc = "`read()` method returns [clk_dsi_select::R](R) reader structure"]
364impl crate::Readable for CLK_DSI_SELECT_SPEC {
365    type Reader = R;
366}
367#[doc = "`write(|w| ..)` method takes [clk_dsi_select::W](W) writer structure"]
368impl crate::Writable for CLK_DSI_SELECT_SPEC {
369    type Writer = W;
370    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
371    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
372}
373#[doc = "`reset()` method sets CLK_DSI_SELECT[%s]
374to value 0"]
375impl crate::Resettable for CLK_DSI_SELECT_SPEC {
376    const RESET_VALUE: Self::Ux = 0;
377}
cyt2b7_d/m0/srss/clk_dsi_select.rs

cyt2b7_d/m0/srss/
clk_dsi_select.rs
