cw32f030_hal/svd/sysctrl/
debug.rs

1#[doc = "Register `DEBUG` reader"]
2pub type R = crate::svd::R<DEBUG_SPEC>;
3#[doc = "Register `DEBUG` writer"]
4pub type W = crate::svd::W<DEBUG_SPEC>;
5#[doc = "Field `ATIM` reader - desc ATIM"]
6pub type ATIM_R = crate::svd::BitReader;
7#[doc = "Field `ATIM` writer - desc ATIM"]
8pub type ATIM_W<'a, REG, const O: u8> = crate::svd::BitWriter<'a, REG, O>;
9#[doc = "Field `GTIM1` reader - desc GTIM1"]
10pub type GTIM1_R = crate::svd::BitReader;
11#[doc = "Field `GTIM1` writer - desc GTIM1"]
12pub type GTIM1_W<'a, REG, const O: u8> = crate::svd::BitWriter<'a, REG, O>;
13#[doc = "Field `GTIM2` reader - desc GTIM2"]
14pub type GTIM2_R = crate::svd::BitReader;
15#[doc = "Field `GTIM2` writer - desc GTIM2"]
16pub type GTIM2_W<'a, REG, const O: u8> = crate::svd::BitWriter<'a, REG, O>;
17#[doc = "Field `GTIM3` reader - desc GTIM3"]
18pub type GTIM3_R = crate::svd::BitReader;
19#[doc = "Field `GTIM3` writer - desc GTIM3"]
20pub type GTIM3_W<'a, REG, const O: u8> = crate::svd::BitWriter<'a, REG, O>;
21#[doc = "Field `GTIM4` reader - desc GTIM4"]
22pub type GTIM4_R = crate::svd::BitReader;
23#[doc = "Field `GTIM4` writer - desc GTIM4"]
24pub type GTIM4_W<'a, REG, const O: u8> = crate::svd::BitWriter<'a, REG, O>;
25#[doc = "Field `BTIM123` reader - desc BTIM123"]
26pub type BTIM123_R = crate::svd::BitReader;
27#[doc = "Field `BTIM123` writer - desc BTIM123"]
28pub type BTIM123_W<'a, REG, const O: u8> = crate::svd::BitWriter<'a, REG, O>;
29#[doc = "Field `AWT` reader - desc AWT"]
30pub type AWT_R = crate::svd::BitReader;
31#[doc = "Field `AWT` writer - desc AWT"]
32pub type AWT_W<'a, REG, const O: u8> = crate::svd::BitWriter<'a, REG, O>;
33#[doc = "Field `RTC` reader - desc RTC"]
34pub type RTC_R = crate::svd::BitReader;
35#[doc = "Field `RTC` writer - desc RTC"]
36pub type RTC_W<'a, REG, const O: u8> = crate::svd::BitWriter<'a, REG, O>;
37#[doc = "Field `IWDT` reader - desc IWDT"]
38pub type IWDT_R = crate::svd::BitReader;
39#[doc = "Field `IWDT` writer - desc IWDT"]
40pub type IWDT_W<'a, REG, const O: u8> = crate::svd::BitWriter<'a, REG, O>;
41#[doc = "Field `WWDT` reader - desc WWDT"]
42pub type WWDT_R = crate::svd::BitReader;
43#[doc = "Field `WWDT` writer - desc WWDT"]
44pub type WWDT_W<'a, REG, const O: u8> = crate::svd::BitWriter<'a, REG, O>;
45impl R {
46    #[doc = "Bit 0 - desc ATIM"]
47    #[inline(always)]
48    pub fn atim(&self) -> ATIM_R {
49        ATIM_R::new((self.bits & 1) != 0)
50    }
51    #[doc = "Bit 1 - desc GTIM1"]
52    #[inline(always)]
53    pub fn gtim1(&self) -> GTIM1_R {
54        GTIM1_R::new(((self.bits >> 1) & 1) != 0)
55    }
56    #[doc = "Bit 2 - desc GTIM2"]
57    #[inline(always)]
58    pub fn gtim2(&self) -> GTIM2_R {
59        GTIM2_R::new(((self.bits >> 2) & 1) != 0)
60    }
61    #[doc = "Bit 3 - desc GTIM3"]
62    #[inline(always)]
63    pub fn gtim3(&self) -> GTIM3_R {
64        GTIM3_R::new(((self.bits >> 3) & 1) != 0)
65    }
66    #[doc = "Bit 4 - desc GTIM4"]
67    #[inline(always)]
68    pub fn gtim4(&self) -> GTIM4_R {
69        GTIM4_R::new(((self.bits >> 4) & 1) != 0)
70    }
71    #[doc = "Bit 5 - desc BTIM123"]
72    #[inline(always)]
73    pub fn btim123(&self) -> BTIM123_R {
74        BTIM123_R::new(((self.bits >> 5) & 1) != 0)
75    }
76    #[doc = "Bit 6 - desc AWT"]
77    #[inline(always)]
78    pub fn awt(&self) -> AWT_R {
79        AWT_R::new(((self.bits >> 6) & 1) != 0)
80    }
81    #[doc = "Bit 8 - desc RTC"]
82    #[inline(always)]
83    pub fn rtc(&self) -> RTC_R {
84        RTC_R::new(((self.bits >> 8) & 1) != 0)
85    }
86    #[doc = "Bit 9 - desc IWDT"]
87    #[inline(always)]
88    pub fn iwdt(&self) -> IWDT_R {
89        IWDT_R::new(((self.bits >> 9) & 1) != 0)
90    }
91    #[doc = "Bit 10 - desc WWDT"]
92    #[inline(always)]
93    pub fn wwdt(&self) -> WWDT_R {
94        WWDT_R::new(((self.bits >> 10) & 1) != 0)
95    }
96}
97impl W {
98    #[doc = "Bit 0 - desc ATIM"]
99    #[inline(always)]
100    #[must_use]
101    pub fn atim(&mut self) -> ATIM_W<DEBUG_SPEC, 0> {
102        ATIM_W::new(self)
103    }
104    #[doc = "Bit 1 - desc GTIM1"]
105    #[inline(always)]
106    #[must_use]
107    pub fn gtim1(&mut self) -> GTIM1_W<DEBUG_SPEC, 1> {
108        GTIM1_W::new(self)
109    }
110    #[doc = "Bit 2 - desc GTIM2"]
111    #[inline(always)]
112    #[must_use]
113    pub fn gtim2(&mut self) -> GTIM2_W<DEBUG_SPEC, 2> {
114        GTIM2_W::new(self)
115    }
116    #[doc = "Bit 3 - desc GTIM3"]
117    #[inline(always)]
118    #[must_use]
119    pub fn gtim3(&mut self) -> GTIM3_W<DEBUG_SPEC, 3> {
120        GTIM3_W::new(self)
121    }
122    #[doc = "Bit 4 - desc GTIM4"]
123    #[inline(always)]
124    #[must_use]
125    pub fn gtim4(&mut self) -> GTIM4_W<DEBUG_SPEC, 4> {
126        GTIM4_W::new(self)
127    }
128    #[doc = "Bit 5 - desc BTIM123"]
129    #[inline(always)]
130    #[must_use]
131    pub fn btim123(&mut self) -> BTIM123_W<DEBUG_SPEC, 5> {
132        BTIM123_W::new(self)
133    }
134    #[doc = "Bit 6 - desc AWT"]
135    #[inline(always)]
136    #[must_use]
137    pub fn awt(&mut self) -> AWT_W<DEBUG_SPEC, 6> {
138        AWT_W::new(self)
139    }
140    #[doc = "Bit 8 - desc RTC"]
141    #[inline(always)]
142    #[must_use]
143    pub fn rtc(&mut self) -> RTC_W<DEBUG_SPEC, 8> {
144        RTC_W::new(self)
145    }
146    #[doc = "Bit 9 - desc IWDT"]
147    #[inline(always)]
148    #[must_use]
149    pub fn iwdt(&mut self) -> IWDT_W<DEBUG_SPEC, 9> {
150        IWDT_W::new(self)
151    }
152    #[doc = "Bit 10 - desc WWDT"]
153    #[inline(always)]
154    #[must_use]
155    pub fn wwdt(&mut self) -> WWDT_W<DEBUG_SPEC, 10> {
156        WWDT_W::new(self)
157    }
158    #[doc = r" Writes raw bits to the register."]
159    #[doc = r""]
160    #[doc = r" # Safety"]
161    #[doc = r""]
162    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
163    #[inline(always)]
164    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
165        self.bits = bits;
166        self
167    }
168}
169#[doc = "Debug Control Reg\n\nYou can [`read`](crate::svd::generic::Reg::read) this register and get [`debug::R`](R).  You can [`reset`](crate::svd::generic::Reg::reset), [`write`](crate::svd::generic::Reg::write), [`write_with_zero`](crate::svd::generic::Reg::write_with_zero) this register using [`debug::W`](W). You can also [`modify`](crate::svd::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
170pub struct DEBUG_SPEC;
171impl crate::svd::RegisterSpec for DEBUG_SPEC {
172    type Ux = u32;
173}
174#[doc = "`read()` method returns [`debug::R`](R) reader structure"]
175impl crate::svd::Readable for DEBUG_SPEC {}
176#[doc = "`write(|w| ..)` method takes [`debug::W`](W) writer structure"]
177impl crate::svd::Writable for DEBUG_SPEC {
178    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
179    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
180}
181#[doc = "`reset()` method sets DEBUG to value 0"]
182impl crate::svd::Resettable for DEBUG_SPEC {
183    const RESET_VALUE: Self::Ux = 0;
184}
cw32f030_hal/svd/sysctrl/debug.rs

cw32f030_hal/svd/sysctrl/
debug.rs
