Module codec 

Register addresses and per-register encoding and decoding for the SCDC register map (HDMI 2.1 §10.4), without I/O.

Scdc uses these to turn register bytes into culvert’s types and back; culvert-async’s client uses the same functions, so the register map exists once. A client only performs the reads and writes: which registers each operation touches is given by the address constants here.

The constants cover every register culvert accesses, plus the CED checksum, which is documented but not decoded yet. Update_1 (0x11), Test_Config_0 (0xC0) and the manufacturer identification registers (0xD0 onwards) are described in doc/roadmap.md.

Constants

CED_REGISTERS

The registers decode_ced takes, in order: each lane’s low and high byte, skipping the checksum at 0x56.

CONFIG_0

Config_0 (§10.4.4).

CONFIG_1

Config_1 (§10.4.4).

ERR_DET_0_H

ERR_DET_0_H (§10.4.5).

ERR_DET_0_L

ERR_DET_0_L (§10.4.5).

ERR_DET_1_H

ERR_DET_1_H (§10.4.5).

ERR_DET_1_L

ERR_DET_1_L (§10.4.5).

ERR_DET_2_H

ERR_DET_2_H (§10.4.5).

ERR_DET_2_L

ERR_DET_2_L (§10.4.5).

ERR_DET_3_H

ERR_DET_3_H (§10.4.5).

ERR_DET_3_L

ERR_DET_3_L (§10.4.5).

ERR_DET_CHECKSUM

The checksum over the CED registers (§10.4.5); documented, not decoded yet.

RS_CORRECTION_H

RS_Correction_H: the Reed-Solomon correction count, high byte (FRL).

RS_CORRECTION_L

RS_Correction_L: the Reed-Solomon correction count, low byte (FRL).

SCRAMBLER_STATUS

Scrambler_Status (§10.4.3).

SINK_VERSION

Sink_Version (§10.4.1).

SOURCE_TEST_CONFIG

Source_Test_Configuration (§10.4.4).

SOURCE_VERSION

Source_Version (§10.4.1).

STATUS_FLAGS_0

Status_Flags_0 (§10.4.4).

STATUS_FLAGS_1

Status_Flags_1 (§10.4.4): link training requests for lanes 0–1.

STATUS_FLAGS_2

Status_Flags_2 (§10.4.4): link training requests for lanes 2–3.

TMDS_CONFIG

TMDS_Config (§10.4.3).

UPDATE_0

Update_0 (§10.4.2). Update_1 (0x11) defines no fields in the HDMI 2.1 implementations this map is based on, so it is not accessed.

Functions

decode_ced

Decodes the per-lane character error counts from the bytes of CED_REGISTERS, in that order. Each high byte’s bit 7 is a validity flag; a lane whose flag is clear is None.

decode_ltp_requests

Decodes the per-lane link training requests from Status_Flags_1 (lanes 0–1) and Status_Flags_2 (lanes 2–3), one nibble per lane, low nibble first.

decode_rs_correction

Decodes the Reed-Solomon correction count from RS_Correction_L/H; None if the high byte’s validity bit (bit 7) is not set.

decode_scrambler_status

Decodes Scrambler_Status: the sink confirms TMDS scrambling is active (bit 0).

decode_source_test_config

Decodes Source_Test_Configuration. Bits 0 and 4 are reserved.

decode_status_flags

Decodes Status_Flags_0: clock detection, lane lock, FLT_Ready and DSC decode failure.

decode_update_flags

Decodes Update_0.

encode_clear_update_flags

Encodes the Update_0 write that clears the flags set in flags (write 1 to clear). RR_Test (bit 2) is never written: ClearableUpdateFlags has no field for it.

encode_config_0

Encodes Config_0: RR_Enable (bit 0) and FLT_No_Retrain (bit 1).

encode_config_1

Encodes Config_1: FRL_Rate in bits[3:0] and FFE_Levels in bits[7:4].

encode_tmds_config

Encodes TMDS_Config: Scrambling_Enable (bit 0) and TMDS_Bit_Clock_Ratio (bit 1).