AVR decoders implemented as part of the
yaxpeax project. Implements traits provided by
brbsinstructions are displayed as their equivalent pseudo-instructions, based on the bit they test:
brbc 0, labelbecomes
brsh label. In this case specifically,
brccalso exists (and is identical), however
brshwill be displayed.
- Target specification is limited to enabling/disabling support for 16-bit
ldsinstructions (as they can collide with other instructions cores with support for them don't have). Valid instructions (even if they might be unsupported by a core) are never rejected. Bytes which don't resemble an instruction from any instruction set subset are still invalid.