Type Alias xmc4800::usic0_ch0::dx1cr::DCEN_W

pub type DCEN_W<'a, REG> = BitWriter<'a, REG, DCEN_A>;

Field DCEN writer - Delay Compensation Enable

Aliased Type

struct DCEN_W<'a, REG> { /* private fields */ }

Implementations

impl<'a, REG> DCEN_W<'a, REG>

where REG: Writable + RegisterSpec,

pub fn value1(self) -> &'a mut W<REG>

The receive shift clock is dependent on INSW selection.

pub fn value2(self) -> &'a mut W<REG>

The receive shift clock is connected to the selected data input line. This setting is used if delay compensation is required in SSC and IIS protocols, else DCEN should always be 0.