pub type W = W<BUSWCON0_SPEC>;
Expand description
Register BUSWCON0
writer
Aliased Type§
struct W { /* private fields */ }
Implementations§
source§impl W
impl W
sourcepub fn fetblen(&mut self) -> FETBLEN_W<'_, BUSWCON0_SPEC>
pub fn fetblen(&mut self) -> FETBLEN_W<'_, BUSWCON0_SPEC>
Bits 0:2 - Burst Length for Synchronous Burst
sourcepub fn fbbmsel(&mut self) -> FBBMSEL_W<'_, BUSWCON0_SPEC>
pub fn fbbmsel(&mut self) -> FBBMSEL_W<'_, BUSWCON0_SPEC>
Bit 3 - Synchronous burst buffer mode select
sourcepub fn ecse(&mut self) -> ECSE_W<'_, BUSWCON0_SPEC>
pub fn ecse(&mut self) -> ECSE_W<'_, BUSWCON0_SPEC>
Bit 16 - Early Chip Select for Synchronous Burst
sourcepub fn ebse(&mut self) -> EBSE_W<'_, BUSWCON0_SPEC>
pub fn ebse(&mut self) -> EBSE_W<'_, BUSWCON0_SPEC>
Bit 17 - Early Burst Signal Enable for Synchronous Burst
sourcepub fn waitinv(&mut self) -> WAITINV_W<'_, BUSWCON0_SPEC>
pub fn waitinv(&mut self) -> WAITINV_W<'_, BUSWCON0_SPEC>
Bit 19 - Reversed polarity at WAIT
sourcepub fn bcgen(&mut self) -> BCGEN_W<'_, BUSWCON0_SPEC>
pub fn bcgen(&mut self) -> BCGEN_W<'_, BUSWCON0_SPEC>
Bits 20:21 - Byte Control Signal Control
sourcepub fn wait(&mut self) -> WAIT_W<'_, BUSWCON0_SPEC>
pub fn wait(&mut self) -> WAIT_W<'_, BUSWCON0_SPEC>
Bits 24:25 - External Wait Control: 0=OFF (default after reset)., 1=Asynchronous input at WAIT., 2=Synchronous input at WAIT., 3=reserved., 0=OFF (default after reset)., 1=Wait for page load (Early WAIT)., 2=Wait for page load (WAIT with data)., 3=Abort and retry access.,
sourcepub fn aap(&mut self) -> AAP_W<'_, BUSWCON0_SPEC>
pub fn aap(&mut self) -> AAP_W<'_, BUSWCON0_SPEC>
Bit 26 - Asynchronous Address phase:
sourcepub fn lockcs(&mut self) -> LOCKCS_W<'_, BUSWCON0_SPEC>
pub fn lockcs(&mut self) -> LOCKCS_W<'_, BUSWCON0_SPEC>
Bit 27 - Lock Chip Select
sourcepub fn agen(&mut self) -> AGEN_W<'_, BUSWCON0_SPEC>
pub fn agen(&mut self) -> AGEN_W<'_, BUSWCON0_SPEC>
Bits 28:31 - Device Type for Region