#[repr(u8)]pub enum CLKSEL_A {
VALUE1 = 0,
VALUE3 = 2,
VALUE4 = 3,
}
Expand description
Clock Selection
Value on reset: 0
Variants§
VALUE1 = 0
0: The fractional divider frequency fFD is selected.
VALUE3 = 2
2: The trigger signal DX1T defines fPIN. Signal MCLK toggles with fPIN.
VALUE4 = 3
3: Signal MCLK corresponds to the DX1S signal and the frequency fPIN is derived from the rising edges of DX1S.
Trait Implementations§
source§impl PartialEq for CLKSEL_A
impl PartialEq for CLKSEL_A
impl Copy for CLKSEL_A
impl Eq for CLKSEL_A
impl IsEnum for CLKSEL_A
impl StructuralPartialEq for CLKSEL_A
Auto Trait Implementations§
impl Freeze for CLKSEL_A
impl RefUnwindSafe for CLKSEL_A
impl Send for CLKSEL_A
impl Sync for CLKSEL_A
impl Unpin for CLKSEL_A
impl UnwindSafe for CLKSEL_A
Blanket Implementations§
source§impl<T> BorrowMut<T> for Twhere
T: ?Sized,
impl<T> BorrowMut<T> for Twhere
T: ?Sized,
source§fn borrow_mut(&mut self) -> &mut T
fn borrow_mut(&mut self) -> &mut T
Mutably borrows from an owned value. Read more