xmc4300/scu_interrupt/
srmsk.rs

1#[doc = "Register `SRMSK` reader"]
2pub type R = crate::R<SRMSK_SPEC>;
3#[doc = "Register `SRMSK` writer"]
4pub type W = crate::W<SRMSK_SPEC>;
5#[doc = "WDT pre-warning Interrupt Mask\n\nValue on reset: 0"]
6#[derive(Clone, Copy, Debug, PartialEq, Eq)]
7pub enum PRWARN_A {
8    #[doc = "0: Disabled"]
9    CONST_0 = 0,
10    #[doc = "1: Enabled"]
11    CONST_1 = 1,
12}
13impl From<PRWARN_A> for bool {
14    #[inline(always)]
15    fn from(variant: PRWARN_A) -> Self {
16        variant as u8 != 0
17    }
18}
19#[doc = "Field `PRWARN` reader - WDT pre-warning Interrupt Mask"]
20pub type PRWARN_R = crate::BitReader<PRWARN_A>;
21impl PRWARN_R {
22    #[doc = "Get enumerated values variant"]
23    #[inline(always)]
24    pub const fn variant(&self) -> PRWARN_A {
25        match self.bits {
26            false => PRWARN_A::CONST_0,
27            true => PRWARN_A::CONST_1,
28        }
29    }
30    #[doc = "Disabled"]
31    #[inline(always)]
32    pub fn is_const_0(&self) -> bool {
33        *self == PRWARN_A::CONST_0
34    }
35    #[doc = "Enabled"]
36    #[inline(always)]
37    pub fn is_const_1(&self) -> bool {
38        *self == PRWARN_A::CONST_1
39    }
40}
41#[doc = "Field `PRWARN` writer - WDT pre-warning Interrupt Mask"]
42pub type PRWARN_W<'a, REG> = crate::BitWriter<'a, REG, PRWARN_A>;
43impl<'a, REG> PRWARN_W<'a, REG>
44where
45    REG: crate::Writable + crate::RegisterSpec,
46{
47    #[doc = "Disabled"]
48    #[inline(always)]
49    pub fn const_0(self) -> &'a mut crate::W<REG> {
50        self.variant(PRWARN_A::CONST_0)
51    }
52    #[doc = "Enabled"]
53    #[inline(always)]
54    pub fn const_1(self) -> &'a mut crate::W<REG> {
55        self.variant(PRWARN_A::CONST_1)
56    }
57}
58#[doc = "RTC Periodic Interrupt Mask\n\nValue on reset: 0"]
59#[derive(Clone, Copy, Debug, PartialEq, Eq)]
60pub enum PI_A {
61    #[doc = "0: Disabled"]
62    CONST_0 = 0,
63    #[doc = "1: Enabled"]
64    CONST_1 = 1,
65}
66impl From<PI_A> for bool {
67    #[inline(always)]
68    fn from(variant: PI_A) -> Self {
69        variant as u8 != 0
70    }
71}
72#[doc = "Field `PI` reader - RTC Periodic Interrupt Mask"]
73pub type PI_R = crate::BitReader<PI_A>;
74impl PI_R {
75    #[doc = "Get enumerated values variant"]
76    #[inline(always)]
77    pub const fn variant(&self) -> PI_A {
78        match self.bits {
79            false => PI_A::CONST_0,
80            true => PI_A::CONST_1,
81        }
82    }
83    #[doc = "Disabled"]
84    #[inline(always)]
85    pub fn is_const_0(&self) -> bool {
86        *self == PI_A::CONST_0
87    }
88    #[doc = "Enabled"]
89    #[inline(always)]
90    pub fn is_const_1(&self) -> bool {
91        *self == PI_A::CONST_1
92    }
93}
94#[doc = "Field `PI` writer - RTC Periodic Interrupt Mask"]
95pub type PI_W<'a, REG> = crate::BitWriter<'a, REG, PI_A>;
96impl<'a, REG> PI_W<'a, REG>
97where
98    REG: crate::Writable + crate::RegisterSpec,
99{
100    #[doc = "Disabled"]
101    #[inline(always)]
102    pub fn const_0(self) -> &'a mut crate::W<REG> {
103        self.variant(PI_A::CONST_0)
104    }
105    #[doc = "Enabled"]
106    #[inline(always)]
107    pub fn const_1(self) -> &'a mut crate::W<REG> {
108        self.variant(PI_A::CONST_1)
109    }
110}
111#[doc = "RTC Alarm Interrupt Mask\n\nValue on reset: 0"]
112#[derive(Clone, Copy, Debug, PartialEq, Eq)]
113pub enum AI_A {
114    #[doc = "0: Disabled"]
115    CONST_0 = 0,
116    #[doc = "1: Enabled"]
117    CONST_1 = 1,
118}
119impl From<AI_A> for bool {
120    #[inline(always)]
121    fn from(variant: AI_A) -> Self {
122        variant as u8 != 0
123    }
124}
125#[doc = "Field `AI` reader - RTC Alarm Interrupt Mask"]
126pub type AI_R = crate::BitReader<AI_A>;
127impl AI_R {
128    #[doc = "Get enumerated values variant"]
129    #[inline(always)]
130    pub const fn variant(&self) -> AI_A {
131        match self.bits {
132            false => AI_A::CONST_0,
133            true => AI_A::CONST_1,
134        }
135    }
136    #[doc = "Disabled"]
137    #[inline(always)]
138    pub fn is_const_0(&self) -> bool {
139        *self == AI_A::CONST_0
140    }
141    #[doc = "Enabled"]
142    #[inline(always)]
143    pub fn is_const_1(&self) -> bool {
144        *self == AI_A::CONST_1
145    }
146}
147#[doc = "Field `AI` writer - RTC Alarm Interrupt Mask"]
148pub type AI_W<'a, REG> = crate::BitWriter<'a, REG, AI_A>;
149impl<'a, REG> AI_W<'a, REG>
150where
151    REG: crate::Writable + crate::RegisterSpec,
152{
153    #[doc = "Disabled"]
154    #[inline(always)]
155    pub fn const_0(self) -> &'a mut crate::W<REG> {
156        self.variant(AI_A::CONST_0)
157    }
158    #[doc = "Enabled"]
159    #[inline(always)]
160    pub fn const_1(self) -> &'a mut crate::W<REG> {
161        self.variant(AI_A::CONST_1)
162    }
163}
164#[doc = "DLR Request Overrun Interrupt Mask\n\nValue on reset: 0"]
165#[derive(Clone, Copy, Debug, PartialEq, Eq)]
166pub enum DLROVR_A {
167    #[doc = "0: Disabled"]
168    CONST_0 = 0,
169    #[doc = "1: Enabled"]
170    CONST_1 = 1,
171}
172impl From<DLROVR_A> for bool {
173    #[inline(always)]
174    fn from(variant: DLROVR_A) -> Self {
175        variant as u8 != 0
176    }
177}
178#[doc = "Field `DLROVR` reader - DLR Request Overrun Interrupt Mask"]
179pub type DLROVR_R = crate::BitReader<DLROVR_A>;
180impl DLROVR_R {
181    #[doc = "Get enumerated values variant"]
182    #[inline(always)]
183    pub const fn variant(&self) -> DLROVR_A {
184        match self.bits {
185            false => DLROVR_A::CONST_0,
186            true => DLROVR_A::CONST_1,
187        }
188    }
189    #[doc = "Disabled"]
190    #[inline(always)]
191    pub fn is_const_0(&self) -> bool {
192        *self == DLROVR_A::CONST_0
193    }
194    #[doc = "Enabled"]
195    #[inline(always)]
196    pub fn is_const_1(&self) -> bool {
197        *self == DLROVR_A::CONST_1
198    }
199}
200#[doc = "Field `DLROVR` writer - DLR Request Overrun Interrupt Mask"]
201pub type DLROVR_W<'a, REG> = crate::BitWriter<'a, REG, DLROVR_A>;
202impl<'a, REG> DLROVR_W<'a, REG>
203where
204    REG: crate::Writable + crate::RegisterSpec,
205{
206    #[doc = "Disabled"]
207    #[inline(always)]
208    pub fn const_0(self) -> &'a mut crate::W<REG> {
209        self.variant(DLROVR_A::CONST_0)
210    }
211    #[doc = "Enabled"]
212    #[inline(always)]
213    pub fn const_1(self) -> &'a mut crate::W<REG> {
214        self.variant(DLROVR_A::CONST_1)
215    }
216}
217#[doc = "HDCLR Mirror Register Update Mask\n\nValue on reset: 0"]
218#[derive(Clone, Copy, Debug, PartialEq, Eq)]
219pub enum HDCLR_A {
220    #[doc = "0: Disabled"]
221    CONST_0 = 0,
222    #[doc = "1: Enabled"]
223    CONST_1 = 1,
224}
225impl From<HDCLR_A> for bool {
226    #[inline(always)]
227    fn from(variant: HDCLR_A) -> Self {
228        variant as u8 != 0
229    }
230}
231#[doc = "Field `HDCLR` reader - HDCLR Mirror Register Update Mask"]
232pub type HDCLR_R = crate::BitReader<HDCLR_A>;
233impl HDCLR_R {
234    #[doc = "Get enumerated values variant"]
235    #[inline(always)]
236    pub const fn variant(&self) -> HDCLR_A {
237        match self.bits {
238            false => HDCLR_A::CONST_0,
239            true => HDCLR_A::CONST_1,
240        }
241    }
242    #[doc = "Disabled"]
243    #[inline(always)]
244    pub fn is_const_0(&self) -> bool {
245        *self == HDCLR_A::CONST_0
246    }
247    #[doc = "Enabled"]
248    #[inline(always)]
249    pub fn is_const_1(&self) -> bool {
250        *self == HDCLR_A::CONST_1
251    }
252}
253#[doc = "Field `HDCLR` writer - HDCLR Mirror Register Update Mask"]
254pub type HDCLR_W<'a, REG> = crate::BitWriter<'a, REG, HDCLR_A>;
255impl<'a, REG> HDCLR_W<'a, REG>
256where
257    REG: crate::Writable + crate::RegisterSpec,
258{
259    #[doc = "Disabled"]
260    #[inline(always)]
261    pub fn const_0(self) -> &'a mut crate::W<REG> {
262        self.variant(HDCLR_A::CONST_0)
263    }
264    #[doc = "Enabled"]
265    #[inline(always)]
266    pub fn const_1(self) -> &'a mut crate::W<REG> {
267        self.variant(HDCLR_A::CONST_1)
268    }
269}
270#[doc = "HDSET Mirror Register Update Mask\n\nValue on reset: 0"]
271#[derive(Clone, Copy, Debug, PartialEq, Eq)]
272pub enum HDSET_A {
273    #[doc = "0: Disabled"]
274    CONST_0 = 0,
275    #[doc = "1: Enabled"]
276    CONST_1 = 1,
277}
278impl From<HDSET_A> for bool {
279    #[inline(always)]
280    fn from(variant: HDSET_A) -> Self {
281        variant as u8 != 0
282    }
283}
284#[doc = "Field `HDSET` reader - HDSET Mirror Register Update Mask"]
285pub type HDSET_R = crate::BitReader<HDSET_A>;
286impl HDSET_R {
287    #[doc = "Get enumerated values variant"]
288    #[inline(always)]
289    pub const fn variant(&self) -> HDSET_A {
290        match self.bits {
291            false => HDSET_A::CONST_0,
292            true => HDSET_A::CONST_1,
293        }
294    }
295    #[doc = "Disabled"]
296    #[inline(always)]
297    pub fn is_const_0(&self) -> bool {
298        *self == HDSET_A::CONST_0
299    }
300    #[doc = "Enabled"]
301    #[inline(always)]
302    pub fn is_const_1(&self) -> bool {
303        *self == HDSET_A::CONST_1
304    }
305}
306#[doc = "Field `HDSET` writer - HDSET Mirror Register Update Mask"]
307pub type HDSET_W<'a, REG> = crate::BitWriter<'a, REG, HDSET_A>;
308impl<'a, REG> HDSET_W<'a, REG>
309where
310    REG: crate::Writable + crate::RegisterSpec,
311{
312    #[doc = "Disabled"]
313    #[inline(always)]
314    pub fn const_0(self) -> &'a mut crate::W<REG> {
315        self.variant(HDSET_A::CONST_0)
316    }
317    #[doc = "Enabled"]
318    #[inline(always)]
319    pub fn const_1(self) -> &'a mut crate::W<REG> {
320        self.variant(HDSET_A::CONST_1)
321    }
322}
323#[doc = "HDCR Mirror Register Update Mask\n\nValue on reset: 0"]
324#[derive(Clone, Copy, Debug, PartialEq, Eq)]
325pub enum HDCR_A {
326    #[doc = "0: Disabled"]
327    CONST_0 = 0,
328    #[doc = "1: Enabled"]
329    CONST_1 = 1,
330}
331impl From<HDCR_A> for bool {
332    #[inline(always)]
333    fn from(variant: HDCR_A) -> Self {
334        variant as u8 != 0
335    }
336}
337#[doc = "Field `HDCR` reader - HDCR Mirror Register Update Mask"]
338pub type HDCR_R = crate::BitReader<HDCR_A>;
339impl HDCR_R {
340    #[doc = "Get enumerated values variant"]
341    #[inline(always)]
342    pub const fn variant(&self) -> HDCR_A {
343        match self.bits {
344            false => HDCR_A::CONST_0,
345            true => HDCR_A::CONST_1,
346        }
347    }
348    #[doc = "Disabled"]
349    #[inline(always)]
350    pub fn is_const_0(&self) -> bool {
351        *self == HDCR_A::CONST_0
352    }
353    #[doc = "Enabled"]
354    #[inline(always)]
355    pub fn is_const_1(&self) -> bool {
356        *self == HDCR_A::CONST_1
357    }
358}
359#[doc = "Field `HDCR` writer - HDCR Mirror Register Update Mask"]
360pub type HDCR_W<'a, REG> = crate::BitWriter<'a, REG, HDCR_A>;
361impl<'a, REG> HDCR_W<'a, REG>
362where
363    REG: crate::Writable + crate::RegisterSpec,
364{
365    #[doc = "Disabled"]
366    #[inline(always)]
367    pub fn const_0(self) -> &'a mut crate::W<REG> {
368        self.variant(HDCR_A::CONST_0)
369    }
370    #[doc = "Enabled"]
371    #[inline(always)]
372    pub fn const_1(self) -> &'a mut crate::W<REG> {
373        self.variant(HDCR_A::CONST_1)
374    }
375}
376#[doc = "OSCSICTRL Mirror Register Update Mask\n\nValue on reset: 0"]
377#[derive(Clone, Copy, Debug, PartialEq, Eq)]
378pub enum OSCSICTRL_A {
379    #[doc = "0: Disabled"]
380    CONST_0 = 0,
381    #[doc = "1: Enabled"]
382    CONST_1 = 1,
383}
384impl From<OSCSICTRL_A> for bool {
385    #[inline(always)]
386    fn from(variant: OSCSICTRL_A) -> Self {
387        variant as u8 != 0
388    }
389}
390#[doc = "Field `OSCSICTRL` reader - OSCSICTRL Mirror Register Update Mask"]
391pub type OSCSICTRL_R = crate::BitReader<OSCSICTRL_A>;
392impl OSCSICTRL_R {
393    #[doc = "Get enumerated values variant"]
394    #[inline(always)]
395    pub const fn variant(&self) -> OSCSICTRL_A {
396        match self.bits {
397            false => OSCSICTRL_A::CONST_0,
398            true => OSCSICTRL_A::CONST_1,
399        }
400    }
401    #[doc = "Disabled"]
402    #[inline(always)]
403    pub fn is_const_0(&self) -> bool {
404        *self == OSCSICTRL_A::CONST_0
405    }
406    #[doc = "Enabled"]
407    #[inline(always)]
408    pub fn is_const_1(&self) -> bool {
409        *self == OSCSICTRL_A::CONST_1
410    }
411}
412#[doc = "Field `OSCSICTRL` writer - OSCSICTRL Mirror Register Update Mask"]
413pub type OSCSICTRL_W<'a, REG> = crate::BitWriter<'a, REG, OSCSICTRL_A>;
414impl<'a, REG> OSCSICTRL_W<'a, REG>
415where
416    REG: crate::Writable + crate::RegisterSpec,
417{
418    #[doc = "Disabled"]
419    #[inline(always)]
420    pub fn const_0(self) -> &'a mut crate::W<REG> {
421        self.variant(OSCSICTRL_A::CONST_0)
422    }
423    #[doc = "Enabled"]
424    #[inline(always)]
425    pub fn const_1(self) -> &'a mut crate::W<REG> {
426        self.variant(OSCSICTRL_A::CONST_1)
427    }
428}
429#[doc = "OSCULCTRL Mirror Register Update Mask\n\nValue on reset: 0"]
430#[derive(Clone, Copy, Debug, PartialEq, Eq)]
431pub enum OSCULCTRL_A {
432    #[doc = "0: Disabled"]
433    CONST_0 = 0,
434    #[doc = "1: Enabled"]
435    CONST_1 = 1,
436}
437impl From<OSCULCTRL_A> for bool {
438    #[inline(always)]
439    fn from(variant: OSCULCTRL_A) -> Self {
440        variant as u8 != 0
441    }
442}
443#[doc = "Field `OSCULCTRL` reader - OSCULCTRL Mirror Register Update Mask"]
444pub type OSCULCTRL_R = crate::BitReader<OSCULCTRL_A>;
445impl OSCULCTRL_R {
446    #[doc = "Get enumerated values variant"]
447    #[inline(always)]
448    pub const fn variant(&self) -> OSCULCTRL_A {
449        match self.bits {
450            false => OSCULCTRL_A::CONST_0,
451            true => OSCULCTRL_A::CONST_1,
452        }
453    }
454    #[doc = "Disabled"]
455    #[inline(always)]
456    pub fn is_const_0(&self) -> bool {
457        *self == OSCULCTRL_A::CONST_0
458    }
459    #[doc = "Enabled"]
460    #[inline(always)]
461    pub fn is_const_1(&self) -> bool {
462        *self == OSCULCTRL_A::CONST_1
463    }
464}
465#[doc = "Field `OSCULCTRL` writer - OSCULCTRL Mirror Register Update Mask"]
466pub type OSCULCTRL_W<'a, REG> = crate::BitWriter<'a, REG, OSCULCTRL_A>;
467impl<'a, REG> OSCULCTRL_W<'a, REG>
468where
469    REG: crate::Writable + crate::RegisterSpec,
470{
471    #[doc = "Disabled"]
472    #[inline(always)]
473    pub fn const_0(self) -> &'a mut crate::W<REG> {
474        self.variant(OSCULCTRL_A::CONST_0)
475    }
476    #[doc = "Enabled"]
477    #[inline(always)]
478    pub fn const_1(self) -> &'a mut crate::W<REG> {
479        self.variant(OSCULCTRL_A::CONST_1)
480    }
481}
482#[doc = "RTC CTR Mirror Register Update Mask\n\nValue on reset: 0"]
483#[derive(Clone, Copy, Debug, PartialEq, Eq)]
484pub enum RTC_CTR_A {
485    #[doc = "0: Disabled"]
486    CONST_0 = 0,
487    #[doc = "1: Enabled"]
488    CONST_1 = 1,
489}
490impl From<RTC_CTR_A> for bool {
491    #[inline(always)]
492    fn from(variant: RTC_CTR_A) -> Self {
493        variant as u8 != 0
494    }
495}
496#[doc = "Field `RTC_CTR` reader - RTC CTR Mirror Register Update Mask"]
497pub type RTC_CTR_R = crate::BitReader<RTC_CTR_A>;
498impl RTC_CTR_R {
499    #[doc = "Get enumerated values variant"]
500    #[inline(always)]
501    pub const fn variant(&self) -> RTC_CTR_A {
502        match self.bits {
503            false => RTC_CTR_A::CONST_0,
504            true => RTC_CTR_A::CONST_1,
505        }
506    }
507    #[doc = "Disabled"]
508    #[inline(always)]
509    pub fn is_const_0(&self) -> bool {
510        *self == RTC_CTR_A::CONST_0
511    }
512    #[doc = "Enabled"]
513    #[inline(always)]
514    pub fn is_const_1(&self) -> bool {
515        *self == RTC_CTR_A::CONST_1
516    }
517}
518#[doc = "Field `RTC_CTR` writer - RTC CTR Mirror Register Update Mask"]
519pub type RTC_CTR_W<'a, REG> = crate::BitWriter<'a, REG, RTC_CTR_A>;
520impl<'a, REG> RTC_CTR_W<'a, REG>
521where
522    REG: crate::Writable + crate::RegisterSpec,
523{
524    #[doc = "Disabled"]
525    #[inline(always)]
526    pub fn const_0(self) -> &'a mut crate::W<REG> {
527        self.variant(RTC_CTR_A::CONST_0)
528    }
529    #[doc = "Enabled"]
530    #[inline(always)]
531    pub fn const_1(self) -> &'a mut crate::W<REG> {
532        self.variant(RTC_CTR_A::CONST_1)
533    }
534}
535#[doc = "RTC ATIM0 Mirror Register Update Mask\n\nValue on reset: 0"]
536#[derive(Clone, Copy, Debug, PartialEq, Eq)]
537pub enum RTC_ATIM0_A {
538    #[doc = "0: Disabled"]
539    CONST_0 = 0,
540    #[doc = "1: Enabled"]
541    CONST_1 = 1,
542}
543impl From<RTC_ATIM0_A> for bool {
544    #[inline(always)]
545    fn from(variant: RTC_ATIM0_A) -> Self {
546        variant as u8 != 0
547    }
548}
549#[doc = "Field `RTC_ATIM0` reader - RTC ATIM0 Mirror Register Update Mask"]
550pub type RTC_ATIM0_R = crate::BitReader<RTC_ATIM0_A>;
551impl RTC_ATIM0_R {
552    #[doc = "Get enumerated values variant"]
553    #[inline(always)]
554    pub const fn variant(&self) -> RTC_ATIM0_A {
555        match self.bits {
556            false => RTC_ATIM0_A::CONST_0,
557            true => RTC_ATIM0_A::CONST_1,
558        }
559    }
560    #[doc = "Disabled"]
561    #[inline(always)]
562    pub fn is_const_0(&self) -> bool {
563        *self == RTC_ATIM0_A::CONST_0
564    }
565    #[doc = "Enabled"]
566    #[inline(always)]
567    pub fn is_const_1(&self) -> bool {
568        *self == RTC_ATIM0_A::CONST_1
569    }
570}
571#[doc = "Field `RTC_ATIM0` writer - RTC ATIM0 Mirror Register Update Mask"]
572pub type RTC_ATIM0_W<'a, REG> = crate::BitWriter<'a, REG, RTC_ATIM0_A>;
573impl<'a, REG> RTC_ATIM0_W<'a, REG>
574where
575    REG: crate::Writable + crate::RegisterSpec,
576{
577    #[doc = "Disabled"]
578    #[inline(always)]
579    pub fn const_0(self) -> &'a mut crate::W<REG> {
580        self.variant(RTC_ATIM0_A::CONST_0)
581    }
582    #[doc = "Enabled"]
583    #[inline(always)]
584    pub fn const_1(self) -> &'a mut crate::W<REG> {
585        self.variant(RTC_ATIM0_A::CONST_1)
586    }
587}
588#[doc = "RTC ATIM1 Mirror Register Update Mask\n\nValue on reset: 0"]
589#[derive(Clone, Copy, Debug, PartialEq, Eq)]
590pub enum RTC_ATIM1_A {
591    #[doc = "0: Disabled"]
592    CONST_0 = 0,
593    #[doc = "1: Enabled"]
594    CONST_1 = 1,
595}
596impl From<RTC_ATIM1_A> for bool {
597    #[inline(always)]
598    fn from(variant: RTC_ATIM1_A) -> Self {
599        variant as u8 != 0
600    }
601}
602#[doc = "Field `RTC_ATIM1` reader - RTC ATIM1 Mirror Register Update Mask"]
603pub type RTC_ATIM1_R = crate::BitReader<RTC_ATIM1_A>;
604impl RTC_ATIM1_R {
605    #[doc = "Get enumerated values variant"]
606    #[inline(always)]
607    pub const fn variant(&self) -> RTC_ATIM1_A {
608        match self.bits {
609            false => RTC_ATIM1_A::CONST_0,
610            true => RTC_ATIM1_A::CONST_1,
611        }
612    }
613    #[doc = "Disabled"]
614    #[inline(always)]
615    pub fn is_const_0(&self) -> bool {
616        *self == RTC_ATIM1_A::CONST_0
617    }
618    #[doc = "Enabled"]
619    #[inline(always)]
620    pub fn is_const_1(&self) -> bool {
621        *self == RTC_ATIM1_A::CONST_1
622    }
623}
624#[doc = "Field `RTC_ATIM1` writer - RTC ATIM1 Mirror Register Update Mask"]
625pub type RTC_ATIM1_W<'a, REG> = crate::BitWriter<'a, REG, RTC_ATIM1_A>;
626impl<'a, REG> RTC_ATIM1_W<'a, REG>
627where
628    REG: crate::Writable + crate::RegisterSpec,
629{
630    #[doc = "Disabled"]
631    #[inline(always)]
632    pub fn const_0(self) -> &'a mut crate::W<REG> {
633        self.variant(RTC_ATIM1_A::CONST_0)
634    }
635    #[doc = "Enabled"]
636    #[inline(always)]
637    pub fn const_1(self) -> &'a mut crate::W<REG> {
638        self.variant(RTC_ATIM1_A::CONST_1)
639    }
640}
641#[doc = "RTC TIM0 Mirror Register Update Mask\n\nValue on reset: 0"]
642#[derive(Clone, Copy, Debug, PartialEq, Eq)]
643pub enum RTC_TIM0_A {
644    #[doc = "0: Disabled"]
645    CONST_0 = 0,
646    #[doc = "1: Enabled"]
647    CONST_1 = 1,
648}
649impl From<RTC_TIM0_A> for bool {
650    #[inline(always)]
651    fn from(variant: RTC_TIM0_A) -> Self {
652        variant as u8 != 0
653    }
654}
655#[doc = "Field `RTC_TIM0` reader - RTC TIM0 Mirror Register Update Mask"]
656pub type RTC_TIM0_R = crate::BitReader<RTC_TIM0_A>;
657impl RTC_TIM0_R {
658    #[doc = "Get enumerated values variant"]
659    #[inline(always)]
660    pub const fn variant(&self) -> RTC_TIM0_A {
661        match self.bits {
662            false => RTC_TIM0_A::CONST_0,
663            true => RTC_TIM0_A::CONST_1,
664        }
665    }
666    #[doc = "Disabled"]
667    #[inline(always)]
668    pub fn is_const_0(&self) -> bool {
669        *self == RTC_TIM0_A::CONST_0
670    }
671    #[doc = "Enabled"]
672    #[inline(always)]
673    pub fn is_const_1(&self) -> bool {
674        *self == RTC_TIM0_A::CONST_1
675    }
676}
677#[doc = "Field `RTC_TIM0` writer - RTC TIM0 Mirror Register Update Mask"]
678pub type RTC_TIM0_W<'a, REG> = crate::BitWriter<'a, REG, RTC_TIM0_A>;
679impl<'a, REG> RTC_TIM0_W<'a, REG>
680where
681    REG: crate::Writable + crate::RegisterSpec,
682{
683    #[doc = "Disabled"]
684    #[inline(always)]
685    pub fn const_0(self) -> &'a mut crate::W<REG> {
686        self.variant(RTC_TIM0_A::CONST_0)
687    }
688    #[doc = "Enabled"]
689    #[inline(always)]
690    pub fn const_1(self) -> &'a mut crate::W<REG> {
691        self.variant(RTC_TIM0_A::CONST_1)
692    }
693}
694#[doc = "RTC TIM1 Mirror Register Update Mask\n\nValue on reset: 0"]
695#[derive(Clone, Copy, Debug, PartialEq, Eq)]
696pub enum RTC_TIM1_A {
697    #[doc = "0: Disabled"]
698    CONST_0 = 0,
699    #[doc = "1: Enabled"]
700    CONST_1 = 1,
701}
702impl From<RTC_TIM1_A> for bool {
703    #[inline(always)]
704    fn from(variant: RTC_TIM1_A) -> Self {
705        variant as u8 != 0
706    }
707}
708#[doc = "Field `RTC_TIM1` reader - RTC TIM1 Mirror Register Update Mask"]
709pub type RTC_TIM1_R = crate::BitReader<RTC_TIM1_A>;
710impl RTC_TIM1_R {
711    #[doc = "Get enumerated values variant"]
712    #[inline(always)]
713    pub const fn variant(&self) -> RTC_TIM1_A {
714        match self.bits {
715            false => RTC_TIM1_A::CONST_0,
716            true => RTC_TIM1_A::CONST_1,
717        }
718    }
719    #[doc = "Disabled"]
720    #[inline(always)]
721    pub fn is_const_0(&self) -> bool {
722        *self == RTC_TIM1_A::CONST_0
723    }
724    #[doc = "Enabled"]
725    #[inline(always)]
726    pub fn is_const_1(&self) -> bool {
727        *self == RTC_TIM1_A::CONST_1
728    }
729}
730#[doc = "Field `RTC_TIM1` writer - RTC TIM1 Mirror Register Update Mask"]
731pub type RTC_TIM1_W<'a, REG> = crate::BitWriter<'a, REG, RTC_TIM1_A>;
732impl<'a, REG> RTC_TIM1_W<'a, REG>
733where
734    REG: crate::Writable + crate::RegisterSpec,
735{
736    #[doc = "Disabled"]
737    #[inline(always)]
738    pub fn const_0(self) -> &'a mut crate::W<REG> {
739        self.variant(RTC_TIM1_A::CONST_0)
740    }
741    #[doc = "Enabled"]
742    #[inline(always)]
743    pub fn const_1(self) -> &'a mut crate::W<REG> {
744        self.variant(RTC_TIM1_A::CONST_1)
745    }
746}
747#[doc = "Retention Memory Mirror Register Update Mask\n\nValue on reset: 0"]
748#[derive(Clone, Copy, Debug, PartialEq, Eq)]
749pub enum RMX_A {
750    #[doc = "0: Disabled"]
751    CONST_0 = 0,
752    #[doc = "1: Enabled"]
753    CONST_1 = 1,
754}
755impl From<RMX_A> for bool {
756    #[inline(always)]
757    fn from(variant: RMX_A) -> Self {
758        variant as u8 != 0
759    }
760}
761#[doc = "Field `RMX` reader - Retention Memory Mirror Register Update Mask"]
762pub type RMX_R = crate::BitReader<RMX_A>;
763impl RMX_R {
764    #[doc = "Get enumerated values variant"]
765    #[inline(always)]
766    pub const fn variant(&self) -> RMX_A {
767        match self.bits {
768            false => RMX_A::CONST_0,
769            true => RMX_A::CONST_1,
770        }
771    }
772    #[doc = "Disabled"]
773    #[inline(always)]
774    pub fn is_const_0(&self) -> bool {
775        *self == RMX_A::CONST_0
776    }
777    #[doc = "Enabled"]
778    #[inline(always)]
779    pub fn is_const_1(&self) -> bool {
780        *self == RMX_A::CONST_1
781    }
782}
783#[doc = "Field `RMX` writer - Retention Memory Mirror Register Update Mask"]
784pub type RMX_W<'a, REG> = crate::BitWriter<'a, REG, RMX_A>;
785impl<'a, REG> RMX_W<'a, REG>
786where
787    REG: crate::Writable + crate::RegisterSpec,
788{
789    #[doc = "Disabled"]
790    #[inline(always)]
791    pub fn const_0(self) -> &'a mut crate::W<REG> {
792        self.variant(RMX_A::CONST_0)
793    }
794    #[doc = "Enabled"]
795    #[inline(always)]
796    pub fn const_1(self) -> &'a mut crate::W<REG> {
797        self.variant(RMX_A::CONST_1)
798    }
799}
800impl R {
801    #[doc = "Bit 0 - WDT pre-warning Interrupt Mask"]
802    #[inline(always)]
803    pub fn prwarn(&self) -> PRWARN_R {
804        PRWARN_R::new((self.bits & 1) != 0)
805    }
806    #[doc = "Bit 1 - RTC Periodic Interrupt Mask"]
807    #[inline(always)]
808    pub fn pi(&self) -> PI_R {
809        PI_R::new(((self.bits >> 1) & 1) != 0)
810    }
811    #[doc = "Bit 2 - RTC Alarm Interrupt Mask"]
812    #[inline(always)]
813    pub fn ai(&self) -> AI_R {
814        AI_R::new(((self.bits >> 2) & 1) != 0)
815    }
816    #[doc = "Bit 3 - DLR Request Overrun Interrupt Mask"]
817    #[inline(always)]
818    pub fn dlrovr(&self) -> DLROVR_R {
819        DLROVR_R::new(((self.bits >> 3) & 1) != 0)
820    }
821    #[doc = "Bit 17 - HDCLR Mirror Register Update Mask"]
822    #[inline(always)]
823    pub fn hdclr(&self) -> HDCLR_R {
824        HDCLR_R::new(((self.bits >> 17) & 1) != 0)
825    }
826    #[doc = "Bit 18 - HDSET Mirror Register Update Mask"]
827    #[inline(always)]
828    pub fn hdset(&self) -> HDSET_R {
829        HDSET_R::new(((self.bits >> 18) & 1) != 0)
830    }
831    #[doc = "Bit 19 - HDCR Mirror Register Update Mask"]
832    #[inline(always)]
833    pub fn hdcr(&self) -> HDCR_R {
834        HDCR_R::new(((self.bits >> 19) & 1) != 0)
835    }
836    #[doc = "Bit 21 - OSCSICTRL Mirror Register Update Mask"]
837    #[inline(always)]
838    pub fn oscsictrl(&self) -> OSCSICTRL_R {
839        OSCSICTRL_R::new(((self.bits >> 21) & 1) != 0)
840    }
841    #[doc = "Bit 23 - OSCULCTRL Mirror Register Update Mask"]
842    #[inline(always)]
843    pub fn osculctrl(&self) -> OSCULCTRL_R {
844        OSCULCTRL_R::new(((self.bits >> 23) & 1) != 0)
845    }
846    #[doc = "Bit 24 - RTC CTR Mirror Register Update Mask"]
847    #[inline(always)]
848    pub fn rtc_ctr(&self) -> RTC_CTR_R {
849        RTC_CTR_R::new(((self.bits >> 24) & 1) != 0)
850    }
851    #[doc = "Bit 25 - RTC ATIM0 Mirror Register Update Mask"]
852    #[inline(always)]
853    pub fn rtc_atim0(&self) -> RTC_ATIM0_R {
854        RTC_ATIM0_R::new(((self.bits >> 25) & 1) != 0)
855    }
856    #[doc = "Bit 26 - RTC ATIM1 Mirror Register Update Mask"]
857    #[inline(always)]
858    pub fn rtc_atim1(&self) -> RTC_ATIM1_R {
859        RTC_ATIM1_R::new(((self.bits >> 26) & 1) != 0)
860    }
861    #[doc = "Bit 27 - RTC TIM0 Mirror Register Update Mask"]
862    #[inline(always)]
863    pub fn rtc_tim0(&self) -> RTC_TIM0_R {
864        RTC_TIM0_R::new(((self.bits >> 27) & 1) != 0)
865    }
866    #[doc = "Bit 28 - RTC TIM1 Mirror Register Update Mask"]
867    #[inline(always)]
868    pub fn rtc_tim1(&self) -> RTC_TIM1_R {
869        RTC_TIM1_R::new(((self.bits >> 28) & 1) != 0)
870    }
871    #[doc = "Bit 29 - Retention Memory Mirror Register Update Mask"]
872    #[inline(always)]
873    pub fn rmx(&self) -> RMX_R {
874        RMX_R::new(((self.bits >> 29) & 1) != 0)
875    }
876}
877impl W {
878    #[doc = "Bit 0 - WDT pre-warning Interrupt Mask"]
879    #[inline(always)]
880    pub fn prwarn(&mut self) -> PRWARN_W<SRMSK_SPEC> {
881        PRWARN_W::new(self, 0)
882    }
883    #[doc = "Bit 1 - RTC Periodic Interrupt Mask"]
884    #[inline(always)]
885    pub fn pi(&mut self) -> PI_W<SRMSK_SPEC> {
886        PI_W::new(self, 1)
887    }
888    #[doc = "Bit 2 - RTC Alarm Interrupt Mask"]
889    #[inline(always)]
890    pub fn ai(&mut self) -> AI_W<SRMSK_SPEC> {
891        AI_W::new(self, 2)
892    }
893    #[doc = "Bit 3 - DLR Request Overrun Interrupt Mask"]
894    #[inline(always)]
895    pub fn dlrovr(&mut self) -> DLROVR_W<SRMSK_SPEC> {
896        DLROVR_W::new(self, 3)
897    }
898    #[doc = "Bit 17 - HDCLR Mirror Register Update Mask"]
899    #[inline(always)]
900    pub fn hdclr(&mut self) -> HDCLR_W<SRMSK_SPEC> {
901        HDCLR_W::new(self, 17)
902    }
903    #[doc = "Bit 18 - HDSET Mirror Register Update Mask"]
904    #[inline(always)]
905    pub fn hdset(&mut self) -> HDSET_W<SRMSK_SPEC> {
906        HDSET_W::new(self, 18)
907    }
908    #[doc = "Bit 19 - HDCR Mirror Register Update Mask"]
909    #[inline(always)]
910    pub fn hdcr(&mut self) -> HDCR_W<SRMSK_SPEC> {
911        HDCR_W::new(self, 19)
912    }
913    #[doc = "Bit 21 - OSCSICTRL Mirror Register Update Mask"]
914    #[inline(always)]
915    pub fn oscsictrl(&mut self) -> OSCSICTRL_W<SRMSK_SPEC> {
916        OSCSICTRL_W::new(self, 21)
917    }
918    #[doc = "Bit 23 - OSCULCTRL Mirror Register Update Mask"]
919    #[inline(always)]
920    pub fn osculctrl(&mut self) -> OSCULCTRL_W<SRMSK_SPEC> {
921        OSCULCTRL_W::new(self, 23)
922    }
923    #[doc = "Bit 24 - RTC CTR Mirror Register Update Mask"]
924    #[inline(always)]
925    pub fn rtc_ctr(&mut self) -> RTC_CTR_W<SRMSK_SPEC> {
926        RTC_CTR_W::new(self, 24)
927    }
928    #[doc = "Bit 25 - RTC ATIM0 Mirror Register Update Mask"]
929    #[inline(always)]
930    pub fn rtc_atim0(&mut self) -> RTC_ATIM0_W<SRMSK_SPEC> {
931        RTC_ATIM0_W::new(self, 25)
932    }
933    #[doc = "Bit 26 - RTC ATIM1 Mirror Register Update Mask"]
934    #[inline(always)]
935    pub fn rtc_atim1(&mut self) -> RTC_ATIM1_W<SRMSK_SPEC> {
936        RTC_ATIM1_W::new(self, 26)
937    }
938    #[doc = "Bit 27 - RTC TIM0 Mirror Register Update Mask"]
939    #[inline(always)]
940    pub fn rtc_tim0(&mut self) -> RTC_TIM0_W<SRMSK_SPEC> {
941        RTC_TIM0_W::new(self, 27)
942    }
943    #[doc = "Bit 28 - RTC TIM1 Mirror Register Update Mask"]
944    #[inline(always)]
945    pub fn rtc_tim1(&mut self) -> RTC_TIM1_W<SRMSK_SPEC> {
946        RTC_TIM1_W::new(self, 28)
947    }
948    #[doc = "Bit 29 - Retention Memory Mirror Register Update Mask"]
949    #[inline(always)]
950    pub fn rmx(&mut self) -> RMX_W<SRMSK_SPEC> {
951        RMX_W::new(self, 29)
952    }
953}
954#[doc = "SCU Service Request Mask\n\nYou can [`read`](crate::Reg::read) this register and get [`srmsk::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`srmsk::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
955pub struct SRMSK_SPEC;
956impl crate::RegisterSpec for SRMSK_SPEC {
957    type Ux = u32;
958}
959#[doc = "`read()` method returns [`srmsk::R`](R) reader structure"]
960impl crate::Readable for SRMSK_SPEC {}
961#[doc = "`write(|w| ..)` method takes [`srmsk::W`](W) writer structure"]
962impl crate::Writable for SRMSK_SPEC {
963    type Safety = crate::Unsafe;
964    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
965    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
966}
967#[doc = "`reset()` method sets SRMSK to value 0"]
968impl crate::Resettable for SRMSK_SPEC {
969    const RESET_VALUE: u32 = 0;
970}
xmc4300/scu_interrupt/srmsk.rs

xmc4300/scu_interrupt/
srmsk.rs
