Struct xmc4200::scu_clk::RegisterBlock
[−]
[src]
#[repr(C)]pub struct RegisterBlock { pub clkstat: CLKSTAT, pub clkset: CLKSET, pub clkclr: CLKCLR, pub sysclkcr: SYSCLKCR, pub cpuclkcr: CPUCLKCR, pub pbclkcr: PBCLKCR, pub usbclkcr: USBCLKCR, pub ccuclkcr: CCUCLKCR, pub wdtclkcr: WDTCLKCR, pub extclkcr: EXTCLKCR, pub mlinkclkcr: MLINKCLKCR, pub sleepcr: SLEEPCR, pub dsleepcr: DSLEEPCR, pub cgatstat0: CGATSTAT0, pub cgatset0: CGATSET0, pub cgatclr0: CGATCLR0, pub cgatstat1: CGATSTAT1, pub cgatset1: CGATSET1, pub cgatclr1: CGATCLR1, pub cgatstat2: CGATSTAT2, pub cgatset2: CGATSET2, pub cgatclr2: CGATCLR2, // some fields omitted }
Register block
Fields
clkstat: CLKSTAT
0x00 - Clock Status Register
clkset: CLKSET
0x04 - CLK Set Register
clkclr: CLKCLR
0x08 - CLK Clear Register
sysclkcr: SYSCLKCR
0x0c - System Clock Control Register
cpuclkcr: CPUCLKCR
0x10 - CPU Clock Control Register
pbclkcr: PBCLKCR
0x14 - Peripheral Bus Clock Control Register
usbclkcr: USBCLKCR
0x18 - USB Clock Control Register
ccuclkcr: CCUCLKCR
0x20 - CCU Clock Control Register
wdtclkcr: WDTCLKCR
0x24 - WDT Clock Control Register
extclkcr: EXTCLKCR
0x28 - External Clock Control
mlinkclkcr: MLINKCLKCR
0x2c - Multi-Link Clock Control
sleepcr: SLEEPCR
0x30 - Sleep Control Register
dsleepcr: DSLEEPCR
0x34 - Deep Sleep Control Register
cgatstat0: CGATSTAT0
0x40 - Peripheral 0 Clock Gating Status
cgatset0: CGATSET0
0x44 - Peripheral 0 Clock Gating Set
cgatclr0: CGATCLR0
0x48 - Peripheral 0 Clock Gating Clear
cgatstat1: CGATSTAT1
0x4c - Peripheral 1 Clock Gating Status
cgatset1: CGATSET1
0x50 - Peripheral 1 Clock Gating Set
cgatclr1: CGATCLR1
0x54 - Peripheral 1 Clock Gating Clear
cgatstat2: CGATSTAT2
0x58 - Peripheral 2 Clock Gating Status
cgatset2: CGATSET2
0x5c - Peripheral 2 Clock Gating Set
cgatclr2: CGATCLR2
0x60 - Peripheral 2 Clock Gating Clear