Module xmc4200::scu_clk
[−]
[src]
System Control Unit
Modules
ccuclkcr |
CCU Clock Control Register |
cgatclr0 |
Peripheral 0 Clock Gating Clear |
cgatclr1 |
Peripheral 1 Clock Gating Clear |
cgatclr2 |
Peripheral 2 Clock Gating Clear |
cgatset0 |
Peripheral 0 Clock Gating Set |
cgatset1 |
Peripheral 1 Clock Gating Set |
cgatset2 |
Peripheral 2 Clock Gating Set |
cgatstat0 |
Peripheral 0 Clock Gating Status |
cgatstat1 |
Peripheral 1 Clock Gating Status |
cgatstat2 |
Peripheral 2 Clock Gating Status |
clkclr |
CLK Clear Register |
clkset |
CLK Set Register |
clkstat |
Clock Status Register |
cpuclkcr |
CPU Clock Control Register |
dsleepcr |
Deep Sleep Control Register |
extclkcr |
External Clock Control |
mlinkclkcr |
Multi-Link Clock Control |
pbclkcr |
Peripheral Bus Clock Control Register |
sleepcr |
Sleep Control Register |
sysclkcr |
System Clock Control Register |
usbclkcr |
USB Clock Control Register |
wdtclkcr |
WDT Clock Control Register |
Structs
CCUCLKCR |
CCU Clock Control Register |
CGATCLR0 |
Peripheral 0 Clock Gating Clear |
CGATCLR1 |
Peripheral 1 Clock Gating Clear |
CGATCLR2 |
Peripheral 2 Clock Gating Clear |
CGATSET0 |
Peripheral 0 Clock Gating Set |
CGATSET1 |
Peripheral 1 Clock Gating Set |
CGATSET2 |
Peripheral 2 Clock Gating Set |
CGATSTAT0 |
Peripheral 0 Clock Gating Status |
CGATSTAT1 |
Peripheral 1 Clock Gating Status |
CGATSTAT2 |
Peripheral 2 Clock Gating Status |
CLKCLR |
CLK Clear Register |
CLKSET |
CLK Set Register |
CLKSTAT |
Clock Status Register |
CPUCLKCR |
CPU Clock Control Register |
DSLEEPCR |
Deep Sleep Control Register |
EXTCLKCR |
External Clock Control |
MLINKCLKCR |
Multi-Link Clock Control |
PBCLKCR |
Peripheral Bus Clock Control Register |
RegisterBlock |
Register block |
SLEEPCR |
Sleep Control Register |
SYSCLKCR |
System Clock Control Register |
USBCLKCR |
USB Clock Control Register |
WDTCLKCR |
WDT Clock Control Register |