Struct xmc4100::generic::W

pub struct W<U, REG> { /* fields omitted */ }

Register writer

Used as an argument to the closures in the write and modify methods of the register

Implementations

impl<U, REG> W<U, REG>

pub unsafe fn bits(&mut self, bits: U) -> &mut Self

Writes raw bits to the register

impl W<u32, Reg<u32, _ACTLR>>

pub fn dismcycint(&mut self) -> DISMCYCINT_W<'_>

Bit 0 - Disable load/store multiple

pub fn disdefwbuf(&mut self) -> DISDEFWBUF_W<'_>

Bit 1 - Disable write buffer

pub fn disfold(&mut self) -> DISFOLD_W<'_>

Bit 2 - Disable IT folding

pub fn disfpca(&mut self) -> DISFPCA_W<'_>

Bit 8 - Disable FPCA update

pub fn disoofp(&mut self) -> DISOOFP_W<'_>

Bit 9 - Disable out of order FP execution

impl W<u32, Reg<u32, _SYST_CSR>>

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 0 - Enable

pub fn tickint(&mut self) -> TICKINT_W<'_>

Bit 1 - Tick Interrupt Enable

pub fn clksource(&mut self) -> CLKSOURCE_W<'_>

Bit 2 - Indicates the clock source:

pub fn countflag(&mut self) -> COUNTFLAG_W<'_>

Bit 16 - Counter Flag

impl W<u32, Reg<u32, _SYST_RVR>>

pub fn reload(&mut self) -> RELOAD_W<'_>

Bits 0:23 - Reload Value

impl W<u32, Reg<u32, _SYST_CVR>>

pub fn current(&mut self) -> CURRENT_W<'_>

Bits 0:23 - Current Value

impl W<u32, Reg<u32, _SYST_CALIB>>

pub fn tenms(&mut self) -> TENMS_W<'_>

Bits 0:23 - Ten Milliseconds Reload Value

pub fn skew(&mut self) -> SKEW_W<'_>

Bit 30 - Ten Milliseconds Skewed

pub fn noref(&mut self) -> NOREF_W<'_>

Bit 31 - No Reference Clock

impl W<u32, Reg<u32, _NVIC_ISER0>>

pub fn setena(&mut self) -> SETENA_W<'_>

Bits 0:31 - Interrupt set-enable bits

impl W<u32, Reg<u32, _NVIC_ISER1>>

pub fn setena(&mut self) -> SETENA_W<'_>

Bits 0:31 - Interrupt set-enable bits

impl W<u32, Reg<u32, _NVIC_ISER2>>

pub fn setena(&mut self) -> SETENA_W<'_>

Bits 0:31 - Interrupt set-enable bits

impl W<u32, Reg<u32, _NVIC_ISER3>>

pub fn setena(&mut self) -> SETENA_W<'_>

Bits 0:31 - Interrupt set-enable bits

impl W<u32, Reg<u32, _NVIC_ICER0>>

pub fn clrena(&mut self) -> CLRENA_W<'_>

Bits 0:31 - Interrupt clear-enable bits.

impl W<u32, Reg<u32, _NVIC_ICER1>>

pub fn clrena(&mut self) -> CLRENA_W<'_>

Bits 0:31 - Interrupt clear-enable bits.

impl W<u32, Reg<u32, _NVIC_ICER2>>

pub fn clrena(&mut self) -> CLRENA_W<'_>

Bits 0:31 - Interrupt clear-enable bits.

impl W<u32, Reg<u32, _NVIC_ICER3>>

pub fn clrena(&mut self) -> CLRENA_W<'_>

Bits 0:31 - Interrupt clear-enable bits.

impl W<u32, Reg<u32, _NVIC_ISPR0>>

pub fn setpend(&mut self) -> SETPEND_W<'_>

Bits 0:31 - Interrupt set-pending bits.

impl W<u32, Reg<u32, _NVIC_ISPR1>>

pub fn setpend(&mut self) -> SETPEND_W<'_>

Bits 0:31 - Interrupt set-pending bits.

impl W<u32, Reg<u32, _NVIC_ISPR2>>

pub fn setpend(&mut self) -> SETPEND_W<'_>

Bits 0:31 - Interrupt set-pending bits.

impl W<u32, Reg<u32, _NVIC_ISPR3>>

pub fn setpend(&mut self) -> SETPEND_W<'_>

Bits 0:31 - Interrupt set-pending bits.

impl W<u32, Reg<u32, _NVIC_ICPR0>>

pub fn clrpend(&mut self) -> CLRPEND_W<'_>

Bits 0:31 - Interrupt set-pending bits.

impl W<u32, Reg<u32, _NVIC_ICPR1>>

pub fn clrpend(&mut self) -> CLRPEND_W<'_>

Bits 0:31 - Interrupt set-pending bits.

impl W<u32, Reg<u32, _NVIC_ICPR2>>

pub fn clrpend(&mut self) -> CLRPEND_W<'_>

Bits 0:31 - Interrupt set-pending bits.

impl W<u32, Reg<u32, _NVIC_ICPR3>>

pub fn clrpend(&mut self) -> CLRPEND_W<'_>

Bits 0:31 - Interrupt set-pending bits.

impl W<u32, Reg<u32, _NVIC_IABR0>>

pub fn active(&mut self) -> ACTIVE_W<'_>

Bits 0:31 - Interrupt active flags:

impl W<u32, Reg<u32, _NVIC_IABR1>>

pub fn active(&mut self) -> ACTIVE_W<'_>

Bits 0:31 - Interrupt active flags:

impl W<u32, Reg<u32, _NVIC_IABR2>>

pub fn active(&mut self) -> ACTIVE_W<'_>

Bits 0:31 - Interrupt active flags:

impl W<u32, Reg<u32, _NVIC_IABR3>>

pub fn active(&mut self) -> ACTIVE_W<'_>

Bits 0:31 - Interrupt active flags:

impl W<u32, Reg<u32, _NVIC_IPR0>>

pub fn pri_0(&mut self) -> PRI_0_W<'_>

Bits 0:7 - Priority value 0

pub fn pri_1(&mut self) -> PRI_1_W<'_>

Bits 8:15 - Priority value 1

pub fn pri_2(&mut self) -> PRI_2_W<'_>

Bits 16:23 - Priority value 2

pub fn pri_3(&mut self) -> PRI_3_W<'_>

Bits 24:31 - Priority value 3

impl W<u32, Reg<u32, _NVIC_IPR1>>

pub fn pri_0(&mut self) -> PRI_0_W<'_>

Bits 0:7 - Priority value 0

pub fn pri_1(&mut self) -> PRI_1_W<'_>

Bits 8:15 - Priority value 1

pub fn pri_2(&mut self) -> PRI_2_W<'_>

Bits 16:23 - Priority value 2

pub fn pri_3(&mut self) -> PRI_3_W<'_>

Bits 24:31 - Priority value 3

impl W<u32, Reg<u32, _NVIC_IPR2>>

pub fn pri_0(&mut self) -> PRI_0_W<'_>

Bits 0:7 - Priority value 0

pub fn pri_1(&mut self) -> PRI_1_W<'_>

Bits 8:15 - Priority value 1

pub fn pri_2(&mut self) -> PRI_2_W<'_>

Bits 16:23 - Priority value 2

pub fn pri_3(&mut self) -> PRI_3_W<'_>

Bits 24:31 - Priority value 3

impl W<u32, Reg<u32, _NVIC_IPR3>>

pub fn pri_0(&mut self) -> PRI_0_W<'_>

Bits 0:7 - Priority value 0

pub fn pri_1(&mut self) -> PRI_1_W<'_>

Bits 8:15 - Priority value 1

pub fn pri_2(&mut self) -> PRI_2_W<'_>

Bits 16:23 - Priority value 2

pub fn pri_3(&mut self) -> PRI_3_W<'_>

Bits 24:31 - Priority value 3

impl W<u32, Reg<u32, _NVIC_IPR4>>

pub fn pri_0(&mut self) -> PRI_0_W<'_>

Bits 0:7 - Priority value 0

pub fn pri_1(&mut self) -> PRI_1_W<'_>

Bits 8:15 - Priority value 1

pub fn pri_2(&mut self) -> PRI_2_W<'_>

Bits 16:23 - Priority value 2

pub fn pri_3(&mut self) -> PRI_3_W<'_>

Bits 24:31 - Priority value 3

impl W<u32, Reg<u32, _NVIC_IPR5>>

pub fn pri_0(&mut self) -> PRI_0_W<'_>

Bits 0:7 - Priority value 0

pub fn pri_1(&mut self) -> PRI_1_W<'_>

Bits 8:15 - Priority value 1

pub fn pri_2(&mut self) -> PRI_2_W<'_>

Bits 16:23 - Priority value 2

pub fn pri_3(&mut self) -> PRI_3_W<'_>

Bits 24:31 - Priority value 3

impl W<u32, Reg<u32, _NVIC_IPR6>>

pub fn pri_0(&mut self) -> PRI_0_W<'_>

Bits 0:7 - Priority value 0

pub fn pri_1(&mut self) -> PRI_1_W<'_>

Bits 8:15 - Priority value 1

pub fn pri_2(&mut self) -> PRI_2_W<'_>

Bits 16:23 - Priority value 2

pub fn pri_3(&mut self) -> PRI_3_W<'_>

Bits 24:31 - Priority value 3

impl W<u32, Reg<u32, _NVIC_IPR7>>

pub fn pri_0(&mut self) -> PRI_0_W<'_>

Bits 0:7 - Priority value 0

pub fn pri_1(&mut self) -> PRI_1_W<'_>

Bits 8:15 - Priority value 1

pub fn pri_2(&mut self) -> PRI_2_W<'_>

Bits 16:23 - Priority value 2

pub fn pri_3(&mut self) -> PRI_3_W<'_>

Bits 24:31 - Priority value 3

impl W<u32, Reg<u32, _NVIC_IPR8>>

pub fn pri_0(&mut self) -> PRI_0_W<'_>

Bits 0:7 - Priority value 0

pub fn pri_1(&mut self) -> PRI_1_W<'_>

Bits 8:15 - Priority value 1

pub fn pri_2(&mut self) -> PRI_2_W<'_>

Bits 16:23 - Priority value 2

pub fn pri_3(&mut self) -> PRI_3_W<'_>

Bits 24:31 - Priority value 3

impl W<u32, Reg<u32, _NVIC_IPR9>>

pub fn pri_0(&mut self) -> PRI_0_W<'_>

Bits 0:7 - Priority value 0

pub fn pri_1(&mut self) -> PRI_1_W<'_>

Bits 8:15 - Priority value 1

pub fn pri_2(&mut self) -> PRI_2_W<'_>

Bits 16:23 - Priority value 2

pub fn pri_3(&mut self) -> PRI_3_W<'_>

Bits 24:31 - Priority value 3

impl W<u32, Reg<u32, _NVIC_IPR10>>

pub fn pri_0(&mut self) -> PRI_0_W<'_>

Bits 0:7 - Priority value 0

pub fn pri_1(&mut self) -> PRI_1_W<'_>

Bits 8:15 - Priority value 1

pub fn pri_2(&mut self) -> PRI_2_W<'_>

Bits 16:23 - Priority value 2

pub fn pri_3(&mut self) -> PRI_3_W<'_>

Bits 24:31 - Priority value 3

impl W<u32, Reg<u32, _NVIC_IPR11>>

pub fn pri_0(&mut self) -> PRI_0_W<'_>

Bits 0:7 - Priority value 0

pub fn pri_1(&mut self) -> PRI_1_W<'_>

Bits 8:15 - Priority value 1

pub fn pri_2(&mut self) -> PRI_2_W<'_>

Bits 16:23 - Priority value 2

pub fn pri_3(&mut self) -> PRI_3_W<'_>

Bits 24:31 - Priority value 3

impl W<u32, Reg<u32, _NVIC_IPR12>>

pub fn pri_0(&mut self) -> PRI_0_W<'_>

Bits 0:7 - Priority value 0

pub fn pri_1(&mut self) -> PRI_1_W<'_>

Bits 8:15 - Priority value 1

pub fn pri_2(&mut self) -> PRI_2_W<'_>

Bits 16:23 - Priority value 2

pub fn pri_3(&mut self) -> PRI_3_W<'_>

Bits 24:31 - Priority value 3

impl W<u32, Reg<u32, _NVIC_IPR13>>

pub fn pri_0(&mut self) -> PRI_0_W<'_>

Bits 0:7 - Priority value 0

pub fn pri_1(&mut self) -> PRI_1_W<'_>

Bits 8:15 - Priority value 1

pub fn pri_2(&mut self) -> PRI_2_W<'_>

Bits 16:23 - Priority value 2

pub fn pri_3(&mut self) -> PRI_3_W<'_>

Bits 24:31 - Priority value 3

impl W<u32, Reg<u32, _NVIC_IPR14>>

pub fn pri_0(&mut self) -> PRI_0_W<'_>

Bits 0:7 - Priority value 0

pub fn pri_1(&mut self) -> PRI_1_W<'_>

Bits 8:15 - Priority value 1

pub fn pri_2(&mut self) -> PRI_2_W<'_>

Bits 16:23 - Priority value 2

pub fn pri_3(&mut self) -> PRI_3_W<'_>

Bits 24:31 - Priority value 3

impl W<u32, Reg<u32, _NVIC_IPR15>>

pub fn pri_0(&mut self) -> PRI_0_W<'_>

Bits 0:7 - Priority value 0

pub fn pri_1(&mut self) -> PRI_1_W<'_>

Bits 8:15 - Priority value 1

pub fn pri_2(&mut self) -> PRI_2_W<'_>

Bits 16:23 - Priority value 2

pub fn pri_3(&mut self) -> PRI_3_W<'_>

Bits 24:31 - Priority value 3

impl W<u32, Reg<u32, _NVIC_IPR16>>

pub fn pri_0(&mut self) -> PRI_0_W<'_>

Bits 0:7 - Priority value 0

pub fn pri_1(&mut self) -> PRI_1_W<'_>

Bits 8:15 - Priority value 1

pub fn pri_2(&mut self) -> PRI_2_W<'_>

Bits 16:23 - Priority value 2

pub fn pri_3(&mut self) -> PRI_3_W<'_>

Bits 24:31 - Priority value 3

impl W<u32, Reg<u32, _NVIC_IPR17>>

pub fn pri_0(&mut self) -> PRI_0_W<'_>

Bits 0:7 - Priority value 0

pub fn pri_1(&mut self) -> PRI_1_W<'_>

Bits 8:15 - Priority value 1

pub fn pri_2(&mut self) -> PRI_2_W<'_>

Bits 16:23 - Priority value 2

pub fn pri_3(&mut self) -> PRI_3_W<'_>

Bits 24:31 - Priority value 3

impl W<u32, Reg<u32, _NVIC_IPR18>>

pub fn pri_0(&mut self) -> PRI_0_W<'_>

Bits 0:7 - Priority value 0

pub fn pri_1(&mut self) -> PRI_1_W<'_>

Bits 8:15 - Priority value 1

pub fn pri_2(&mut self) -> PRI_2_W<'_>

Bits 16:23 - Priority value 2

pub fn pri_3(&mut self) -> PRI_3_W<'_>

Bits 24:31 - Priority value 3

impl W<u32, Reg<u32, _NVIC_IPR19>>

pub fn pri_0(&mut self) -> PRI_0_W<'_>

Bits 0:7 - Priority value 0

pub fn pri_1(&mut self) -> PRI_1_W<'_>

Bits 8:15 - Priority value 1

pub fn pri_2(&mut self) -> PRI_2_W<'_>

Bits 16:23 - Priority value 2

pub fn pri_3(&mut self) -> PRI_3_W<'_>

Bits 24:31 - Priority value 3

impl W<u32, Reg<u32, _NVIC_IPR20>>

pub fn pri_0(&mut self) -> PRI_0_W<'_>

Bits 0:7 - Priority value 0

pub fn pri_1(&mut self) -> PRI_1_W<'_>

Bits 8:15 - Priority value 1

pub fn pri_2(&mut self) -> PRI_2_W<'_>

Bits 16:23 - Priority value 2

pub fn pri_3(&mut self) -> PRI_3_W<'_>

Bits 24:31 - Priority value 3

impl W<u32, Reg<u32, _NVIC_IPR21>>

pub fn pri_0(&mut self) -> PRI_0_W<'_>

Bits 0:7 - Priority value 0

pub fn pri_1(&mut self) -> PRI_1_W<'_>

Bits 8:15 - Priority value 1

pub fn pri_2(&mut self) -> PRI_2_W<'_>

Bits 16:23 - Priority value 2

pub fn pri_3(&mut self) -> PRI_3_W<'_>

Bits 24:31 - Priority value 3

impl W<u32, Reg<u32, _NVIC_IPR22>>

pub fn pri_0(&mut self) -> PRI_0_W<'_>

Bits 0:7 - Priority value 0

pub fn pri_1(&mut self) -> PRI_1_W<'_>

Bits 8:15 - Priority value 1

pub fn pri_2(&mut self) -> PRI_2_W<'_>

Bits 16:23 - Priority value 2

pub fn pri_3(&mut self) -> PRI_3_W<'_>

Bits 24:31 - Priority value 3

impl W<u32, Reg<u32, _NVIC_IPR23>>

pub fn pri_0(&mut self) -> PRI_0_W<'_>

Bits 0:7 - Priority value 0

pub fn pri_1(&mut self) -> PRI_1_W<'_>

Bits 8:15 - Priority value 1

pub fn pri_2(&mut self) -> PRI_2_W<'_>

Bits 16:23 - Priority value 2

pub fn pri_3(&mut self) -> PRI_3_W<'_>

Bits 24:31 - Priority value 3

impl W<u32, Reg<u32, _NVIC_IPR24>>

pub fn pri_0(&mut self) -> PRI_0_W<'_>

Bits 0:7 - Priority value 0

pub fn pri_1(&mut self) -> PRI_1_W<'_>

Bits 8:15 - Priority value 1

pub fn pri_2(&mut self) -> PRI_2_W<'_>

Bits 16:23 - Priority value 2

pub fn pri_3(&mut self) -> PRI_3_W<'_>

Bits 24:31 - Priority value 3

impl W<u32, Reg<u32, _NVIC_IPR25>>

pub fn pri_0(&mut self) -> PRI_0_W<'_>

Bits 0:7 - Priority value 0

pub fn pri_1(&mut self) -> PRI_1_W<'_>

Bits 8:15 - Priority value 1

pub fn pri_2(&mut self) -> PRI_2_W<'_>

Bits 16:23 - Priority value 2

pub fn pri_3(&mut self) -> PRI_3_W<'_>

Bits 24:31 - Priority value 3

impl W<u32, Reg<u32, _NVIC_IPR26>>

pub fn pri_0(&mut self) -> PRI_0_W<'_>

Bits 0:7 - Priority value 0

pub fn pri_1(&mut self) -> PRI_1_W<'_>

Bits 8:15 - Priority value 1

pub fn pri_2(&mut self) -> PRI_2_W<'_>

Bits 16:23 - Priority value 2

pub fn pri_3(&mut self) -> PRI_3_W<'_>

Bits 24:31 - Priority value 3

impl W<u32, Reg<u32, _NVIC_IPR27>>

pub fn pri_0(&mut self) -> PRI_0_W<'_>

Bits 0:7 - Priority value 0

pub fn pri_1(&mut self) -> PRI_1_W<'_>

Bits 8:15 - Priority value 1

pub fn pri_2(&mut self) -> PRI_2_W<'_>

Bits 16:23 - Priority value 2

pub fn pri_3(&mut self) -> PRI_3_W<'_>

Bits 24:31 - Priority value 3

impl W<u32, Reg<u32, _ICSR>>

pub fn pendstclr(&mut self) -> PENDSTCLR_W<'_>

Bit 25 - SysTick exception clear-pending bit

pub fn pendstset(&mut self) -> PENDSTSET_W<'_>

Bit 26 - SysTick exception set-pending bit

pub fn pendsvclr(&mut self) -> PENDSVCLR_W<'_>

Bit 27 - PendSV clear-pending bit

pub fn pendsvset(&mut self) -> PENDSVSET_W<'_>

Bit 28 - PendSV set-pending bit: 0b0=no effect, 0b1=changes PendSV exception state to pending., 0b0=PendSV exception is not pending, 0b1=PendSV exception is pending.,

pub fn nmipendset(&mut self) -> NMIPENDSET_W<'_>

Bit 31 - NMI set-pending bit: 0b0=no effect, 0b1=changes NMI exception state to pending., 0b0=NMI exception is not pending, 0b1=NMI exception is pending.,

impl W<u32, Reg<u32, _VTOR>>

pub fn tbloff(&mut self) -> TBLOFF_W<'_>

Bits 10:31 - Vector table base offset field

impl W<u32, Reg<u32, _AIRCR>>

pub fn vectreset(&mut self) -> VECTRESET_W<'_>

Bit 0 - Reserved for Debug use.

pub fn vectclractive(&mut self) -> VECTCLRACTIVE_W<'_>

Bit 1 - Reserved for Debug use.

pub fn sysresetreq(&mut self) -> SYSRESETREQ_W<'_>

Bit 2 - System reset request

pub fn prigroup(&mut self) -> PRIGROUP_W<'_>

Bits 8:10 - Interrupt priority grouping field

pub fn vectkey(&mut self) -> VECTKEY_W<'_>

Bits 16:31 - Register key

impl W<u32, Reg<u32, _SCR>>

pub fn sleeponexit(&mut self) -> SLEEPONEXIT_W<'_>

Bit 1 - Sleep on Exit

pub fn sleepdeep(&mut self) -> SLEEPDEEP_W<'_>

Bit 2 - Sleep or Deep Sleep

pub fn sevonpend(&mut self) -> SEVONPEND_W<'_>

Bit 4 - Send Event on Pending bit:

impl W<u32, Reg<u32, _CCR>>

pub fn nonbasethrdena(&mut self) -> NONBASETHRDENA_W<'_>

Bit 0 - Non Base Thread Mode Enable

pub fn usersetmpend(&mut self) -> USERSETMPEND_W<'_>

Bit 1 - User Set Pending Enable

pub fn unalign_trp(&mut self) -> UNALIGN_TRP_W<'_>

Bit 3 - Unaligned Access Trap Enable

pub fn div_0_trp(&mut self) -> DIV_0_TRP_W<'_>

Bit 4 - Divide by Zero Trap Enable

pub fn bfhfnmign(&mut self) -> BFHFNMIGN_W<'_>

Bit 8 - Bus Fault Hard Fault and NMI Ignore

pub fn stkalign(&mut self) -> STKALIGN_W<'_>

Bit 9 - Stack Alignment

impl W<u32, Reg<u32, _SHPR1>>

pub fn pri_4(&mut self) -> PRI_4_W<'_>

Bits 0:7 - Priority of system handler 4, MemManage

pub fn pri_5(&mut self) -> PRI_5_W<'_>

Bits 8:15 - Priority of system handler 5, BusFault

pub fn pri_6(&mut self) -> PRI_6_W<'_>

Bits 16:23 - Priority of system handler 6, UsageFault

impl W<u32, Reg<u32, _SHPR2>>

pub fn pri_11(&mut self) -> PRI_11_W<'_>

Bits 24:31 - Priority of system handler 11, SVCall

impl W<u32, Reg<u32, _SHPR3>>

pub fn pri_14(&mut self) -> PRI_14_W<'_>

Bits 16:23 - Priority of system handler 14

pub fn pri_15(&mut self) -> PRI_15_W<'_>

Bits 24:31 - Priority of system handler 15

impl W<u32, Reg<u32, _SHCSR>>

pub fn memfaultact(&mut self) -> MEMFAULTACT_W<'_>

Bit 0 - MemManage exception active bit

pub fn busfaultact(&mut self) -> BUSFAULTACT_W<'_>

Bit 1 - BusFault exception active bit

pub fn usgfaultact(&mut self) -> USGFAULTACT_W<'_>

Bit 3 - UsageFault exception active bit

pub fn svcallact(&mut self) -> SVCALLACT_W<'_>

Bit 7 - SVCall active bit

pub fn monitoract(&mut self) -> MONITORACT_W<'_>

Bit 8 - Debug monitor active bit

pub fn pendsvact(&mut self) -> PENDSVACT_W<'_>

Bit 10 - PendSV exception active bit

pub fn systickact(&mut self) -> SYSTICKACT_W<'_>

Bit 11 - SysTick exception active bit

pub fn usgfaultpended(&mut self) -> USGFAULTPENDED_W<'_>

Bit 12 - UsageFault exception pending bit

pub fn memfaultpended(&mut self) -> MEMFAULTPENDED_W<'_>

Bit 13 - MemManage exception pending bit

pub fn busfaultpended(&mut self) -> BUSFAULTPENDED_W<'_>

Bit 14 - BusFault exception pending bit

pub fn svcallpended(&mut self) -> SVCALLPENDED_W<'_>

Bit 15 - SVCall pending bit

pub fn memfaultena(&mut self) -> MEMFAULTENA_W<'_>

Bit 16 - MemManage enable bit

pub fn busfaultena(&mut self) -> BUSFAULTENA_W<'_>

Bit 17 - BusFault enable bit

pub fn usgfaultena(&mut self) -> USGFAULTENA_W<'_>

Bit 18 - UsageFault enable bit

impl W<u32, Reg<u32, _CFSR>>

pub fn iaccviol(&mut self) -> IACCVIOL_W<'_>

Bit 0 - Instruction access violation flag

pub fn daccviol(&mut self) -> DACCVIOL_W<'_>

Bit 1 - Data access violation flag

pub fn munstkerr(&mut self) -> MUNSTKERR_W<'_>

Bit 3 - MemManage fault on unstacking for a return from exception

pub fn mstkerr(&mut self) -> MSTKERR_W<'_>

Bit 4 - MemManage fault on stacking for exception entry

pub fn mlsperr(&mut self) -> MLSPERR_W<'_>

Bit 5 - MemManage fault during floating point lazy state preservation

pub fn mmarvalid(&mut self) -> MMARVALID_W<'_>

Bit 7 - MemManage Fault Address Register (MMFAR) valid flag

pub fn ibuserr(&mut self) -> IBUSERR_W<'_>

Bit 8 - Instruction bus error

pub fn preciserr(&mut self) -> PRECISERR_W<'_>

Bit 9 - Precise data bus error

pub fn impreciserr(&mut self) -> IMPRECISERR_W<'_>

Bit 10 - Imprecise data bus error

pub fn unstkerr(&mut self) -> UNSTKERR_W<'_>

Bit 11 - BusFault on unstacking for a return from exception

pub fn stkerr(&mut self) -> STKERR_W<'_>

Bit 12 - BusFault on stacking for exception entry

pub fn lsperr(&mut self) -> LSPERR_W<'_>

Bit 13 - BusFault during floating point lazy state preservation

pub fn bfarvalid(&mut self) -> BFARVALID_W<'_>

Bit 15 - BusFault Address Register (BFAR) valid flag

pub fn undefinstr(&mut self) -> UNDEFINSTR_W<'_>

Bit 16 - Undefined instruction UsageFault

pub fn invstate(&mut self) -> INVSTATE_W<'_>

Bit 17 - Invalid state UsageFault

pub fn invpc(&mut self) -> INVPC_W<'_>

Bit 18 - Invalid PC load UsageFault

pub fn nocp(&mut self) -> NOCP_W<'_>

Bit 19 - No coprocessor UsageFault

pub fn unaligned(&mut self) -> UNALIGNED_W<'_>

Bit 24 - Unaligned access UsageFault

pub fn divbyzero(&mut self) -> DIVBYZERO_W<'_>

Bit 25 - Divide by zero UsageFault

impl W<u32, Reg<u32, _HFSR>>

pub fn vecttbl(&mut self) -> VECTTBL_W<'_>

Bit 1 - BusFault on vector table read

pub fn forced(&mut self) -> FORCED_W<'_>

Bit 30 - Forced HardFault

pub fn debugevt(&mut self) -> DEBUGEVT_W<'_>

Bit 31 - Reserved for Debug use

impl W<u32, Reg<u32, _MMFAR>>

pub fn address(&mut self) -> ADDRESS_W<'_>

Bits 0:31 - Address causing the fault

impl W<u32, Reg<u32, _BFAR>>

pub fn address(&mut self) -> ADDRESS_W<'_>

Bits 0:31 - Address causing the fault

impl W<u32, Reg<u32, _AFSR>>

pub fn value(&mut self) -> VALUE_W<'_>

Bits 0:31 - Reserved

impl W<u32, Reg<u32, _CPACR>>

pub fn cp10(&mut self) -> CP10_W<'_>

Bits 20:21 - Access privileges for coprocessor 10

pub fn cp11(&mut self) -> CP11_W<'_>

Bits 22:23 - Access privileges for coprocessor 11

impl W<u32, Reg<u32, _MPU_CTRL>>

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 0 - Enable MPU

pub fn hfnmiena(&mut self) -> HFNMIENA_W<'_>

Bit 1 - Enable the operation of MPU during hard fault, NMI, and FAULTMASK handlers

pub fn privdefena(&mut self) -> PRIVDEFENA_W<'_>

Bit 2 - Enables privileged software access to the default memory map

impl W<u32, Reg<u32, _MPU_RNR>>

pub fn region(&mut self) -> REGION_W<'_>

Bits 0:7 - Region

impl W<u32, Reg<u32, _MPU_RBAR>>

pub fn region(&mut self) -> REGION_W<'_>

Bits 0:3 - MPU region field

pub fn valid(&mut self) -> VALID_W<'_>

Bit 4 - MPU Region Number valid bit

pub fn addr(&mut self) -> ADDR_W<'_>

Bits 9:31 - Region base address field

impl W<u32, Reg<u32, _MPU_RASR>>

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 0 - Region enable bit.

pub fn size(&mut self) -> SIZE_W<'_>

Bits 1:5 - MPU protection region size

pub fn srd(&mut self) -> SRD_W<'_>

Bits 8:15 - Subregion disable bits

pub fn b(&mut self) -> B_W<'_>

Bit 16 - Memory access attribute

pub fn c(&mut self) -> C_W<'_>

Bit 17 - Memory access attribute

pub fn s(&mut self) -> S_W<'_>

Bit 18 - Shareable bit

pub fn tex(&mut self) -> TEX_W<'_>

Bits 19:21 - Memory access attribute

pub fn ap(&mut self) -> AP_W<'_>

Bits 24:26 - Access permission field

pub fn xn(&mut self) -> XN_W<'_>

Bit 28 - Instruction access disable bit

impl W<u32, Reg<u32, _MPU_RBAR_A1>>

pub fn region(&mut self) -> REGION_W<'_>

Bits 0:3 - MPU region field

pub fn valid(&mut self) -> VALID_W<'_>

Bit 4 - MPU Region Number valid bit

pub fn addr(&mut self) -> ADDR_W<'_>

Bits 9:31 - Region base address field

impl W<u32, Reg<u32, _MPU_RASR_A1>>

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 0 - Region enable bit.

pub fn size(&mut self) -> SIZE_W<'_>

Bits 1:5 - MPU protection region size

pub fn srd(&mut self) -> SRD_W<'_>

Bits 8:15 - Subregion disable bits

pub fn b(&mut self) -> B_W<'_>

Bit 16 - Memory access attribute

pub fn c(&mut self) -> C_W<'_>

Bit 17 - Memory access attribute

pub fn s(&mut self) -> S_W<'_>

Bit 18 - Shareable bit

pub fn tex(&mut self) -> TEX_W<'_>

Bits 19:21 - Memory access attribute

pub fn ap(&mut self) -> AP_W<'_>

Bits 24:26 - Access permission field

pub fn xn(&mut self) -> XN_W<'_>

Bit 28 - Instruction access disable bit

impl W<u32, Reg<u32, _MPU_RBAR_A2>>

pub fn region(&mut self) -> REGION_W<'_>

Bits 0:3 - MPU region field

pub fn valid(&mut self) -> VALID_W<'_>

Bit 4 - MPU Region Number valid bit

pub fn addr(&mut self) -> ADDR_W<'_>

Bits 9:31 - Region base address field

impl W<u32, Reg<u32, _MPU_RASR_A2>>

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 0 - Region enable bit.

pub fn size(&mut self) -> SIZE_W<'_>

Bits 1:5 - MPU protection region size

pub fn srd(&mut self) -> SRD_W<'_>

Bits 8:15 - Subregion disable bits

pub fn b(&mut self) -> B_W<'_>

Bit 16 - Memory access attribute

pub fn c(&mut self) -> C_W<'_>

Bit 17 - Memory access attribute

pub fn s(&mut self) -> S_W<'_>

Bit 18 - Shareable bit

pub fn tex(&mut self) -> TEX_W<'_>

Bits 19:21 - Memory access attribute

pub fn ap(&mut self) -> AP_W<'_>

Bits 24:26 - Access permission field

pub fn xn(&mut self) -> XN_W<'_>

Bit 28 - Instruction access disable bit

impl W<u32, Reg<u32, _MPU_RBAR_A3>>

pub fn region(&mut self) -> REGION_W<'_>

Bits 0:3 - MPU region field

pub fn valid(&mut self) -> VALID_W<'_>

Bit 4 - MPU Region Number valid bit

pub fn addr(&mut self) -> ADDR_W<'_>

Bits 9:31 - Region base address field

impl W<u32, Reg<u32, _MPU_RASR_A3>>

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 0 - Region enable bit.

pub fn size(&mut self) -> SIZE_W<'_>

Bits 1:5 - MPU protection region size

pub fn srd(&mut self) -> SRD_W<'_>

Bits 8:15 - Subregion disable bits

pub fn b(&mut self) -> B_W<'_>

Bit 16 - Memory access attribute

pub fn c(&mut self) -> C_W<'_>

Bit 17 - Memory access attribute

pub fn s(&mut self) -> S_W<'_>

Bit 18 - Shareable bit

pub fn tex(&mut self) -> TEX_W<'_>

Bits 19:21 - Memory access attribute

pub fn ap(&mut self) -> AP_W<'_>

Bits 24:26 - Access permission field

pub fn xn(&mut self) -> XN_W<'_>

Bit 28 - Instruction access disable bit

impl W<u32, Reg<u32, _STIR>>

pub fn intid(&mut self) -> INTID_W<'_>

Bits 0:8 - Interrupt ID of the interrupt to trigger

impl W<u32, Reg<u32, _FPCCR>>

pub fn lspact(&mut self) -> LSPACT_W<'_>

Bit 0 - Lazy State Preservation Active

pub fn user(&mut self) -> USER_W<'_>

Bit 1 - User allocated Stack Frame

pub fn thread(&mut self) -> THREAD_W<'_>

Bit 3 - Thread Mode allocated Stack Frame

pub fn hfrdy(&mut self) -> HFRDY_W<'_>

Bit 4 - HardFault Ready

pub fn mmrdy(&mut self) -> MMRDY_W<'_>

Bit 5 - MemManage Ready

pub fn bfrdy(&mut self) -> BFRDY_W<'_>

Bit 6 - BusFault Ready

pub fn monrdy(&mut self) -> MONRDY_W<'_>

Bit 8 - Monitor Ready

pub fn lspen(&mut self) -> LSPEN_W<'_>

Bit 30 - Lazy State Preservation Enabled

pub fn aspen(&mut self) -> ASPEN_W<'_>

Bit 31 - Automatic State Preservation

impl W<u32, Reg<u32, _FPCAR>>

pub fn address(&mut self) -> ADDRESS_W<'_>

Bits 3:31 - Address

impl W<u32, Reg<u32, _FPDSCR>>

pub fn rmode(&mut self) -> RMODE_W<'_>

Bits 22:23 - Default value for FPSCR.RMode

pub fn fz(&mut self) -> FZ_W<'_>

Bit 24 - Default value for FPSCR.FZ

pub fn dn(&mut self) -> DN_W<'_>

Bit 25 - Default value for FPSCR.DN

pub fn ahp(&mut self) -> AHP_W<'_>

Bit 26 - Default value for FPSCR.AHP

impl W<u32, Reg<u32, _OVRCLR>>

pub fn ln0(&mut self) -> LN0_W<'_>

Bit 0 - Line 0 Overrun Status Clear

pub fn ln1(&mut self) -> LN1_W<'_>

Bit 1 - Line 1 Overrun Status Clear

pub fn ln2(&mut self) -> LN2_W<'_>

Bit 2 - Line 2 Overrun Status Clear

pub fn ln3(&mut self) -> LN3_W<'_>

Bit 3 - Line 3 Overrun Status Clear

pub fn ln4(&mut self) -> LN4_W<'_>

Bit 4 - Line 4 Overrun Status Clear

pub fn ln5(&mut self) -> LN5_W<'_>

Bit 5 - Line 5 Overrun Status Clear

pub fn ln6(&mut self) -> LN6_W<'_>

Bit 6 - Line 6 Overrun Status Clear

pub fn ln7(&mut self) -> LN7_W<'_>

Bit 7 - Line 7 Overrun Status Clear

impl W<u32, Reg<u32, _SRSEL0>>

pub fn rs0(&mut self) -> RS0_W<'_>

Bits 0:3 - Request Source for Line 0

pub fn rs1(&mut self) -> RS1_W<'_>

Bits 4:7 - Request Source for Line 1

pub fn rs2(&mut self) -> RS2_W<'_>

Bits 8:11 - Request Source for Line 2

pub fn rs3(&mut self) -> RS3_W<'_>

Bits 12:15 - Request Source for Line 3

pub fn rs4(&mut self) -> RS4_W<'_>

Bits 16:19 - Request Source for Line 4

pub fn rs5(&mut self) -> RS5_W<'_>

Bits 20:23 - Request Source for Line 5

pub fn rs6(&mut self) -> RS6_W<'_>

Bits 24:27 - Request Source for Line 6

pub fn rs7(&mut self) -> RS7_W<'_>

Bits 28:31 - Request Source for Line 7

impl W<u32, Reg<u32, _LNEN>>

pub fn ln0(&mut self) -> LN0_W<'_>

Bit 0 - Line 0 Enable

pub fn ln1(&mut self) -> LN1_W<'_>

Bit 1 - Line 1 Enable

pub fn ln2(&mut self) -> LN2_W<'_>

Bit 2 - Line 2 Enable

pub fn ln3(&mut self) -> LN3_W<'_>

Bit 3 - Line 3 Enable

pub fn ln4(&mut self) -> LN4_W<'_>

Bit 4 - Line 4 Enable

pub fn ln5(&mut self) -> LN5_W<'_>

Bit 5 - Line 5 Enable

pub fn ln6(&mut self) -> LN6_W<'_>

Bit 6 - Line 6 Enable

pub fn ln7(&mut self) -> LN7_W<'_>

Bit 7 - Line 7 Enable

impl W<u32, Reg<u32, _EXISEL>>

pub fn exs0a(&mut self) -> EXS0A_W<'_>

Bits 0:1 - Event Source Select for A0 (ERS0)

pub fn exs0b(&mut self) -> EXS0B_W<'_>

Bits 2:3 - Event Source Select for B0 (ERS0)

pub fn exs1a(&mut self) -> EXS1A_W<'_>

Bits 4:5 - Event Source Select for A1 (ERS1)

pub fn exs1b(&mut self) -> EXS1B_W<'_>

Bits 6:7 - Event Source Select for B1 (ERS1)

pub fn exs2a(&mut self) -> EXS2A_W<'_>

Bits 8:9 - Event Source Select for A2 (ERS2)

pub fn exs2b(&mut self) -> EXS2B_W<'_>

Bits 10:11 - Event Source Select for B2 (ERS2)

pub fn exs3a(&mut self) -> EXS3A_W<'_>

Bits 12:13 - Event Source Select for A3 (ERS3)

pub fn exs3b(&mut self) -> EXS3B_W<'_>

Bits 14:15 - Event Source Select for B3 (ERS3)

impl W<u32, Reg<u32, _EXICON>>

pub fn pe(&mut self) -> PE_W<'_>

Bit 0 - Output Trigger Pulse Enable for ETLx

pub fn ld(&mut self) -> LD_W<'_>

Bit 1 - Rebuild Level Detection for Status Flag for ETLx

pub fn re(&mut self) -> RE_W<'_>

Bit 2 - Rising Edge Detection Enable ETLx

pub fn fe(&mut self) -> FE_W<'_>

Bit 3 - Falling Edge Detection Enable ETLx

pub fn ocs(&mut self) -> OCS_W<'_>

Bits 4:6 - Output Channel Select for ETLx Output Trigger Pulse

pub fn fl(&mut self) -> FL_W<'_>

Bit 7 - Status Flag for ETLx

pub fn ss(&mut self) -> SS_W<'_>

Bits 8:9 - Input Source Select for ERSx

pub fn na(&mut self) -> NA_W<'_>

Bit 10 - Input A Negation Select for ERSx

pub fn nb(&mut self) -> NB_W<'_>

Bit 11 - Input B Negation Select for ERSx

impl W<u32, Reg<u32, _EXOCON>>

pub fn iss(&mut self) -> ISS_W<'_>

Bits 0:1 - Internal Trigger Source Selection

pub fn geen(&mut self) -> GEEN_W<'_>

Bit 2 - Gating Event Enable

pub fn gp(&mut self) -> GP_W<'_>

Bits 4:5 - Gating Selection for Pattern Detection Result

pub fn ipen0(&mut self) -> IPEN0_W<'_>

Bit 12 - Pattern Detection Enable for ETL0

pub fn ipen1(&mut self) -> IPEN1_W<'_>

Bit 13 - Pattern Detection Enable for ETL1

pub fn ipen2(&mut self) -> IPEN2_W<'_>

Bit 14 - Pattern Detection Enable for ETL2

pub fn ipen3(&mut self) -> IPEN3_W<'_>

Bit 15 - Pattern Detection Enable for ETL3

impl W<u32, Reg<u32, _RAWTFR>>

pub fn ch0(&mut self) -> CH0_W<'_>

Bit 0 - Raw Interrupt Status for channel 0

pub fn ch1(&mut self) -> CH1_W<'_>

Bit 1 - Raw Interrupt Status for channel 1

pub fn ch2(&mut self) -> CH2_W<'_>

Bit 2 - Raw Interrupt Status for channel 2

pub fn ch3(&mut self) -> CH3_W<'_>

Bit 3 - Raw Interrupt Status for channel 3

pub fn ch4(&mut self) -> CH4_W<'_>

Bit 4 - Raw Interrupt Status for channel 4

pub fn ch5(&mut self) -> CH5_W<'_>

Bit 5 - Raw Interrupt Status for channel 5

pub fn ch6(&mut self) -> CH6_W<'_>

Bit 6 - Raw Interrupt Status for channel 6

pub fn ch7(&mut self) -> CH7_W<'_>

Bit 7 - Raw Interrupt Status for channel 7

impl W<u32, Reg<u32, _RAWBLOCK>>

pub fn ch0(&mut self) -> CH0_W<'_>

Bit 0 - Raw Interrupt Status for channel 0

pub fn ch1(&mut self) -> CH1_W<'_>

Bit 1 - Raw Interrupt Status for channel 1

pub fn ch2(&mut self) -> CH2_W<'_>

Bit 2 - Raw Interrupt Status for channel 2

pub fn ch3(&mut self) -> CH3_W<'_>

Bit 3 - Raw Interrupt Status for channel 3

pub fn ch4(&mut self) -> CH4_W<'_>

Bit 4 - Raw Interrupt Status for channel 4

pub fn ch5(&mut self) -> CH5_W<'_>

Bit 5 - Raw Interrupt Status for channel 5

pub fn ch6(&mut self) -> CH6_W<'_>

Bit 6 - Raw Interrupt Status for channel 6

pub fn ch7(&mut self) -> CH7_W<'_>

Bit 7 - Raw Interrupt Status for channel 7

impl W<u32, Reg<u32, _RAWSRCTRAN>>

pub fn ch0(&mut self) -> CH0_W<'_>

Bit 0 - Raw Interrupt Status for channel 0

pub fn ch1(&mut self) -> CH1_W<'_>

Bit 1 - Raw Interrupt Status for channel 1

pub fn ch2(&mut self) -> CH2_W<'_>

Bit 2 - Raw Interrupt Status for channel 2

pub fn ch3(&mut self) -> CH3_W<'_>

Bit 3 - Raw Interrupt Status for channel 3

pub fn ch4(&mut self) -> CH4_W<'_>

Bit 4 - Raw Interrupt Status for channel 4

pub fn ch5(&mut self) -> CH5_W<'_>

Bit 5 - Raw Interrupt Status for channel 5

pub fn ch6(&mut self) -> CH6_W<'_>

Bit 6 - Raw Interrupt Status for channel 6

pub fn ch7(&mut self) -> CH7_W<'_>

Bit 7 - Raw Interrupt Status for channel 7

impl W<u32, Reg<u32, _RAWDSTTRAN>>

pub fn ch0(&mut self) -> CH0_W<'_>

Bit 0 - Raw Interrupt Status for channel 0

pub fn ch1(&mut self) -> CH1_W<'_>

Bit 1 - Raw Interrupt Status for channel 1

pub fn ch2(&mut self) -> CH2_W<'_>

Bit 2 - Raw Interrupt Status for channel 2

pub fn ch3(&mut self) -> CH3_W<'_>

Bit 3 - Raw Interrupt Status for channel 3

pub fn ch4(&mut self) -> CH4_W<'_>

Bit 4 - Raw Interrupt Status for channel 4

pub fn ch5(&mut self) -> CH5_W<'_>

Bit 5 - Raw Interrupt Status for channel 5

pub fn ch6(&mut self) -> CH6_W<'_>

Bit 6 - Raw Interrupt Status for channel 6

pub fn ch7(&mut self) -> CH7_W<'_>

Bit 7 - Raw Interrupt Status for channel 7

impl W<u32, Reg<u32, _RAWERR>>

pub fn ch0(&mut self) -> CH0_W<'_>

Bit 0 - Raw Interrupt Status for channel 0

pub fn ch1(&mut self) -> CH1_W<'_>

Bit 1 - Raw Interrupt Status for channel 1

pub fn ch2(&mut self) -> CH2_W<'_>

Bit 2 - Raw Interrupt Status for channel 2

pub fn ch3(&mut self) -> CH3_W<'_>

Bit 3 - Raw Interrupt Status for channel 3

pub fn ch4(&mut self) -> CH4_W<'_>

Bit 4 - Raw Interrupt Status for channel 4

pub fn ch5(&mut self) -> CH5_W<'_>

Bit 5 - Raw Interrupt Status for channel 5

pub fn ch6(&mut self) -> CH6_W<'_>

Bit 6 - Raw Interrupt Status for channel 6

pub fn ch7(&mut self) -> CH7_W<'_>

Bit 7 - Raw Interrupt Status for channel 7

impl W<u32, Reg<u32, _MASKTFR>>

pub fn we_ch0(&mut self) -> WE_CH0_W<'_>

Bit 8 - Write enable for mask bit of channel 0

pub fn we_ch1(&mut self) -> WE_CH1_W<'_>

Bit 9 - Write enable for mask bit of channel 1

pub fn we_ch2(&mut self) -> WE_CH2_W<'_>

Bit 10 - Write enable for mask bit of channel 2

pub fn we_ch3(&mut self) -> WE_CH3_W<'_>

Bit 11 - Write enable for mask bit of channel 3

pub fn we_ch4(&mut self) -> WE_CH4_W<'_>

Bit 12 - Write enable for mask bit of channel 4

pub fn we_ch5(&mut self) -> WE_CH5_W<'_>

Bit 13 - Write enable for mask bit of channel 5

pub fn we_ch6(&mut self) -> WE_CH6_W<'_>

Bit 14 - Write enable for mask bit of channel 6

pub fn we_ch7(&mut self) -> WE_CH7_W<'_>

Bit 15 - Write enable for mask bit of channel 7

pub fn ch0(&mut self) -> CH0_W<'_>

Bit 0 - Mask bit for channel 0

pub fn ch1(&mut self) -> CH1_W<'_>

Bit 1 - Mask bit for channel 1

pub fn ch2(&mut self) -> CH2_W<'_>

Bit 2 - Mask bit for channel 2

pub fn ch3(&mut self) -> CH3_W<'_>

Bit 3 - Mask bit for channel 3

pub fn ch4(&mut self) -> CH4_W<'_>

Bit 4 - Mask bit for channel 4

pub fn ch5(&mut self) -> CH5_W<'_>

Bit 5 - Mask bit for channel 5

pub fn ch6(&mut self) -> CH6_W<'_>

Bit 6 - Mask bit for channel 6

pub fn ch7(&mut self) -> CH7_W<'_>

Bit 7 - Mask bit for channel 7

impl W<u32, Reg<u32, _MASKBLOCK>>

pub fn we_ch0(&mut self) -> WE_CH0_W<'_>

Bit 8 - Write enable for mask bit of channel 0

pub fn we_ch1(&mut self) -> WE_CH1_W<'_>

Bit 9 - Write enable for mask bit of channel 1

pub fn we_ch2(&mut self) -> WE_CH2_W<'_>

Bit 10 - Write enable for mask bit of channel 2

pub fn we_ch3(&mut self) -> WE_CH3_W<'_>

Bit 11 - Write enable for mask bit of channel 3

pub fn we_ch4(&mut self) -> WE_CH4_W<'_>

Bit 12 - Write enable for mask bit of channel 4

pub fn we_ch5(&mut self) -> WE_CH5_W<'_>

Bit 13 - Write enable for mask bit of channel 5

pub fn we_ch6(&mut self) -> WE_CH6_W<'_>

Bit 14 - Write enable for mask bit of channel 6

pub fn we_ch7(&mut self) -> WE_CH7_W<'_>

Bit 15 - Write enable for mask bit of channel 7

pub fn ch0(&mut self) -> CH0_W<'_>

Bit 0 - Mask bit for channel 0

pub fn ch1(&mut self) -> CH1_W<'_>

Bit 1 - Mask bit for channel 1

pub fn ch2(&mut self) -> CH2_W<'_>

Bit 2 - Mask bit for channel 2

pub fn ch3(&mut self) -> CH3_W<'_>

Bit 3 - Mask bit for channel 3

pub fn ch4(&mut self) -> CH4_W<'_>

Bit 4 - Mask bit for channel 4

pub fn ch5(&mut self) -> CH5_W<'_>

Bit 5 - Mask bit for channel 5

pub fn ch6(&mut self) -> CH6_W<'_>

Bit 6 - Mask bit for channel 6

pub fn ch7(&mut self) -> CH7_W<'_>

Bit 7 - Mask bit for channel 7

impl W<u32, Reg<u32, _MASKSRCTRAN>>

pub fn we_ch0(&mut self) -> WE_CH0_W<'_>

Bit 8 - Write enable for mask bit of channel 0

pub fn we_ch1(&mut self) -> WE_CH1_W<'_>

Bit 9 - Write enable for mask bit of channel 1

pub fn we_ch2(&mut self) -> WE_CH2_W<'_>

Bit 10 - Write enable for mask bit of channel 2

pub fn we_ch3(&mut self) -> WE_CH3_W<'_>

Bit 11 - Write enable for mask bit of channel 3

pub fn we_ch4(&mut self) -> WE_CH4_W<'_>

Bit 12 - Write enable for mask bit of channel 4

pub fn we_ch5(&mut self) -> WE_CH5_W<'_>

Bit 13 - Write enable for mask bit of channel 5

pub fn we_ch6(&mut self) -> WE_CH6_W<'_>

Bit 14 - Write enable for mask bit of channel 6

pub fn we_ch7(&mut self) -> WE_CH7_W<'_>

Bit 15 - Write enable for mask bit of channel 7

pub fn ch0(&mut self) -> CH0_W<'_>

Bit 0 - Mask bit for channel 0

pub fn ch1(&mut self) -> CH1_W<'_>

Bit 1 - Mask bit for channel 1

pub fn ch2(&mut self) -> CH2_W<'_>

Bit 2 - Mask bit for channel 2

pub fn ch3(&mut self) -> CH3_W<'_>

Bit 3 - Mask bit for channel 3

pub fn ch4(&mut self) -> CH4_W<'_>

Bit 4 - Mask bit for channel 4

pub fn ch5(&mut self) -> CH5_W<'_>

Bit 5 - Mask bit for channel 5

pub fn ch6(&mut self) -> CH6_W<'_>

Bit 6 - Mask bit for channel 6

pub fn ch7(&mut self) -> CH7_W<'_>

Bit 7 - Mask bit for channel 7

impl W<u32, Reg<u32, _MASKDSTTRAN>>

pub fn we_ch0(&mut self) -> WE_CH0_W<'_>

Bit 8 - Write enable for mask bit of channel 0

pub fn we_ch1(&mut self) -> WE_CH1_W<'_>

Bit 9 - Write enable for mask bit of channel 1

pub fn we_ch2(&mut self) -> WE_CH2_W<'_>

Bit 10 - Write enable for mask bit of channel 2

pub fn we_ch3(&mut self) -> WE_CH3_W<'_>

Bit 11 - Write enable for mask bit of channel 3

pub fn we_ch4(&mut self) -> WE_CH4_W<'_>

Bit 12 - Write enable for mask bit of channel 4

pub fn we_ch5(&mut self) -> WE_CH5_W<'_>

Bit 13 - Write enable for mask bit of channel 5

pub fn we_ch6(&mut self) -> WE_CH6_W<'_>

Bit 14 - Write enable for mask bit of channel 6

pub fn we_ch7(&mut self) -> WE_CH7_W<'_>

Bit 15 - Write enable for mask bit of channel 7

pub fn ch0(&mut self) -> CH0_W<'_>

Bit 0 - Mask bit for channel 0

pub fn ch1(&mut self) -> CH1_W<'_>

Bit 1 - Mask bit for channel 1

pub fn ch2(&mut self) -> CH2_W<'_>

Bit 2 - Mask bit for channel 2

pub fn ch3(&mut self) -> CH3_W<'_>

Bit 3 - Mask bit for channel 3

pub fn ch4(&mut self) -> CH4_W<'_>

Bit 4 - Mask bit for channel 4

pub fn ch5(&mut self) -> CH5_W<'_>

Bit 5 - Mask bit for channel 5

pub fn ch6(&mut self) -> CH6_W<'_>

Bit 6 - Mask bit for channel 6

pub fn ch7(&mut self) -> CH7_W<'_>

Bit 7 - Mask bit for channel 7

impl W<u32, Reg<u32, _MASKERR>>

pub fn we_ch0(&mut self) -> WE_CH0_W<'_>

Bit 8 - Write enable for mask bit of channel 0

pub fn we_ch1(&mut self) -> WE_CH1_W<'_>

Bit 9 - Write enable for mask bit of channel 1

pub fn we_ch2(&mut self) -> WE_CH2_W<'_>

Bit 10 - Write enable for mask bit of channel 2

pub fn we_ch3(&mut self) -> WE_CH3_W<'_>

Bit 11 - Write enable for mask bit of channel 3

pub fn we_ch4(&mut self) -> WE_CH4_W<'_>

Bit 12 - Write enable for mask bit of channel 4

pub fn we_ch5(&mut self) -> WE_CH5_W<'_>

Bit 13 - Write enable for mask bit of channel 5

pub fn we_ch6(&mut self) -> WE_CH6_W<'_>

Bit 14 - Write enable for mask bit of channel 6

pub fn we_ch7(&mut self) -> WE_CH7_W<'_>

Bit 15 - Write enable for mask bit of channel 7

pub fn ch0(&mut self) -> CH0_W<'_>

Bit 0 - Mask bit for channel 0

pub fn ch1(&mut self) -> CH1_W<'_>

Bit 1 - Mask bit for channel 1

pub fn ch2(&mut self) -> CH2_W<'_>

Bit 2 - Mask bit for channel 2

pub fn ch3(&mut self) -> CH3_W<'_>

Bit 3 - Mask bit for channel 3

pub fn ch4(&mut self) -> CH4_W<'_>

Bit 4 - Mask bit for channel 4

pub fn ch5(&mut self) -> CH5_W<'_>

Bit 5 - Mask bit for channel 5

pub fn ch6(&mut self) -> CH6_W<'_>

Bit 6 - Mask bit for channel 6

pub fn ch7(&mut self) -> CH7_W<'_>

Bit 7 - Mask bit for channel 7

impl W<u32, Reg<u32, _CLEARTFR>>

pub fn ch0(&mut self) -> CH0_W<'_>

Bit 0 - Clear Interrupt Status and Raw Status for channel 0

pub fn ch1(&mut self) -> CH1_W<'_>

Bit 1 - Clear Interrupt Status and Raw Status for channel 1

pub fn ch2(&mut self) -> CH2_W<'_>

Bit 2 - Clear Interrupt Status and Raw Status for channel 2

pub fn ch3(&mut self) -> CH3_W<'_>

Bit 3 - Clear Interrupt Status and Raw Status for channel 3

pub fn ch4(&mut self) -> CH4_W<'_>

Bit 4 - Clear Interrupt Status and Raw Status for channel 4

pub fn ch5(&mut self) -> CH5_W<'_>

Bit 5 - Clear Interrupt Status and Raw Status for channel 5

pub fn ch6(&mut self) -> CH6_W<'_>

Bit 6 - Clear Interrupt Status and Raw Status for channel 6

pub fn ch7(&mut self) -> CH7_W<'_>

Bit 7 - Clear Interrupt Status and Raw Status for channel 7

impl W<u32, Reg<u32, _CLEARBLOCK>>

pub fn ch0(&mut self) -> CH0_W<'_>

Bit 0 - Clear Interrupt Status and Raw Status for channel 0

pub fn ch1(&mut self) -> CH1_W<'_>

Bit 1 - Clear Interrupt Status and Raw Status for channel 1

pub fn ch2(&mut self) -> CH2_W<'_>

Bit 2 - Clear Interrupt Status and Raw Status for channel 2

pub fn ch3(&mut self) -> CH3_W<'_>

Bit 3 - Clear Interrupt Status and Raw Status for channel 3

pub fn ch4(&mut self) -> CH4_W<'_>

Bit 4 - Clear Interrupt Status and Raw Status for channel 4

pub fn ch5(&mut self) -> CH5_W<'_>

Bit 5 - Clear Interrupt Status and Raw Status for channel 5

pub fn ch6(&mut self) -> CH6_W<'_>

Bit 6 - Clear Interrupt Status and Raw Status for channel 6

pub fn ch7(&mut self) -> CH7_W<'_>

Bit 7 - Clear Interrupt Status and Raw Status for channel 7

impl W<u32, Reg<u32, _CLEARSRCTRAN>>

pub fn ch0(&mut self) -> CH0_W<'_>

Bit 0 - Clear Interrupt Status and Raw Status for channel 0

pub fn ch1(&mut self) -> CH1_W<'_>

Bit 1 - Clear Interrupt Status and Raw Status for channel 1

pub fn ch2(&mut self) -> CH2_W<'_>

Bit 2 - Clear Interrupt Status and Raw Status for channel 2

pub fn ch3(&mut self) -> CH3_W<'_>

Bit 3 - Clear Interrupt Status and Raw Status for channel 3

pub fn ch4(&mut self) -> CH4_W<'_>

Bit 4 - Clear Interrupt Status and Raw Status for channel 4

pub fn ch5(&mut self) -> CH5_W<'_>

Bit 5 - Clear Interrupt Status and Raw Status for channel 5

pub fn ch6(&mut self) -> CH6_W<'_>

Bit 6 - Clear Interrupt Status and Raw Status for channel 6

pub fn ch7(&mut self) -> CH7_W<'_>

Bit 7 - Clear Interrupt Status and Raw Status for channel 7

impl W<u32, Reg<u32, _CLEARDSTTRAN>>

pub fn ch0(&mut self) -> CH0_W<'_>

Bit 0 - Clear Interrupt Status and Raw Status for channel 0

pub fn ch1(&mut self) -> CH1_W<'_>

Bit 1 - Clear Interrupt Status and Raw Status for channel 1

pub fn ch2(&mut self) -> CH2_W<'_>

Bit 2 - Clear Interrupt Status and Raw Status for channel 2

pub fn ch3(&mut self) -> CH3_W<'_>

Bit 3 - Clear Interrupt Status and Raw Status for channel 3

pub fn ch4(&mut self) -> CH4_W<'_>

Bit 4 - Clear Interrupt Status and Raw Status for channel 4

pub fn ch5(&mut self) -> CH5_W<'_>

Bit 5 - Clear Interrupt Status and Raw Status for channel 5

pub fn ch6(&mut self) -> CH6_W<'_>

Bit 6 - Clear Interrupt Status and Raw Status for channel 6

pub fn ch7(&mut self) -> CH7_W<'_>

Bit 7 - Clear Interrupt Status and Raw Status for channel 7

impl W<u32, Reg<u32, _CLEARERR>>

pub fn ch0(&mut self) -> CH0_W<'_>

Bit 0 - Clear Interrupt Status and Raw Status for channel 0

pub fn ch1(&mut self) -> CH1_W<'_>

Bit 1 - Clear Interrupt Status and Raw Status for channel 1

pub fn ch2(&mut self) -> CH2_W<'_>

Bit 2 - Clear Interrupt Status and Raw Status for channel 2

pub fn ch3(&mut self) -> CH3_W<'_>

Bit 3 - Clear Interrupt Status and Raw Status for channel 3

pub fn ch4(&mut self) -> CH4_W<'_>

Bit 4 - Clear Interrupt Status and Raw Status for channel 4

pub fn ch5(&mut self) -> CH5_W<'_>

Bit 5 - Clear Interrupt Status and Raw Status for channel 5

pub fn ch6(&mut self) -> CH6_W<'_>

Bit 6 - Clear Interrupt Status and Raw Status for channel 6

pub fn ch7(&mut self) -> CH7_W<'_>

Bit 7 - Clear Interrupt Status and Raw Status for channel 7

impl W<u32, Reg<u32, _REQSRCREG>>

pub fn we_ch0(&mut self) -> WE_CH0_W<'_>

Bit 8 - Source request write enable for channel 0

pub fn we_ch1(&mut self) -> WE_CH1_W<'_>

Bit 9 - Source request write enable for channel 1

pub fn we_ch2(&mut self) -> WE_CH2_W<'_>

Bit 10 - Source request write enable for channel 2

pub fn we_ch3(&mut self) -> WE_CH3_W<'_>

Bit 11 - Source request write enable for channel 3

pub fn we_ch4(&mut self) -> WE_CH4_W<'_>

Bit 12 - Source request write enable for channel 4

pub fn we_ch5(&mut self) -> WE_CH5_W<'_>

Bit 13 - Source request write enable for channel 5

pub fn we_ch6(&mut self) -> WE_CH6_W<'_>

Bit 14 - Source request write enable for channel 6

pub fn we_ch7(&mut self) -> WE_CH7_W<'_>

Bit 15 - Source request write enable for channel 7

pub fn ch0(&mut self) -> CH0_W<'_>

Bit 0 - Source request for channel 0

pub fn ch1(&mut self) -> CH1_W<'_>

Bit 1 - Source request for channel 1

pub fn ch2(&mut self) -> CH2_W<'_>

Bit 2 - Source request for channel 2

pub fn ch3(&mut self) -> CH3_W<'_>

Bit 3 - Source request for channel 3

pub fn ch4(&mut self) -> CH4_W<'_>

Bit 4 - Source request for channel 4

pub fn ch5(&mut self) -> CH5_W<'_>

Bit 5 - Source request for channel 5

pub fn ch6(&mut self) -> CH6_W<'_>

Bit 6 - Source request for channel 6

pub fn ch7(&mut self) -> CH7_W<'_>

Bit 7 - Source request for channel 7

impl W<u32, Reg<u32, _REQDSTREG>>

pub fn we_ch0(&mut self) -> WE_CH0_W<'_>

Bit 8 - Source request write enable for channel 0

pub fn we_ch1(&mut self) -> WE_CH1_W<'_>

Bit 9 - Source request write enable for channel 1

pub fn we_ch2(&mut self) -> WE_CH2_W<'_>

Bit 10 - Source request write enable for channel 2

pub fn we_ch3(&mut self) -> WE_CH3_W<'_>

Bit 11 - Source request write enable for channel 3

pub fn we_ch4(&mut self) -> WE_CH4_W<'_>

Bit 12 - Source request write enable for channel 4

pub fn we_ch5(&mut self) -> WE_CH5_W<'_>

Bit 13 - Source request write enable for channel 5

pub fn we_ch6(&mut self) -> WE_CH6_W<'_>

Bit 14 - Source request write enable for channel 6

pub fn we_ch7(&mut self) -> WE_CH7_W<'_>

Bit 15 - Source request write enable for channel 7

pub fn ch0(&mut self) -> CH0_W<'_>

Bit 0 - Source request for channel 0

pub fn ch1(&mut self) -> CH1_W<'_>

Bit 1 - Source request for channel 1

pub fn ch2(&mut self) -> CH2_W<'_>

Bit 2 - Source request for channel 2

pub fn ch3(&mut self) -> CH3_W<'_>

Bit 3 - Source request for channel 3

pub fn ch4(&mut self) -> CH4_W<'_>

Bit 4 - Source request for channel 4

pub fn ch5(&mut self) -> CH5_W<'_>

Bit 5 - Source request for channel 5

pub fn ch6(&mut self) -> CH6_W<'_>

Bit 6 - Source request for channel 6

pub fn ch7(&mut self) -> CH7_W<'_>

Bit 7 - Source request for channel 7

impl W<u32, Reg<u32, _SGLREQSRCREG>>

pub fn we_ch0(&mut self) -> WE_CH0_W<'_>

Bit 8 - Source request write enable for channel 0

pub fn we_ch1(&mut self) -> WE_CH1_W<'_>

Bit 9 - Source request write enable for channel 1

pub fn we_ch2(&mut self) -> WE_CH2_W<'_>

Bit 10 - Source request write enable for channel 2

pub fn we_ch3(&mut self) -> WE_CH3_W<'_>

Bit 11 - Source request write enable for channel 3

pub fn we_ch4(&mut self) -> WE_CH4_W<'_>

Bit 12 - Source request write enable for channel 4

pub fn we_ch5(&mut self) -> WE_CH5_W<'_>

Bit 13 - Source request write enable for channel 5

pub fn we_ch6(&mut self) -> WE_CH6_W<'_>

Bit 14 - Source request write enable for channel 6

pub fn we_ch7(&mut self) -> WE_CH7_W<'_>

Bit 15 - Source request write enable for channel 7

pub fn ch0(&mut self) -> CH0_W<'_>

Bit 0 - Source request for channel 0

pub fn ch1(&mut self) -> CH1_W<'_>

Bit 1 - Source request for channel 1

pub fn ch2(&mut self) -> CH2_W<'_>

Bit 2 - Source request for channel 2

pub fn ch3(&mut self) -> CH3_W<'_>

Bit 3 - Source request for channel 3

pub fn ch4(&mut self) -> CH4_W<'_>

Bit 4 - Source request for channel 4

pub fn ch5(&mut self) -> CH5_W<'_>

Bit 5 - Source request for channel 5

pub fn ch6(&mut self) -> CH6_W<'_>

Bit 6 - Source request for channel 6

pub fn ch7(&mut self) -> CH7_W<'_>

Bit 7 - Source request for channel 7

impl W<u32, Reg<u32, _SGLREQDSTREG>>

pub fn we_ch0(&mut self) -> WE_CH0_W<'_>

Bit 8 - Source request write enable for channel 0

pub fn we_ch1(&mut self) -> WE_CH1_W<'_>

Bit 9 - Source request write enable for channel 1

pub fn we_ch2(&mut self) -> WE_CH2_W<'_>

Bit 10 - Source request write enable for channel 2

pub fn we_ch3(&mut self) -> WE_CH3_W<'_>

Bit 11 - Source request write enable for channel 3

pub fn we_ch4(&mut self) -> WE_CH4_W<'_>

Bit 12 - Source request write enable for channel 4

pub fn we_ch5(&mut self) -> WE_CH5_W<'_>

Bit 13 - Source request write enable for channel 5

pub fn we_ch6(&mut self) -> WE_CH6_W<'_>

Bit 14 - Source request write enable for channel 6

pub fn we_ch7(&mut self) -> WE_CH7_W<'_>

Bit 15 - Source request write enable for channel 7

pub fn ch0(&mut self) -> CH0_W<'_>

Bit 0 - Source request for channel 0

pub fn ch1(&mut self) -> CH1_W<'_>

Bit 1 - Source request for channel 1

pub fn ch2(&mut self) -> CH2_W<'_>

Bit 2 - Source request for channel 2

pub fn ch3(&mut self) -> CH3_W<'_>

Bit 3 - Source request for channel 3

pub fn ch4(&mut self) -> CH4_W<'_>

Bit 4 - Source request for channel 4

pub fn ch5(&mut self) -> CH5_W<'_>

Bit 5 - Source request for channel 5

pub fn ch6(&mut self) -> CH6_W<'_>

Bit 6 - Source request for channel 6

pub fn ch7(&mut self) -> CH7_W<'_>

Bit 7 - Source request for channel 7

impl W<u32, Reg<u32, _LSTSRCREG>>

pub fn we_ch0(&mut self) -> WE_CH0_W<'_>

Bit 8 - Source last transaction request write enable for channel 0

pub fn we_ch1(&mut self) -> WE_CH1_W<'_>

Bit 9 - Source last transaction request write enable for channel 1

pub fn we_ch2(&mut self) -> WE_CH2_W<'_>

Bit 10 - Source last transaction request write enable for channel 2

pub fn we_ch3(&mut self) -> WE_CH3_W<'_>

Bit 11 - Source last transaction request write enable for channel 3

pub fn we_ch4(&mut self) -> WE_CH4_W<'_>

Bit 12 - Source last transaction request write enable for channel 4

pub fn we_ch5(&mut self) -> WE_CH5_W<'_>

Bit 13 - Source last transaction request write enable for channel 5

pub fn we_ch6(&mut self) -> WE_CH6_W<'_>

Bit 14 - Source last transaction request write enable for channel 6

pub fn we_ch7(&mut self) -> WE_CH7_W<'_>

Bit 15 - Source last transaction request write enable for channel 7

pub fn ch0(&mut self) -> CH0_W<'_>

Bit 0 - Source last request for channel 0

pub fn ch1(&mut self) -> CH1_W<'_>

Bit 1 - Source last request for channel 1

pub fn ch2(&mut self) -> CH2_W<'_>

Bit 2 - Source last request for channel 2

pub fn ch3(&mut self) -> CH3_W<'_>

Bit 3 - Source last request for channel 3

pub fn ch4(&mut self) -> CH4_W<'_>

Bit 4 - Source last request for channel 4

pub fn ch5(&mut self) -> CH5_W<'_>

Bit 5 - Source last request for channel 5

pub fn ch6(&mut self) -> CH6_W<'_>

Bit 6 - Source last request for channel 6

pub fn ch7(&mut self) -> CH7_W<'_>

Bit 7 - Source last request for channel 7

impl W<u32, Reg<u32, _LSTDSTREG>>

pub fn we_ch0(&mut self) -> WE_CH0_W<'_>

Bit 8 - Destination last transaction request write enable for channel 0

pub fn we_ch1(&mut self) -> WE_CH1_W<'_>

Bit 9 - Destination last transaction request write enable for channel 1

pub fn we_ch2(&mut self) -> WE_CH2_W<'_>

Bit 10 - Destination last transaction request write enable for channel 2

pub fn we_ch3(&mut self) -> WE_CH3_W<'_>

Bit 11 - Destination last transaction request write enable for channel 3

pub fn we_ch4(&mut self) -> WE_CH4_W<'_>

Bit 12 - Destination last transaction request write enable for channel 4

pub fn we_ch5(&mut self) -> WE_CH5_W<'_>

Bit 13 - Destination last transaction request write enable for channel 5

pub fn we_ch6(&mut self) -> WE_CH6_W<'_>

Bit 14 - Destination last transaction request write enable for channel 6

pub fn we_ch7(&mut self) -> WE_CH7_W<'_>

Bit 15 - Destination last transaction request write enable for channel 7

pub fn ch0(&mut self) -> CH0_W<'_>

Bit 0 - Destination last request for channel 0

pub fn ch1(&mut self) -> CH1_W<'_>

Bit 1 - Destination last request for channel 1

pub fn ch2(&mut self) -> CH2_W<'_>

Bit 2 - Destination last request for channel 2

pub fn ch3(&mut self) -> CH3_W<'_>

Bit 3 - Destination last request for channel 3

pub fn ch4(&mut self) -> CH4_W<'_>

Bit 4 - Destination last request for channel 4

pub fn ch5(&mut self) -> CH5_W<'_>

Bit 5 - Destination last request for channel 5

pub fn ch6(&mut self) -> CH6_W<'_>

Bit 6 - Destination last request for channel 6

pub fn ch7(&mut self) -> CH7_W<'_>

Bit 7 - Destination last request for channel 7

impl W<u32, Reg<u32, _DMACFGREG>>

pub fn dma_en(&mut self) -> DMA_EN_W<'_>

Bit 0 - GPDMA Enable bit.

impl W<u32, Reg<u32, _CHENREG>>

pub fn we_ch(&mut self) -> WE_CH_W<'_>

Bits 8:15 - Channel enable write enable

pub fn ch(&mut self) -> CH_W<'_>

Bits 0:7 - Enables/Disables the channel

impl W<u32, Reg<u32, _SAR>>

pub fn sar(&mut self) -> SAR_W<'_>

Bits 0:31 - Current Source Address of DMA transfer

impl W<u32, Reg<u32, _DAR>>

pub fn dar(&mut self) -> DAR_W<'_>

Bits 0:31 - Current Destination address of DMA transfer

impl W<u32, Reg<u32, _LLP>>

pub fn loc(&mut self) -> LOC_W<'_>

Bits 2:31 - Starting Address In Memory

impl W<u32, Reg<u32, _CTLL>>

pub fn llp_src_en(&mut self) -> LLP_SRC_EN_W<'_>

Bit 28 - Linked List Pointer for Source Enable

pub fn llp_dst_en(&mut self) -> LLP_DST_EN_W<'_>

Bit 27 - Linked List Pointer for Destination Enable

pub fn tt_fc(&mut self) -> TT_FC_W<'_>

Bits 20:22 - Transfer Type and Flow Control

pub fn dst_scatter_en(&mut self) -> DST_SCATTER_EN_W<'_>

Bit 18 - Destination scatter enable

pub fn src_gather_en(&mut self) -> SRC_GATHER_EN_W<'_>

Bit 17 - Source gather enable

pub fn src_msize(&mut self) -> SRC_MSIZE_W<'_>

Bits 14:16 - Source Burst Transaction Length

pub fn dest_msize(&mut self) -> DEST_MSIZE_W<'_>

Bits 11:13 - Destination Burst Transaction Length

pub fn sinc(&mut self) -> SINC_W<'_>

Bits 9:10 - Source Address Increment

pub fn dinc(&mut self) -> DINC_W<'_>

Bits 7:8 - Destination Address Increment

pub fn src_tr_width(&mut self) -> SRC_TR_WIDTH_W<'_>

Bits 4:6 - Source Transfer Width

pub fn dst_tr_width(&mut self) -> DST_TR_WIDTH_W<'_>

Bits 1:3 - Destination Transfer Width

pub fn int_en(&mut self) -> INT_EN_W<'_>

Bit 0 - Interrupt Enable Bit

impl W<u32, Reg<u32, _CTLH>>

pub fn done(&mut self) -> DONE_W<'_>

Bit 12 - Done bit

pub fn block_ts(&mut self) -> BLOCK_TS_W<'_>

Bits 0:11 - Block Transfer Size

impl W<u32, Reg<u32, _SSTAT>>

pub fn sstat(&mut self) -> SSTAT_W<'_>

Bits 0:31 - Source Status

impl W<u32, Reg<u32, _DSTAT>>

pub fn dstat(&mut self) -> DSTAT_W<'_>

Bits 0:31 - Destination Status

impl W<u32, Reg<u32, _SSTATAR>>

pub fn sstatar(&mut self) -> SSTATAR_W<'_>

Bits 0:31 - Source Status Address

impl W<u32, Reg<u32, _DSTATAR>>

pub fn dstatar(&mut self) -> DSTATAR_W<'_>

Bits 0:31 - Destination Status Address

impl W<u32, Reg<u32, _CFGL>>

pub fn reload_dst(&mut self) -> RELOAD_DST_W<'_>

Bit 31 - Automatic Destination Reload

pub fn reload_src(&mut self) -> RELOAD_SRC_W<'_>

Bit 30 - Automatic Source Reload

pub fn max_abrst(&mut self) -> MAX_ABRST_W<'_>

Bits 20:29 - Maximum AMBA Burst Length

pub fn src_hs_pol(&mut self) -> SRC_HS_POL_W<'_>

Bit 19 - Source Handshaking Interface Polarity

pub fn dst_hs_pol(&mut self) -> DST_HS_POL_W<'_>

Bit 18 - Destination Handshaking Interface Polarity

pub fn lock_b(&mut self) -> LOCK_B_W<'_>

Bit 17 - Bus Lock Bit

pub fn lock_ch(&mut self) -> LOCK_CH_W<'_>

Bit 16 - Channel Lock Bit

pub fn lock_b_l(&mut self) -> LOCK_B_L_W<'_>

Bits 14:15 - Bus Lock Level

pub fn lock_ch_l(&mut self) -> LOCK_CH_L_W<'_>

Bits 12:13 - Channel Lock Level

pub fn hs_sel_src(&mut self) -> HS_SEL_SRC_W<'_>

Bit 11 - Source Software or Hardware Handshaking Select

pub fn hs_sel_dst(&mut self) -> HS_SEL_DST_W<'_>

Bit 10 - Destination Software or Hardware Handshaking Select

pub fn ch_susp(&mut self) -> CH_SUSP_W<'_>

Bit 8 - Channel Suspend

pub fn ch_prior(&mut self) -> CH_PRIOR_W<'_>

Bits 5:7 - Channel priority

impl W<u32, Reg<u32, _CFGH>>

pub fn dest_per(&mut self) -> DEST_PER_W<'_>

Bits 11:14 - Destination Peripheral

pub fn src_per(&mut self) -> SRC_PER_W<'_>

Bits 7:10 - Source Peripheral

pub fn ss_upd_en(&mut self) -> SS_UPD_EN_W<'_>

Bit 6 - Source Status Update Enable

pub fn ds_upd_en(&mut self) -> DS_UPD_EN_W<'_>

Bit 5 - Destination Status Update Enable

pub fn protctl(&mut self) -> PROTCTL_W<'_>

Bits 2:4 - Protection Control

pub fn fifo_mode(&mut self) -> FIFO_MODE_W<'_>

Bit 1 - FIFO Mode Select

pub fn fcmode(&mut self) -> FCMODE_W<'_>

Bit 0 - Flow Control Mode

impl W<u32, Reg<u32, _SGR>>

pub fn sgc(&mut self) -> SGC_W<'_>

Bits 20:31 - Source gather count

pub fn sgi(&mut self) -> SGI_W<'_>

Bits 0:19 - Source gather interval

impl W<u32, Reg<u32, _DSR>>

pub fn dsc(&mut self) -> DSC_W<'_>

Bits 20:31 - Destination scatter count

pub fn dsi(&mut self) -> DSI_W<'_>

Bits 0:19 - Destination scatter interval

impl W<u32, Reg<u32, _SAR>>

pub fn sar(&mut self) -> SAR_W<'_>

Bits 0:31 - Current Source Address of DMA transfer

impl W<u32, Reg<u32, _DAR>>

pub fn dar(&mut self) -> DAR_W<'_>

Bits 0:31 - Current Destination address of DMA transfer

impl W<u32, Reg<u32, _CTLL>>

pub fn tt_fc(&mut self) -> TT_FC_W<'_>

Bits 20:22 - Transfer Type and Flow Control

pub fn src_msize(&mut self) -> SRC_MSIZE_W<'_>

Bits 14:16 - Source Burst Transaction Length

pub fn dest_msize(&mut self) -> DEST_MSIZE_W<'_>

Bits 11:13 - Destination Burst Transaction Length

pub fn sinc(&mut self) -> SINC_W<'_>

Bits 9:10 - Source Address Increment

pub fn dinc(&mut self) -> DINC_W<'_>

Bits 7:8 - Destination Address Increment

pub fn src_tr_width(&mut self) -> SRC_TR_WIDTH_W<'_>

Bits 4:6 - Source Transfer Width

pub fn dst_tr_width(&mut self) -> DST_TR_WIDTH_W<'_>

Bits 1:3 - Destination Transfer Width

pub fn int_en(&mut self) -> INT_EN_W<'_>

Bit 0 - Interrupt Enable Bit

impl W<u32, Reg<u32, _CTLH>>

pub fn done(&mut self) -> DONE_W<'_>

Bit 12 - Done bit

pub fn block_ts(&mut self) -> BLOCK_TS_W<'_>

Bits 0:11 - Block Transfer Size

impl W<u32, Reg<u32, _CFGL>>

pub fn max_abrst(&mut self) -> MAX_ABRST_W<'_>

Bits 20:29 - Maximum AMBA Burst Length

pub fn src_hs_pol(&mut self) -> SRC_HS_POL_W<'_>

Bit 19 - Source Handshaking Interface Polarity

pub fn dst_hs_pol(&mut self) -> DST_HS_POL_W<'_>

Bit 18 - Destination Handshaking Interface Polarity

pub fn lock_b(&mut self) -> LOCK_B_W<'_>

Bit 17 - Bus Lock Bit

pub fn lock_ch(&mut self) -> LOCK_CH_W<'_>

Bit 16 - Channel Lock Bit

pub fn lock_b_l(&mut self) -> LOCK_B_L_W<'_>

Bits 14:15 - Bus Lock Level

pub fn lock_ch_l(&mut self) -> LOCK_CH_L_W<'_>

Bits 12:13 - Channel Lock Level

pub fn hs_sel_src(&mut self) -> HS_SEL_SRC_W<'_>

Bit 11 - Source Software or Hardware Handshaking Select

pub fn hs_sel_dst(&mut self) -> HS_SEL_DST_W<'_>

Bit 10 - Destination Software or Hardware Handshaking Select

pub fn ch_susp(&mut self) -> CH_SUSP_W<'_>

Bit 8 - Channel Suspend

pub fn ch_prior(&mut self) -> CH_PRIOR_W<'_>

Bits 5:7 - Channel priority

impl W<u32, Reg<u32, _CFGH>>

pub fn dest_per(&mut self) -> DEST_PER_W<'_>

Bits 11:14 - Destination Peripheral

pub fn src_per(&mut self) -> SRC_PER_W<'_>

Bits 7:10 - Source Peripheral

pub fn protctl(&mut self) -> PROTCTL_W<'_>

Bits 2:4 - Protection Control

pub fn fifo_mode(&mut self) -> FIFO_MODE_W<'_>

Bit 1 - FIFO Mode Select

pub fn fcmode(&mut self) -> FCMODE_W<'_>

Bit 0 - Flow Control Mode

impl W<u32, Reg<u32, _CLC>>

pub fn disr(&mut self) -> DISR_W<'_>

Bit 0 - Module Disable Request Bit

impl W<u32, Reg<u32, _IR>>

pub fn ir(&mut self) -> IR_W<'_>

Bits 0:31 - Input Register

impl W<u32, Reg<u32, _CFG>>

pub fn cmi(&mut self) -> CMI_W<'_>

Bit 0 - CRC Mismatch Interrupt

pub fn cei(&mut self) -> CEI_W<'_>

Bit 1 - Configuration Error Interrupt

pub fn lei(&mut self) -> LEI_W<'_>

Bit 2 - Length Error Interrupt

pub fn bei(&mut self) -> BEI_W<'_>

Bit 3 - Bus Error Interrupt

pub fn cce(&mut self) -> CCE_W<'_>

Bit 4 - CRC Check Comparison

pub fn alr(&mut self) -> ALR_W<'_>

Bit 5 - Automatic Length Reload

pub fn refin(&mut self) -> REFIN_W<'_>

Bit 8 - IR Byte Wise Reflection

pub fn refout(&mut self) -> REFOUT_W<'_>

Bit 9 - CRC 32-Bit Wise Reflection

pub fn xsel(&mut self) -> XSEL_W<'_>

Bit 10 - Selects the value to be xored with the final CRC

impl W<u32, Reg<u32, _STS>>

pub fn cmf(&mut self) -> CMF_W<'_>

Bit 0 - CRC Mismatch Flag

pub fn cef(&mut self) -> CEF_W<'_>

Bit 1 - Configuration Error Flag

pub fn lef(&mut self) -> LEF_W<'_>

Bit 2 - Length Error Flag

pub fn bef(&mut self) -> BEF_W<'_>

Bit 3 - Bus Error Flag

impl W<u32, Reg<u32, _LENGTH>>

pub fn length(&mut self) -> LENGTH_W<'_>

Bits 0:15 - Message Length Register

impl W<u32, Reg<u32, _CHECK>>

pub fn check(&mut self) -> CHECK_W<'_>

Bits 0:31 - CHECK Register

impl W<u32, Reg<u32, _CRC>>

pub fn crc(&mut self) -> CRC_W<'_>

Bits 0:31 - CRC Register

impl W<u32, Reg<u32, _CTR>>

pub fn fcm(&mut self) -> FCM_W<'_>

Bit 0 - Force CRC Mismatch

pub fn frm_cfg(&mut self) -> FRM_CFG_W<'_>

Bit 1 - Force CFG Register Mismatch

pub fn frm_check(&mut self) -> FRM_CHECK_W<'_>

Bit 2 - Force Check Register Mismatch

impl W<u32, Reg<u32, _STS>>

pub fn werr(&mut self) -> WERR_W<'_>

Bit 0 - Bufferable Write Access Error

impl W<u32, Reg<u32, _FCON>>

pub fn wspflash(&mut self) -> WSPFLASH_W<'_>

Bits 0:3 - Wait States for read access to PFLASH

pub fn wsecpf(&mut self) -> WSECPF_W<'_>

Bit 4 - Wait State for Error Correction of PFLASH

pub fn idle(&mut self) -> IDLE_W<'_>

Bit 13 - Dynamic Flash Idle

pub fn esldis(&mut self) -> ESLDIS_W<'_>

Bit 14 - External Sleep Request Disable

pub fn sleep(&mut self) -> SLEEP_W<'_>

Bit 15 - Flash SLEEP

pub fn dcf(&mut self) -> DCF_W<'_>

Bit 17 - Disable Code Fetch from Flash Memory

pub fn ddf(&mut self) -> DDF_W<'_>

Bit 18 - Disable Any Data Fetch from Flash

pub fn voperm(&mut self) -> VOPERM_W<'_>

Bit 24 - Verify and Operation Error Interrupt Mask

pub fn sqerm(&mut self) -> SQERM_W<'_>

Bit 25 - Command Sequence Error Interrupt Mask

pub fn proerm(&mut self) -> PROERM_W<'_>

Bit 26 - Protection Error Interrupt Mask

pub fn pfsberm(&mut self) -> PFSBERM_W<'_>

Bit 27 - PFLASH Single-Bit Error Interrupt Mask

pub fn pfdberm(&mut self) -> PFDBERM_W<'_>

Bit 29 - PFLASH Double-Bit Error Interrupt Mask

pub fn eobm(&mut self) -> EOBM_W<'_>

Bit 31 - End of Busy Interrupt Mask

impl W<u32, Reg<u32, _MARP>>

pub fn margin(&mut self) -> MARGIN_W<'_>

Bits 0:3 - PFLASH Margin Selection

pub fn trapdis(&mut self) -> TRAPDIS_W<'_>

Bit 15 - PFLASH Double-Bit Error Trap Disable

impl W<u32, Reg<u32, _PCON>>

pub fn ibyp(&mut self) -> IBYP_W<'_>

Bit 0 - Instruction Prefetch Buffer Bypass

pub fn iinv(&mut self) -> IINV_W<'_>

Bit 1 - Instruction Prefetch Buffer Invalidate

pub fn dbyp(&mut self) -> DBYP_W<'_>

Bit 4 - Data Buffer Bypass

impl W<u32, Reg<u32, _CTR>>

pub fn enb(&mut self) -> ENB_W<'_>

Bit 0 - Enable

pub fn pre(&mut self) -> PRE_W<'_>

Bit 1 - Pre-warning

pub fn dsp(&mut self) -> DSP_W<'_>

Bit 4 - Debug Suspend

pub fn spw(&mut self) -> SPW_W<'_>

Bits 8:15 - Service Indication Pulse Width

impl W<u32, Reg<u32, _SRV>>

pub fn srv(&mut self) -> SRV_W<'_>

Bits 0:31 - Service

impl W<u32, Reg<u32, _WLB>>

pub fn wlb(&mut self) -> WLB_W<'_>

Bits 0:31 - Window Lower Bound

impl W<u32, Reg<u32, _WUB>>

pub fn wub(&mut self) -> WUB_W<'_>

Bits 0:31 - Window Upper Bound

impl W<u32, Reg<u32, _WDTCLR>>

pub fn almc(&mut self) -> ALMC_W<'_>

Bit 0 - Pre-warning Alarm

impl W<u32, Reg<u32, _CTR>>

pub fn enb(&mut self) -> ENB_W<'_>

Bit 0 - RTC Module Enable

pub fn tae(&mut self) -> TAE_W<'_>

Bit 2 - Timer Alarm Enable for Hibernation Wake-up

pub fn esec(&mut self) -> ESEC_W<'_>

Bit 8 - Enable Seconds Comparison for Hibernation Wake-up

pub fn emic(&mut self) -> EMIC_W<'_>

Bit 9 - Enable Minutes Comparison for Hibernation Wake-up

pub fn ehoc(&mut self) -> EHOC_W<'_>

Bit 10 - Enable Hours Comparison for Hibernation Wake-up

pub fn edac(&mut self) -> EDAC_W<'_>

Bit 11 - Enable Days Comparison for Hibernation Wake-up

pub fn emoc(&mut self) -> EMOC_W<'_>

Bit 13 - Enable Months Comparison for Hibernation Wake-up

pub fn eyec(&mut self) -> EYEC_W<'_>

Bit 14 - Enable Years Comparison for Hibernation Wake-up

pub fn div(&mut self) -> DIV_W<'_>

Bits 16:31 - RTC Clock Divider Value

impl W<u32, Reg<u32, _MSKSR>>

pub fn mpse(&mut self) -> MPSE_W<'_>

Bit 0 - Periodic Seconds Interrupt Mask

pub fn mpmi(&mut self) -> MPMI_W<'_>

Bit 1 - Periodic Minutes Interrupt Mask

pub fn mpho(&mut self) -> MPHO_W<'_>

Bit 2 - Periodic Hours Interrupt Mask

pub fn mpda(&mut self) -> MPDA_W<'_>

Bit 3 - Periodic Days Interrupt Mask

pub fn mpmo(&mut self) -> MPMO_W<'_>

Bit 5 - Periodic Months Interrupt Mask

pub fn mpye(&mut self) -> MPYE_W<'_>

Bit 6 - Periodic Years Interrupt Mask

pub fn mai(&mut self) -> MAI_W<'_>

Bit 8 - Alarm Interrupt Mask

impl W<u32, Reg<u32, _CLRSR>>

pub fn rpse(&mut self) -> RPSE_W<'_>

Bit 0 - Periodic Seconds Interrupt Clear

pub fn rpmi(&mut self) -> RPMI_W<'_>

Bit 1 - Periodic Minutes Interrupt Clear

pub fn rpho(&mut self) -> RPHO_W<'_>

Bit 2 - Periodic Hours Interrupt Clear

pub fn rpda(&mut self) -> RPDA_W<'_>

Bit 3 - Periodic Days Interrupt Clear

pub fn rpmo(&mut self) -> RPMO_W<'_>

Bit 5 - Periodic Months Interrupt Clear

pub fn rpye(&mut self) -> RPYE_W<'_>

Bit 6 - Periodic Years Interrupt Clear

pub fn rai(&mut self) -> RAI_W<'_>

Bit 8 - Alarm Interrupt Clear

impl W<u32, Reg<u32, _ATIM0>>

pub fn ase(&mut self) -> ASE_W<'_>

Bits 0:5 - Alarm Seconds Compare Value

pub fn ami(&mut self) -> AMI_W<'_>

Bits 8:13 - Alarm Minutes Compare Value

pub fn aho(&mut self) -> AHO_W<'_>

Bits 16:20 - Alarm Hours Compare Value

pub fn ada(&mut self) -> ADA_W<'_>

Bits 24:28 - Alarm Days Compare Value

impl W<u32, Reg<u32, _ATIM1>>

pub fn amo(&mut self) -> AMO_W<'_>

Bits 8:11 - Alarm Month Compare Value

pub fn aye(&mut self) -> AYE_W<'_>

Bits 16:31 - Alarm Year Compare Value

impl W<u32, Reg<u32, _TIM0>>

pub fn se(&mut self) -> SE_W<'_>

Bits 0:5 - Seconds Time Value

pub fn mi(&mut self) -> MI_W<'_>

Bits 8:13 - Minutes Time Value

pub fn ho(&mut self) -> HO_W<'_>

Bits 16:20 - Hours Time Value

pub fn da(&mut self) -> DA_W<'_>

Bits 24:28 - Days Time Value

impl W<u32, Reg<u32, _TIM1>>

pub fn dawe(&mut self) -> DAWE_W<'_>

Bits 0:2 - Days of Week Time Value

pub fn mo(&mut self) -> MO_W<'_>

Bits 8:11 - Month Time Value

pub fn ye(&mut self) -> YE_W<'_>

Bits 16:31 - Year Time Value

impl W<u32, Reg<u32, _CLKSET>>

pub fn usbcen(&mut self) -> USBCEN_W<'_>

Bit 0 - USB Clock Enable

pub fn ccucen(&mut self) -> CCUCEN_W<'_>

Bit 4 - CCU Clock Enable

pub fn wdtcen(&mut self) -> WDTCEN_W<'_>

Bit 5 - WDT Clock Enable

impl W<u32, Reg<u32, _CLKCLR>>

pub fn usbcdi(&mut self) -> USBCDI_W<'_>

Bit 0 - USB Clock Disable

pub fn ccucdi(&mut self) -> CCUCDI_W<'_>

Bit 4 - CCU Clock Disable

pub fn wdtcdi(&mut self) -> WDTCDI_W<'_>

Bit 5 - WDT Clock Disable

impl W<u32, Reg<u32, _SYSCLKCR>>

pub fn sysdiv(&mut self) -> SYSDIV_W<'_>

Bits 0:7 - System Clock Division Value

pub fn syssel(&mut self) -> SYSSEL_W<'_>

Bit 16 - System Clock Selection Value

impl W<u32, Reg<u32, _CPUCLKCR>>

pub fn cpudiv(&mut self) -> CPUDIV_W<'_>

Bit 0 - CPU Clock Divider Enable

impl W<u32, Reg<u32, _PBCLKCR>>

pub fn pbdiv(&mut self) -> PBDIV_W<'_>

Bit 0 - PB Clock Divider Enable

impl W<u32, Reg<u32, _USBCLKCR>>

pub fn usbdiv(&mut self) -> USBDIV_W<'_>

Bits 0:2 - USB Clock Divider Value

pub fn usbsel(&mut self) -> USBSEL_W<'_>

Bit 16 - USB Clock Selection Value

impl W<u32, Reg<u32, _CCUCLKCR>>

pub fn ccudiv(&mut self) -> CCUDIV_W<'_>

Bit 0 - CCU Clock Divider Enable

impl W<u32, Reg<u32, _WDTCLKCR>>

pub fn wdtdiv(&mut self) -> WDTDIV_W<'_>

Bits 0:7 - WDT Clock Divider Value

pub fn wdtsel(&mut self) -> WDTSEL_W<'_>

Bits 16:17 - WDT Clock Selection Value

impl W<u32, Reg<u32, _EXTCLKCR>>

pub fn ecksel(&mut self) -> ECKSEL_W<'_>

Bits 0:2 - External Clock Selection Value

pub fn eckdiv(&mut self) -> ECKDIV_W<'_>

Bits 16:24 - External Clock Divider Value

impl W<u32, Reg<u32, _MLINKCLKCR>>

pub fn sysdiv(&mut self) -> SYSDIV_W<'_>

Bits 0:7 - System Clock Division Value

pub fn syssel(&mut self) -> SYSSEL_W<'_>

Bit 8 - System Clock Selection Value

pub fn cpudiv(&mut self) -> CPUDIV_W<'_>

Bit 10 - CPU Clock Divider Enable

pub fn pbdiv(&mut self) -> PBDIV_W<'_>

Bit 12 - PB Clock Divider Enable

pub fn ccudiv(&mut self) -> CCUDIV_W<'_>

Bit 14 - CCU Clock Divider Enable

pub fn wdtdiv(&mut self) -> WDTDIV_W<'_>

Bits 16:23 - WDT Clock Divider Value

pub fn wdtsel(&mut self) -> WDTSEL_W<'_>

Bits 24:25 - WDT Clock Selection Value

impl W<u32, Reg<u32, _SLEEPCR>>

pub fn syssel(&mut self) -> SYSSEL_W<'_>

Bit 0 - System Clock Selection Value

pub fn usbcr(&mut self) -> USBCR_W<'_>

Bit 16 - USB Clock Control

pub fn ccucr(&mut self) -> CCUCR_W<'_>

Bit 20 - CCU Clock Control

pub fn wdtcr(&mut self) -> WDTCR_W<'_>

Bit 21 - WDT Clock Control

impl W<u32, Reg<u32, _DSLEEPCR>>

pub fn syssel(&mut self) -> SYSSEL_W<'_>

Bit 0 - System Clock Selection Value

pub fn fpdn(&mut self) -> FPDN_W<'_>

Bit 11 - Flash Power Down

pub fn pllpdn(&mut self) -> PLLPDN_W<'_>

Bit 12 - PLL Power Down

pub fn vcopdn(&mut self) -> VCOPDN_W<'_>

Bit 13 - VCO Power Down

pub fn usbcr(&mut self) -> USBCR_W<'_>

Bit 16 - USB Clock Control

pub fn ccucr(&mut self) -> CCUCR_W<'_>

Bit 20 - CCU Clock Control

pub fn wdtcr(&mut self) -> WDTCR_W<'_>

Bit 21 - WDT Clock Control

impl W<u32, Reg<u32, _CGATSET0>>

pub fn vadc(&mut self) -> VADC_W<'_>

Bit 0 - VADC Gating Set

pub fn ccu40(&mut self) -> CCU40_W<'_>

Bit 2 - CCU40 Gating Set

pub fn ccu41(&mut self) -> CCU41_W<'_>

Bit 3 - CCU41 Gating Set

pub fn ccu80(&mut self) -> CCU80_W<'_>

Bit 7 - CCU80 Gating Set

pub fn posif0(&mut self) -> POSIF0_W<'_>

Bit 9 - POSIF0 Gating Set

pub fn usic0(&mut self) -> USIC0_W<'_>

Bit 11 - USIC0 Gating Set

pub fn eru1(&mut self) -> ERU1_W<'_>

Bit 16 - ERU1 Gating Set

pub fn hrpwm0(&mut self) -> HRPWM0_W<'_>

Bit 23 - HRPWM0 Gating Set

impl W<u32, Reg<u32, _CGATCLR0>>

pub fn vadc(&mut self) -> VADC_W<'_>

Bit 0 - VADC Gating Clear

pub fn ccu40(&mut self) -> CCU40_W<'_>

Bit 2 - CCU40 Gating Clear

pub fn ccu41(&mut self) -> CCU41_W<'_>

Bit 3 - CCU41 Gating Clear

pub fn ccu80(&mut self) -> CCU80_W<'_>

Bit 7 - CCU80 Gating Clear

pub fn posif0(&mut self) -> POSIF0_W<'_>

Bit 9 - POSIF0 Gating Clear

pub fn usic0(&mut self) -> USIC0_W<'_>

Bit 11 - USIC0 Gating Clear

pub fn eru1(&mut self) -> ERU1_W<'_>

Bit 16 - ERU1 Gating Clear

pub fn hrpwm0(&mut self) -> HRPWM0_W<'_>

Bit 23 - HRPWM0 Gating Clear

impl W<u32, Reg<u32, _CGATSET1>>

pub fn ledtscu0(&mut self) -> LEDTSCU0_W<'_>

Bit 3 - LEDTS Gating Set

pub fn mcan0(&mut self) -> MCAN0_W<'_>

Bit 4 - MultiCAN Gating Set

pub fn dac(&mut self) -> DAC_W<'_>

Bit 5 - DAC Gating Set

pub fn usic1(&mut self) -> USIC1_W<'_>

Bit 7 - USIC1 Gating Set

pub fn pports(&mut self) -> PPORTS_W<'_>

Bit 9 - PORTS Gating Set

impl W<u32, Reg<u32, _CGATCLR1>>

pub fn ledtscu0(&mut self) -> LEDTSCU0_W<'_>

Bit 3 - LEDTS Gating Clear

pub fn mcan0(&mut self) -> MCAN0_W<'_>

Bit 4 - MultiCAN Gating Clear

pub fn dac(&mut self) -> DAC_W<'_>

Bit 5 - DAC Gating Clear

pub fn usic1(&mut self) -> USIC1_W<'_>

Bit 7 - USIC1 Gating Clear

pub fn pports(&mut self) -> PPORTS_W<'_>

Bit 9 - PORTS Gating Clear

impl W<u32, Reg<u32, _CGATSET2>>

pub fn wdt(&mut self) -> WDT_W<'_>

Bit 1 - WDT Gating Set

pub fn dma0(&mut self) -> DMA0_W<'_>

Bit 4 - DMA0 Gating Set

pub fn fce(&mut self) -> FCE_W<'_>

Bit 6 - FCE Gating Set

pub fn usb(&mut self) -> USB_W<'_>

Bit 7 - USB Gating Set

impl W<u32, Reg<u32, _CGATCLR2>>

pub fn wdt(&mut self) -> WDT_W<'_>

Bit 1 - WDT Gating Clear

pub fn dma0(&mut self) -> DMA0_W<'_>

Bit 4 - DMA0 Gating Clear

pub fn fce(&mut self) -> FCE_W<'_>

Bit 6 - FCE Gating Clear

pub fn usb(&mut self) -> USB_W<'_>

Bit 7 - USB Gating Clear

impl W<u32, Reg<u32, _OSCHPCTRL>>

pub fn x1den(&mut self) -> X1DEN_W<'_>

Bit 0 - XTAL1 Data Enable

pub fn shby(&mut self) -> SHBY_W<'_>

Bit 1 - Shaper Bypass

pub fn mode(&mut self) -> MODE_W<'_>

Bits 4:5 - Oscillator Mode

pub fn oscval(&mut self) -> OSCVAL_W<'_>

Bits 16:19 - OSC Frequency Value

impl W<u32, Reg<u32, _CLKCALCONST>>

pub fn calibconst(&mut self) -> CALIBCONST_W<'_>

Bits 0:3 - Clock Calibration Constant Value

impl W<u32, Reg<u32, _PLLCON0>>

pub fn vcobyp(&mut self) -> VCOBYP_W<'_>

Bit 0 - VCO Bypass

pub fn vcopwd(&mut self) -> VCOPWD_W<'_>

Bit 1 - VCO Power Saving Mode

pub fn vcotr(&mut self) -> VCOTR_W<'_>

Bit 2 - VCO Trim Control

pub fn findis(&mut self) -> FINDIS_W<'_>

Bit 4 - Disconnect Oscillator from VCO

pub fn oscdiscdis(&mut self) -> OSCDISCDIS_W<'_>

Bit 6 - Oscillator Disconnect Disable

pub fn pllpwd(&mut self) -> PLLPWD_W<'_>

Bit 16 - PLL Power Saving Mode

pub fn oscres(&mut self) -> OSCRES_W<'_>

Bit 17 - Oscillator Watchdog Reset

pub fn resld(&mut self) -> RESLD_W<'_>

Bit 18 - Restart VCO Lock Detection

pub fn aotren(&mut self) -> AOTREN_W<'_>

Bit 19 - Automatic Oscillator Calibration Enable

pub fn fotr(&mut self) -> FOTR_W<'_>

Bit 20 - Factory Oscillator Calibration

impl W<u32, Reg<u32, _PLLCON1>>

pub fn k1div(&mut self) -> K1DIV_W<'_>

Bits 0:6 - K1-Divider Value

pub fn ndiv(&mut self) -> NDIV_W<'_>

Bits 8:14 - N-Divider Value

pub fn k2div(&mut self) -> K2DIV_W<'_>

Bits 16:22 - K2-Divider Value

pub fn pdiv(&mut self) -> PDIV_W<'_>

Bits 24:27 - P-Divider Value

impl W<u32, Reg<u32, _PLLCON2>>

pub fn pinsel(&mut self) -> PINSEL_W<'_>

Bit 0 - P-Divider Input Selection

pub fn k1insel(&mut self) -> K1INSEL_W<'_>

Bit 8 - K1-Divider Input Selection

impl W<u32, Reg<u32, _USBPLLCON>>

pub fn vcobyp(&mut self) -> VCOBYP_W<'_>

Bit 0 - VCO Bypass

pub fn vcopwd(&mut self) -> VCOPWD_W<'_>

Bit 1 - VCO Power Saving Mode

pub fn vcotr(&mut self) -> VCOTR_W<'_>

Bit 2 - VCO Trim Control

pub fn findis(&mut self) -> FINDIS_W<'_>

Bit 4 - Disconnect Oscillator from VCO

pub fn oscdiscdis(&mut self) -> OSCDISCDIS_W<'_>

Bit 6 - Oscillator Disconnect Disable

pub fn ndiv(&mut self) -> NDIV_W<'_>

Bits 8:14 - N-Divider Value

pub fn pllpwd(&mut self) -> PLLPWD_W<'_>

Bit 16 - PLL Power Saving Mode

pub fn resld(&mut self) -> RESLD_W<'_>

Bit 18 - Restart VCO Lock Detection

pub fn pdiv(&mut self) -> PDIV_W<'_>

Bits 24:27 - P-Divider Value

impl W<u32, Reg<u32, _STCON>>

pub fn swcon(&mut self) -> SWCON_W<'_>

Bits 8:11 - SW Configuration

impl W<u32, Reg<u32, _GPR0>>

pub fn dat(&mut self) -> DAT_W<'_>

Bits 0:31 - User Data

impl W<u32, Reg<u32, _GPR1>>

pub fn dat(&mut self) -> DAT_W<'_>

Bits 0:31 - User Data

impl W<u32, Reg<u32, _CCUCON>>

pub fn gsc40(&mut self) -> GSC40_W<'_>

Bit 0 - Global Start Control CCU40

pub fn gsc41(&mut self) -> GSC41_W<'_>

Bit 1 - Global Start Control CCU41

pub fn gsc80(&mut self) -> GSC80_W<'_>

Bit 8 - Global Start Control CCU80

pub fn gshr0(&mut self) -> GSHR0_W<'_>

Bit 24 - Global Start Control HRPWM0

impl W<u32, Reg<u32, _DTSCON>>

pub fn pwd(&mut self) -> PWD_W<'_>

Bit 0 - Sensor Power Down

pub fn start(&mut self) -> START_W<'_>

Bit 1 - Sensor Measurement Start

pub fn offset(&mut self) -> OFFSET_W<'_>

Bits 4:10 - Offset Calibration Value

pub fn gain(&mut self) -> GAIN_W<'_>

Bits 11:16 - Gain Calibration Value

pub fn reftrim(&mut self) -> REFTRIM_W<'_>

Bits 17:19 - Reference Trim Calibration Value

pub fn bgtrim(&mut self) -> BGTRIM_W<'_>

Bits 20:23 - Bandgap Trim Calibration Value

impl W<u32, Reg<u32, _G0ORCEN>>

pub fn enorc6(&mut self) -> ENORC6_W<'_>

Bit 6 - Enable Out of Range Comparator, Channel 6

pub fn enorc7(&mut self) -> ENORC7_W<'_>

Bit 7 - Enable Out of Range Comparator, Channel 7

impl W<u32, Reg<u32, _G1ORCEN>>

pub fn enorc6(&mut self) -> ENORC6_W<'_>

Bit 6 - Enable Out of Range Comparator, Channel 6

pub fn enorc7(&mut self) -> ENORC7_W<'_>

Bit 7 - Enable Out of Range Comparator, Channel 7

impl W<u32, Reg<u32, _DTEMPLIM>>

pub fn lower(&mut self) -> LOWER_W<'_>

Bits 0:9 - Lower Limit

pub fn upper(&mut self) -> UPPER_W<'_>

Bits 16:25 - Upper Limit

impl W<u32, Reg<u32, _RMACR>>

pub fn rdwr(&mut self) -> RDWR_W<'_>

Bit 0 - Hibernate Retention Memory Register Update Control

pub fn addr(&mut self) -> ADDR_W<'_>

Bits 16:19 - Hibernate Retention Memory Register Address Select

impl W<u32, Reg<u32, _RMDATA>>

pub fn data(&mut self) -> DATA_W<'_>

Bits 0:31 - Hibernate Retention Memory Data

impl W<u32, Reg<u32, _MIRRALLREQ>>

pub fn req(&mut self) -> REQ_W<'_>

Bit 0 - Mirror All Execution Request

impl W<u32, Reg<u32, _SRMSK>>

pub fn prwarn(&mut self) -> PRWARN_W<'_>

Bit 0 - WDT pre-warning Interrupt Mask

pub fn pi(&mut self) -> PI_W<'_>

Bit 1 - RTC Periodic Interrupt Mask

pub fn ai(&mut self) -> AI_W<'_>

Bit 2 - RTC Alarm Interrupt Mask

pub fn dlrovr(&mut self) -> DLROVR_W<'_>

Bit 3 - DLR Request Overrun Interrupt Mask

pub fn lpaccr(&mut self) -> LPACCR_W<'_>

Bit 6 - LPACLR Mirror Register Update Interrupt Mask

pub fn lpacth0(&mut self) -> LPACTH0_W<'_>

Bit 7 - LPACTH0 Mirror Register Update Interrupt Mask

pub fn lpacth1(&mut self) -> LPACTH1_W<'_>

Bit 8 - LPACTH1 Mirror Register Update Interrupt Mask

pub fn lpacst(&mut self) -> LPACST_W<'_>

Bit 9 - LPACST Mirror Register Update Interrupt Mask

pub fn lpacclr(&mut self) -> LPACCLR_W<'_>

Bit 10 - LPACCLR Mirror Register Update Interrupt Mask

pub fn lpacset(&mut self) -> LPACSET_W<'_>

Bit 11 - LPACSET Mirror Register Update Interrupt Mask

pub fn hintst(&mut self) -> HINTST_W<'_>

Bit 12 - HINTST Mirror Register Update Interrupt Mask

pub fn hintclr(&mut self) -> HINTCLR_W<'_>

Bit 13 - HINTCLR Mirror Register Update Interrupt Mask

pub fn hintset(&mut self) -> HINTSET_W<'_>

Bit 14 - HINTSET Mirror Register Update Interrupt Mask

pub fn hdclr(&mut self) -> HDCLR_W<'_>

Bit 17 - HDCLR Mirror Register Update Mask

pub fn hdset(&mut self) -> HDSET_W<'_>

Bit 18 - HDSET Mirror Register Update Mask

pub fn hdcr(&mut self) -> HDCR_W<'_>

Bit 19 - HDCR Mirror Register Update Mask

pub fn oscsictrl(&mut self) -> OSCSICTRL_W<'_>

Bit 21 - OSCSICTRL Mirror Register Update Mask

pub fn osculctrl(&mut self) -> OSCULCTRL_W<'_>

Bit 23 - OSCULCTRL Mirror Register Update Mask

pub fn rtc_ctr(&mut self) -> RTC_CTR_W<'_>

Bit 24 - RTC CTR Mirror Register Update Mask

pub fn rtc_atim0(&mut self) -> RTC_ATIM0_W<'_>

Bit 25 - RTC ATIM0 Mirror Register Update Mask

pub fn rtc_atim1(&mut self) -> RTC_ATIM1_W<'_>

Bit 26 - RTC ATIM1 Mirror Register Update Mask

pub fn rtc_tim0(&mut self) -> RTC_TIM0_W<'_>

Bit 27 - RTC TIM0 Mirror Register Update Mask

pub fn rtc_tim1(&mut self) -> RTC_TIM1_W<'_>

Bit 28 - RTC TIM1 Mirror Register Update Mask

pub fn rmx(&mut self) -> RMX_W<'_>

Bit 29 - Retention Memory Mirror Register Update Mask

impl W<u32, Reg<u32, _SRCLR>>

pub fn prwarn(&mut self) -> PRWARN_W<'_>

Bit 0 - WDT pre-warning Interrupt Clear

pub fn pi(&mut self) -> PI_W<'_>

Bit 1 - RTC Periodic Interrupt Clear

pub fn ai(&mut self) -> AI_W<'_>

Bit 2 - RTC Alarm Interrupt Clear

pub fn dlrovr(&mut self) -> DLROVR_W<'_>

Bit 3 - DLR Request Overrun Interrupt clear

pub fn lpaccr(&mut self) -> LPACCR_W<'_>

Bit 6 - LPACLR Mirror Register Update Interrupt Clear

pub fn lpacth0(&mut self) -> LPACTH0_W<'_>

Bit 7 - LPACTH0 Mirror Register Update Interrupt Clear

pub fn lpacth1(&mut self) -> LPACTH1_W<'_>

Bit 8 - LPACTH1 Mirror Register Update Interrupt Clear

pub fn lpacst(&mut self) -> LPACST_W<'_>

Bit 9 - LPACST Mirror Register Update Interrupt Clear

pub fn lpacclr(&mut self) -> LPACCLR_W<'_>

Bit 10 - LPACCLR Mirror Register Update Interrupt Clear

pub fn lpacset(&mut self) -> LPACSET_W<'_>

Bit 11 - LPACSET Mirror Register Update Interrupt Clear

pub fn hintst(&mut self) -> HINTST_W<'_>

Bit 12 - HINTST Mirror Register Update Interrupt Clear

pub fn hintclr(&mut self) -> HINTCLR_W<'_>

Bit 13 - HINTCLR Mirror Register Update Interrupt Clear

pub fn hintset(&mut self) -> HINTSET_W<'_>

Bit 14 - HINTSET Mirror Register Update Interrupt Clear

pub fn hdclr(&mut self) -> HDCLR_W<'_>

Bit 17 - HDCLR Mirror Register Update Clear

pub fn hdset(&mut self) -> HDSET_W<'_>

Bit 18 - HDSET Mirror Register Update Clear

pub fn hdcr(&mut self) -> HDCR_W<'_>

Bit 19 - HDCR Mirror Register Update Clear

pub fn oscsictrl(&mut self) -> OSCSICTRL_W<'_>

Bit 21 - OSCSICTRL Mirror Register Update Clear

pub fn osculctrl(&mut self) -> OSCULCTRL_W<'_>

Bit 23 - OSCULCTRL Mirror Register Update Clear

pub fn rtc_ctr(&mut self) -> RTC_CTR_W<'_>

Bit 24 - RTC CTR Mirror Register Update Clear

pub fn rtc_atim0(&mut self) -> RTC_ATIM0_W<'_>

Bit 25 - RTC ATIM0 Mirror Register Update Clear

pub fn rtc_atim1(&mut self) -> RTC_ATIM1_W<'_>

Bit 26 - RTC ATIM1 Mirror Register Update Clear

pub fn rtc_tim0(&mut self) -> RTC_TIM0_W<'_>

Bit 27 - RTC TIM0 Mirror Register Update Clear

pub fn rtc_tim1(&mut self) -> RTC_TIM1_W<'_>

Bit 28 - RTC TIM1 Mirror Register Update Clear

pub fn rmx(&mut self) -> RMX_W<'_>

Bit 29 - Retention Memory Mirror Register Update Clear

impl W<u32, Reg<u32, _SRSET>>

pub fn prwarn(&mut self) -> PRWARN_W<'_>

Bit 0 - WDT pre-warning Interrupt Set

pub fn pi(&mut self) -> PI_W<'_>

Bit 1 - RTC Periodic Interrupt Set

pub fn ai(&mut self) -> AI_W<'_>

Bit 2 - RTC Alarm Interrupt Set

pub fn dlrovr(&mut self) -> DLROVR_W<'_>

Bit 3 - DLR Request Overrun Interrupt Set

pub fn lpaccr(&mut self) -> LPACCR_W<'_>

Bit 6 - LPACLR Mirror Register Update Interrupt Set

pub fn lpacth0(&mut self) -> LPACTH0_W<'_>

Bit 7 - LPACTH0 Mirror Register Update Interrupt Set

pub fn lpacth1(&mut self) -> LPACTH1_W<'_>

Bit 8 - LPACTH1 Mirror Register Update Interrupt Set

pub fn lpacst(&mut self) -> LPACST_W<'_>

Bit 9 - LPACST Mirror Register Update Interrupt Set

pub fn lpacclr(&mut self) -> LPACCLR_W<'_>

Bit 10 - LPACCLR Mirror Register Update Interrupt Set

pub fn lpacset(&mut self) -> LPACSET_W<'_>

Bit 11 - LPACSET Mirror Register Update Interrupt Set

pub fn hintst(&mut self) -> HINTST_W<'_>

Bit 12 - HINTST Mirror Register Update Interrupt Set

pub fn hintclr(&mut self) -> HINTCLR_W<'_>

Bit 13 - HINTCLR Mirror Register Update Interrupt Set

pub fn hintset(&mut self) -> HINTSET_W<'_>

Bit 14 - HINTSET Mirror Register Update Interrupt Set

pub fn hdcrclr(&mut self) -> HDCRCLR_W<'_>

Bit 17 - HDCRCLR Mirror Register Update Set

pub fn hdcrset(&mut self) -> HDCRSET_W<'_>

Bit 18 - HDCRSET Mirror Register Update Set

pub fn hdcr(&mut self) -> HDCR_W<'_>

Bit 19 - HDCR Mirror Register Update Set

pub fn oscsictrl(&mut self) -> OSCSICTRL_W<'_>

Bit 21 - OSCSICTRL Mirror Register Update Set

pub fn osculctrl(&mut self) -> OSCULCTRL_W<'_>

Bit 23 - OSCULCTRL Mirror Register Update Set

pub fn rtc_ctr(&mut self) -> RTC_CTR_W<'_>

Bit 24 - RTC CTR Mirror Register Update Set

pub fn rtc_atim0(&mut self) -> RTC_ATIM0_W<'_>

Bit 25 - RTC ATIM0 Mirror Register Update Set

pub fn rtc_atim1(&mut self) -> RTC_ATIM1_W<'_>

Bit 26 - RTC ATIM1 Mirror Register Update Set

pub fn rtc_tim0(&mut self) -> RTC_TIM0_W<'_>

Bit 27 - RTC TIM0 Mirror Register Update Set

pub fn rtc_tim1(&mut self) -> RTC_TIM1_W<'_>

Bit 28 - RTC TIM1 Mirror Register Update Set

pub fn rmx(&mut self) -> RMX_W<'_>

Bit 29 - Retention Memory Mirror Register Update Set

impl W<u32, Reg<u32, _NMIREQEN>>

pub fn prwarn(&mut self) -> PRWARN_W<'_>

Bit 0 - Promote Pre-Warning Interrupt Request to NMI Request

pub fn pi(&mut self) -> PI_W<'_>

Bit 1 - Promote RTC Periodic Interrupt request to NMI Request

pub fn ai(&mut self) -> AI_W<'_>

Bit 2 - Promote RTC Alarm Interrupt Request to NMI Request

pub fn eru00(&mut self) -> ERU00_W<'_>

Bit 16 - Promote Channel 0 Interrupt of ERU0 Request to NMI Request

pub fn eru01(&mut self) -> ERU01_W<'_>

Bit 17 - Promote Channel 1 Interrupt of ERU0 Request to NMI Request

pub fn eru02(&mut self) -> ERU02_W<'_>

Bit 18 - Promote Channel 2 Interrupt of ERU0 Request to NMI Request

pub fn eru03(&mut self) -> ERU03_W<'_>

Bit 19 - Promote Channel 3 Interrupt of ERU0 Request to NMI Request

impl W<u32, Reg<u32, _PEEN>>

pub fn peenps(&mut self) -> PEENPS_W<'_>

Bit 0 - Parity Error Enable for PSRAM

pub fn peends1(&mut self) -> PEENDS1_W<'_>

Bit 1 - Parity Error Enable for DSRAM1

pub fn peenu0(&mut self) -> PEENU0_W<'_>

Bit 8 - Parity Error Enable for USIC0 Memory

pub fn peenu1(&mut self) -> PEENU1_W<'_>

Bit 9 - Parity Error Enable for USIC1 Memory

pub fn peenmc(&mut self) -> PEENMC_W<'_>

Bit 12 - Parity Error Enable for MultiCAN Memory

pub fn peenpprf(&mut self) -> PEENPPRF_W<'_>

Bit 13 - Parity Error Enable for PMU Prefetch Memory

pub fn peenusb(&mut self) -> PEENUSB_W<'_>

Bit 16 - Parity Error Enable for USB Memory

impl W<u32, Reg<u32, _MCHKCON>>

pub fn selps(&mut self) -> SELPS_W<'_>

Bit 0 - Select Memory Check for PSRAM

pub fn selds1(&mut self) -> SELDS1_W<'_>

Bit 1 - Select Memory Check for DSRAM1

pub fn usic0dra(&mut self) -> USIC0DRA_W<'_>

Bit 8 - Select Memory Check for USIC0

pub fn usic1dra(&mut self) -> USIC1DRA_W<'_>

Bit 9 - Select Memory Check for USIC1

pub fn mcandra(&mut self) -> MCANDRA_W<'_>

Bit 12 - Select Memory Check for MultiCAN

pub fn pprfdra(&mut self) -> PPRFDRA_W<'_>

Bit 13 - Select Memory Check for PMU

pub fn selusb(&mut self) -> SELUSB_W<'_>

Bit 16 - Select Memory Check for USB SRAM

impl W<u32, Reg<u32, _PETE>>

pub fn peteps(&mut self) -> PETEPS_W<'_>

Bit 0 - Parity Error Trap Enable for PSRAM

pub fn peteds1(&mut self) -> PETEDS1_W<'_>

Bit 1 - Parity Error Trap Enable for DSRAM1

pub fn peteu0(&mut self) -> PETEU0_W<'_>

Bit 8 - Parity Error Trap Enable for USIC0 Memory

pub fn peteu1(&mut self) -> PETEU1_W<'_>

Bit 9 - Parity Error Trap Enable for USIC1 Memory

pub fn petemc(&mut self) -> PETEMC_W<'_>

Bit 12 - Parity Error Trap Enable for MultiCAN Memory

pub fn petepprf(&mut self) -> PETEPPRF_W<'_>

Bit 13 - Parity Error Trap Enable for PMU Prefetch Memory

pub fn peteusb(&mut self) -> PETEUSB_W<'_>

Bit 16 - Parity Error Trap Enable for USB Memory

impl W<u32, Reg<u32, _PERSTEN>>

pub fn rsen(&mut self) -> RSEN_W<'_>

Bit 0 - System Reset Enable upon Parity Error Trap

impl W<u32, Reg<u32, _PEFLAG>>

pub fn pefps(&mut self) -> PEFPS_W<'_>

Bit 0 - Parity Error Flag for PSRAM

pub fn pefds1(&mut self) -> PEFDS1_W<'_>

Bit 1 - Parity Error Flag for DSRAM1

pub fn pefu0(&mut self) -> PEFU0_W<'_>

Bit 8 - Parity Error Flag for USIC0 Memory

pub fn pefu1(&mut self) -> PEFU1_W<'_>

Bit 9 - Parity Error Flag for USIC1 Memory

pub fn pefmc(&mut self) -> PEFMC_W<'_>

Bit 12 - Parity Error Flag for MultiCAN Memory

pub fn pefpprf(&mut self) -> PEFPPRF_W<'_>

Bit 13 - Parity Error Flag for PMU Prefetch Memory

pub fn peusb(&mut self) -> PEUSB_W<'_>

Bit 16 - Parity Error Flag for USB Memory

impl W<u32, Reg<u32, _PMTPR>>

pub fn pwr(&mut self) -> PWR_W<'_>

Bits 0:7 - Parity Write Values for Memory Test

impl W<u32, Reg<u32, _PMTSR>>

pub fn mtenps(&mut self) -> MTENPS_W<'_>

Bit 0 - Test Enable Control for PSRAM

pub fn mtends1(&mut self) -> MTENDS1_W<'_>

Bit 1 - Test Enable Control for DSRAM1

pub fn mteu0(&mut self) -> MTEU0_W<'_>

Bit 8 - Test Enable Control for USIC0 Memory

pub fn mteu1(&mut self) -> MTEU1_W<'_>

Bit 9 - Test Enable Control for USIC1 Memory

pub fn mtemc(&mut self) -> MTEMC_W<'_>

Bit 12 - Test Enable Control for MultiCAN Memory

pub fn mtepprf(&mut self) -> MTEPPRF_W<'_>

Bit 13 - Test Enable Control for PMU Prefetch Memory

pub fn mtusb(&mut self) -> MTUSB_W<'_>

Bit 16 - Test Enable Control for USB Memory

impl W<u32, Reg<u32, _TRAPDIS>>

pub fn soscwdgt(&mut self) -> SOSCWDGT_W<'_>

Bit 0 - System OSC WDT Trap Disable

pub fn svcolckt(&mut self) -> SVCOLCKT_W<'_>

Bit 2 - System VCO Lock Trap Disable

pub fn uvcolckt(&mut self) -> UVCOLCKT_W<'_>

Bit 3 - USB VCO Lock Trap Disable

pub fn pet(&mut self) -> PET_W<'_>

Bit 4 - Parity Error Trap Disable

pub fn brwnt(&mut self) -> BRWNT_W<'_>

Bit 5 - Brown Out Trap Disable

pub fn ulpwdgt(&mut self) -> ULPWDGT_W<'_>

Bit 6 - Wake-up Trap Disable

pub fn bwerr0t(&mut self) -> BWERR0T_W<'_>

Bit 7 - Peripheral Bridge 0 Trap Disable

pub fn bwerr1t(&mut self) -> BWERR1T_W<'_>

Bit 8 - Peripheral Bridge 1 Trap Disable

pub fn temphit(&mut self) -> TEMPHIT_W<'_>

Bit 12 - Die Temperature Too High Trap Disable

pub fn templot(&mut self) -> TEMPLOT_W<'_>

Bit 13 - Die Temperature Too Low Trap Disable

impl W<u32, Reg<u32, _TRAPCLR>>

pub fn soscwdgt(&mut self) -> SOSCWDGT_W<'_>

Bit 0 - System OSC WDT Trap Clear

pub fn svcolckt(&mut self) -> SVCOLCKT_W<'_>

Bit 2 - System VCO Lock Trap Clear

pub fn uvcolckt(&mut self) -> UVCOLCKT_W<'_>

Bit 3 - USB VCO Lock Trap Clear

pub fn pet(&mut self) -> PET_W<'_>

Bit 4 - Parity Error Trap Clear

pub fn brwnt(&mut self) -> BRWNT_W<'_>

Bit 5 - Brown Out Trap Clear

pub fn ulpwdgt(&mut self) -> ULPWDGT_W<'_>

Bit 6 - OSC_ULP WDG Trap Clear

pub fn bwerr0t(&mut self) -> BWERR0T_W<'_>

Bit 7 - Peripheral Bridge 0 Trap Clear

pub fn bwerr1t(&mut self) -> BWERR1T_W<'_>

Bit 8 - Peripheral Bridge 1 Trap Clear

pub fn temphit(&mut self) -> TEMPHIT_W<'_>

Bit 12 - Die Temperature Too High Trap Clear

pub fn templot(&mut self) -> TEMPLOT_W<'_>

Bit 13 - Die Temperature Too Low Trap Clear

impl W<u32, Reg<u32, _TRAPSET>>

pub fn soscwdgt(&mut self) -> SOSCWDGT_W<'_>

Bit 0 - System OSC WDT Trap Set

pub fn svcolckt(&mut self) -> SVCOLCKT_W<'_>

Bit 2 - System VCO Lock Trap Set

pub fn uvcolckt(&mut self) -> UVCOLCKT_W<'_>

Bit 3 - USB VCO Lock Trap Set

pub fn pet(&mut self) -> PET_W<'_>

Bit 4 - Parity Error Trap Set

pub fn brwnt(&mut self) -> BRWNT_W<'_>

Bit 5 - Brown Out Trap Set

pub fn ulpwdt(&mut self) -> ULPWDT_W<'_>

Bit 6 - OSC_ULP WDG Trap Set

pub fn bwerr0t(&mut self) -> BWERR0T_W<'_>

Bit 7 - Peripheral Bridge 0 Trap Set

pub fn bwerr1t(&mut self) -> BWERR1T_W<'_>

Bit 8 - Peripheral Bridge 1 Trap Set

pub fn temphit(&mut self) -> TEMPHIT_W<'_>

Bit 12 - Die Temperature Too High Trap Set

pub fn templot(&mut self) -> TEMPLOT_W<'_>

Bit 13 - Die Temperature Too Low Trap Set

impl W<u32, Reg<u32, _HDCLR>>

pub fn epev(&mut self) -> EPEV_W<'_>

Bit 0 - Wake-up Pin Event Positive Edge Clear

pub fn enev(&mut self) -> ENEV_W<'_>

Bit 1 - Wake-up Pin Event Negative Edge Clear

pub fn rtcev(&mut self) -> RTCEV_W<'_>

Bit 2 - RTC Event Clear

pub fn ulpwdg(&mut self) -> ULPWDG_W<'_>

Bit 3 - ULP WDG Alarm Clear

pub fn vbatpev(&mut self) -> VBATPEV_W<'_>

Bit 8 - Wake-Up on LPAC Positive Edge of VBAT Threshold Crossing Clear

pub fn vbatnev(&mut self) -> VBATNEV_W<'_>

Bit 9 - Wake-Up on LPAC Negative Edge of VBAT Threshold Crossing Clear

pub fn ahibio0pev(&mut self) -> AHIBIO0PEV_W<'_>

Bit 10 - Wake-Up on LPAC Positive Edge of HIB_IO_0 Threshold Crossing Clear

pub fn ahibio0nev(&mut self) -> AHIBIO0NEV_W<'_>

Bit 11 - Wake-Up on LPAC Negative Edge of HIB_IO_0 Threshold Crossing Clear

impl W<u32, Reg<u32, _HDSET>>

pub fn epev(&mut self) -> EPEV_W<'_>

Bit 0 - Wake-up Pin Event Positive Edge Set

pub fn enev(&mut self) -> ENEV_W<'_>

Bit 1 - Wake-up Pin Event Negative Edge Set

pub fn rtcev(&mut self) -> RTCEV_W<'_>

Bit 2 - RTC Event Set

pub fn ulpwdg(&mut self) -> ULPWDG_W<'_>

Bit 3 - ULP WDG Alarm Set

pub fn vbatpev(&mut self) -> VBATPEV_W<'_>

Bit 8 - Wake-Up on LPAC Positive Edge of VBAT Threshold Crossing Set

pub fn vbatnev(&mut self) -> VBATNEV_W<'_>

Bit 9 - Wake-Up on LPAC Negative Edge of VBAT Threshold Crossing Set

pub fn ahibio0pev(&mut self) -> AHIBIO0PEV_W<'_>

Bit 10 - Wake-Up on LPAC Positive Edge of HIB_IO_0 Threshold Crossing Set

pub fn ahibio0nev(&mut self) -> AHIBIO0NEV_W<'_>

Bit 11 - Wake-Up on LPAC Negative Edge of HIB_IO_0 Threshold Crossing Set

impl W<u32, Reg<u32, _HDCR>>

pub fn wkpep(&mut self) -> WKPEP_W<'_>

Bit 0 - Wake-Up on Pin Event Positive Edge Enable

pub fn wkpen(&mut self) -> WKPEN_W<'_>

Bit 1 - Wake-up on Pin Event Negative Edge Enable

pub fn rtce(&mut self) -> RTCE_W<'_>

Bit 2 - Wake-up on RTC Event Enable

pub fn ulpwdgen(&mut self) -> ULPWDGEN_W<'_>

Bit 3 - ULP WDG Alarm Enable

pub fn hib(&mut self) -> HIB_W<'_>

Bit 4 - Hibernate Request Value Set

pub fn xtalgpi1sel(&mut self) -> XTALGPI1SEL_W<'_>

Bit 5 - Multiplex Control for RTC_XTAL_1 Select as GPI Input

pub fn rcs(&mut self) -> RCS_W<'_>

Bit 6 - fRTC Clock Selection

pub fn stdbysel(&mut self) -> STDBYSEL_W<'_>

Bit 7 - fSTDBY Clock Selection

pub fn wkupsel(&mut self) -> WKUPSEL_W<'_>

Bit 8 - Wake-Up from Hibernate Trigger Input Selection

pub fn gpi0sel(&mut self) -> GPI0SEL_W<'_>

Bit 10 - General Purpose Input 0 Selection

pub fn hibio0pol(&mut self) -> HIBIO0POL_W<'_>

Bit 12 - HIBIO0 Polarity Set

pub fn adig0sel(&mut self) -> ADIG0SEL_W<'_>

Bit 14 - Select Analog Channel 0 or Digital Output Path

pub fn hibio0sel(&mut self) -> HIBIO0SEL_W<'_>

Bits 16:19 - HIB_IO_0 Pin I/O Control (default HIBOUT)

pub fn vbatlo(&mut self) -> VBATLO_W<'_>

Bit 24 - Wake-Up on VBAT Falling Below Threshold Enable

pub fn vbathi(&mut self) -> VBATHI_W<'_>

Bit 25 - Wake-Up on VBAT Rising Above Threshold Enable

pub fn ahibio0lo(&mut self) -> AHIBIO0LO_W<'_>

Bit 26 - Wake-Up on Analog HIB_IO_0 Falling Below Threshold Enable

pub fn ahibio0hi(&mut self) -> AHIBIO0HI_W<'_>

Bit 27 - Wake-Up on Analog HIB_IO_0 Rising Above Threshold Enable

impl W<u32, Reg<u32, _OSCSICTRL>>

pub fn pwd(&mut self) -> PWD_W<'_>

Bit 0 - Turn OFF the fOSI Clock Source

impl W<u32, Reg<u32, _OSCULCTRL>>

pub fn x1den(&mut self) -> X1DEN_W<'_>

Bit 0 - XTAL1 Data General Purpose Input Enable

pub fn mode(&mut self) -> MODE_W<'_>

Bits 4:5 - Oscillator Mode

impl W<u32, Reg<u32, _LPACCONF>>

pub fn cmpen(&mut self) -> CMPEN_W<'_>

Bits 0:2 - Compare Enable for Input Selection

pub fn trigsel(&mut self) -> TRIGSEL_W<'_>

Bits 4:6 - Analog Compare Trigger Select

pub fn convdel(&mut self) -> CONVDEL_W<'_>

Bit 12 - Conversion Delay

pub fn intervcnt(&mut self) -> INTERVCNT_W<'_>

Bits 16:27 - Sub-second Interval Counter

pub fn settlecnt(&mut self) -> SETTLECNT_W<'_>

Bits 28:31 - LPAC Settle Time Counter

impl W<u32, Reg<u32, _LPACTH0>>

pub fn vbatlo(&mut self) -> VBATLO_W<'_>

Bits 0:5 - VBAT Lower Threshold Value

pub fn vbathi(&mut self) -> VBATHI_W<'_>

Bits 8:13 - VBAT Upper Threshold Value

impl W<u32, Reg<u32, _LPACTH1>>

pub fn ahibio0lo(&mut self) -> AHIBIO0LO_W<'_>

Bits 0:5 - Analog HIB_IO_0 Lower Threshold Value

pub fn ahibio0hi(&mut self) -> AHIBIO0HI_W<'_>

Bits 8:13 - Analog HIB_IO_0 Upper Threshold Value

impl W<u32, Reg<u32, _LPACCLR>>

pub fn vbatscmp(&mut self) -> VBATSCMP_W<'_>

Bit 0 - Trigger VBAT Single Compare Operation Clear

pub fn ahibio0scmp(&mut self) -> AHIBIO0SCMP_W<'_>

Bit 1 - Trigger HIB_IO_0 Input Single Compare Operation Clear

pub fn vbatval(&mut self) -> VBATVAL_W<'_>

Bit 16 - VBAT Compare Operation Initial Value Clear

pub fn ahibio0val(&mut self) -> AHIBIO0VAL_W<'_>

Bit 17 - HIB_IO_0 Input Compare Initial Value Clear

impl W<u32, Reg<u32, _LPACSET>>

pub fn vbatscmp(&mut self) -> VBATSCMP_W<'_>

Bit 0 - Trigger VBAT Single Compare Operation Set

pub fn ahibio0scmp(&mut self) -> AHIBIO0SCMP_W<'_>

Bit 1 - Trigger HIB_IO_0 Input Single Compare Operation Set

pub fn vbatval(&mut self) -> VBATVAL_W<'_>

Bit 16 - VBAT Compare Operation Initial Value Set

pub fn ahibio0val(&mut self) -> AHIBIO0VAL_W<'_>

Bit 17 - HIB_IO_0 Input Compare Initial Value Set

impl W<u32, Reg<u32, _HINTCLR>>

pub fn hibnint(&mut self) -> HIBNINT_W<'_>

Bit 0 - Internally Controlled Hibernate Sequence Request Clear

pub fn flashoff(&mut self) -> FLASHOFF_W<'_>

Bit 2 - VDDP Supply Switch of Flash Clear

pub fn flashpd(&mut self) -> FLASHPD_W<'_>

Bit 3 - Flash Power Down Clear

pub fn poffd(&mut self) -> POFFD_W<'_>

Bit 4 - PORST Pull-up OFF Direct Control Clear

pub fn ppodel(&mut self) -> PPODEL_W<'_>

Bits 16:17 - Delay on PORTS Pull-up Switching OFF on Hibernate Request Clear

pub fn poffh(&mut self) -> POFFH_W<'_>

Bit 20 - PORST Pull-up OFF in Hibernate Mode Clear

impl W<u32, Reg<u32, _HINTSET>>

pub fn hibnint(&mut self) -> HIBNINT_W<'_>

Bit 0 - Internally Controlled Hibernate Sequence Request Set

pub fn vcoreoff(&mut self) -> VCOREOFF_W<'_>

Bit 1 - VDDC Generation off on EVR Set

pub fn flashoff(&mut self) -> FLASHOFF_W<'_>

Bit 2 - VDDP Supply Switch of Flash Set

pub fn flashpd(&mut self) -> FLASHPD_W<'_>

Bit 3 - Flash Power Down Set

pub fn poffd(&mut self) -> POFFD_W<'_>

Bit 4 - PORST Pull-up OFF Direct Control Set

pub fn ppodel(&mut self) -> PPODEL_W<'_>

Bits 16:17 - Delay on PORTS Pull-up Switching OFF on Hibernate Request Set

pub fn poffh(&mut self) -> POFFH_W<'_>

Bit 20 - PORST Pull-up OFF in Hibernate Mode Set

impl W<u32, Reg<u32, _PWRSET>>

pub fn hib(&mut self) -> HIB_W<'_>

Bit 0 - Set Hibernate Domain Enable

pub fn usbphypdq(&mut self) -> USBPHYPDQ_W<'_>

Bit 16 - Set USB PHY Transceiver Disable

pub fn usbpuwq(&mut self) -> USBPUWQ_W<'_>

Bit 18 - Set USB Weak Pull-Up at PADN Enable

impl W<u32, Reg<u32, _PWRCLR>>

pub fn hib(&mut self) -> HIB_W<'_>

Bit 0 - Clear Disable Hibernate Domain

pub fn usbphypdq(&mut self) -> USBPHYPDQ_W<'_>

Bit 16 - Clear USB PHY Transceiver Disable

pub fn usbpuwq(&mut self) -> USBPUWQ_W<'_>

Bit 18 - Clear USB Weak Pull-Up at PADN Enable

impl W<u32, Reg<u32, _PWRMON>>

pub fn thrs(&mut self) -> THRS_W<'_>

Bits 0:7 - Threshold

pub fn intv(&mut self) -> INTV_W<'_>

Bits 8:15 - Interval

pub fn enb(&mut self) -> ENB_W<'_>

Bit 16 - Enable

impl W<u32, Reg<u32, _RSTSET>>

pub fn hibwk(&mut self) -> HIBWK_W<'_>

Bit 8 - Set Hibernate Wake-up Reset Status

pub fn hibrs(&mut self) -> HIBRS_W<'_>

Bit 9 - Set Hibernate Reset

pub fn lcken(&mut self) -> LCKEN_W<'_>

Bit 10 - Enable Lockup Reset

impl W<u32, Reg<u32, _RSTCLR>>

pub fn rsclr(&mut self) -> RSCLR_W<'_>

Bit 0 - Clear Reset Status

pub fn hibwk(&mut self) -> HIBWK_W<'_>

Bit 8 - Clear Hibernate Wake-up Reset Status

pub fn hibrs(&mut self) -> HIBRS_W<'_>

Bit 9 - Clear Hibernate Reset

pub fn lcken(&mut self) -> LCKEN_W<'_>

Bit 10 - Enable Lockup Reset

impl W<u32, Reg<u32, _PRSET0>>

pub fn vadcrs(&mut self) -> VADCRS_W<'_>

Bit 0 - VADC Reset Assert

pub fn ccu40rs(&mut self) -> CCU40RS_W<'_>

Bit 2 - CCU40 Reset Assert

pub fn ccu41rs(&mut self) -> CCU41RS_W<'_>

Bit 3 - CCU41 Reset Assert

pub fn ccu80rs(&mut self) -> CCU80RS_W<'_>

Bit 7 - CCU80 Reset Assert

pub fn posif0rs(&mut self) -> POSIF0RS_W<'_>

Bit 9 - POSIF0 Reset Assert

pub fn usic0rs(&mut self) -> USIC0RS_W<'_>

Bit 11 - USIC0 Reset Assert

pub fn eru1rs(&mut self) -> ERU1RS_W<'_>

Bit 16 - ERU1 Reset Assert

pub fn hrpwm0rs(&mut self) -> HRPWM0RS_W<'_>

Bit 23 - HRPWM0 Reset Assert

impl W<u32, Reg<u32, _PRCLR0>>

pub fn vadcrs(&mut self) -> VADCRS_W<'_>

Bit 0 - VADC Reset Clear

pub fn ccu40rs(&mut self) -> CCU40RS_W<'_>

Bit 2 - CCU40 Reset Clear

pub fn ccu41rs(&mut self) -> CCU41RS_W<'_>

Bit 3 - CCU41 Reset Clear

pub fn ccu80rs(&mut self) -> CCU80RS_W<'_>

Bit 7 - CCU80 Reset Clear

pub fn posif0rs(&mut self) -> POSIF0RS_W<'_>

Bit 9 - POSIF0 Reset Clear

pub fn usic0rs(&mut self) -> USIC0RS_W<'_>

Bit 11 - USIC0 Reset Clear

pub fn eru1rs(&mut self) -> ERU1RS_W<'_>

Bit 16 - ERU1 Reset Clear

pub fn hrpwm0rs(&mut self) -> HRPWM0RS_W<'_>

Bit 23 - HRPWM0 Reset Clear

impl W<u32, Reg<u32, _PRSET1>>

pub fn ledtscu0rs(&mut self) -> LEDTSCU0RS_W<'_>

Bit 3 - LEDTS Reset Assert

pub fn mcan0rs(&mut self) -> MCAN0RS_W<'_>

Bit 4 - MultiCAN Reset Assert

pub fn dacrs(&mut self) -> DACRS_W<'_>

Bit 5 - DAC Reset Assert

pub fn usic1rs(&mut self) -> USIC1RS_W<'_>

Bit 7 - USIC1 Reset Assert

pub fn pportsrs(&mut self) -> PPORTSRS_W<'_>

Bit 9 - PORTS Reset Assert

impl W<u32, Reg<u32, _PRCLR1>>

pub fn ledtscu0rs(&mut self) -> LEDTSCU0RS_W<'_>

Bit 3 - LEDTS Reset Clear

pub fn mcan0rs(&mut self) -> MCAN0RS_W<'_>

Bit 4 - MultiCAN Reset Clear

pub fn dacrs(&mut self) -> DACRS_W<'_>

Bit 5 - DAC Reset Clear

pub fn usic1rs(&mut self) -> USIC1RS_W<'_>

Bit 7 - USIC1 Reset Clear

pub fn pportsrs(&mut self) -> PPORTSRS_W<'_>

Bit 9 - PORTS Reset Clear

impl W<u32, Reg<u32, _PRSET2>>

pub fn wdtrs(&mut self) -> WDTRS_W<'_>

Bit 1 - WDT Reset Assert

pub fn dma0rs(&mut self) -> DMA0RS_W<'_>

Bit 4 - DMA0 Reset Assert

pub fn fcers(&mut self) -> FCERS_W<'_>

Bit 6 - FCE Reset Assert

pub fn usbrs(&mut self) -> USBRS_W<'_>

Bit 7 - USB Reset Assert

impl W<u32, Reg<u32, _PRCLR2>>

pub fn wdtrs(&mut self) -> WDTRS_W<'_>

Bit 1 - WDT Reset Clear

pub fn dma0rs(&mut self) -> DMA0RS_W<'_>

Bit 4 - DMA0 Reset Clear

pub fn fcers(&mut self) -> FCERS_W<'_>

Bit 6 - FCE Reset Clear

pub fn usbrs(&mut self) -> USBRS_W<'_>

Bit 7 - USB Reset Clear

impl W<u32, Reg<u32, _GLOBCTL>>

pub fn ts_en(&mut self) -> TS_EN_W<'_>

Bit 0 - Touch-Sense Function Enable

pub fn ld_en(&mut self) -> LD_EN_W<'_>

Bit 1 - LED Function Enable

pub fn cmtr(&mut self) -> CMTR_W<'_>

Bit 2 - Clock Master Disable

pub fn ensync(&mut self) -> ENSYNC_W<'_>

Bit 3 - Enable Autoscan Time Period Synchronization

pub fn suscfg(&mut self) -> SUSCFG_W<'_>

Bit 8 - Suspend Request Configuration

pub fn maskval(&mut self) -> MASKVAL_W<'_>

Bits 9:11 - Mask Number of LSB Bits for Event Validation

pub fn fenval(&mut self) -> FENVAL_W<'_>

Bit 12 - Enable (Extended) Time Frame Validation

pub fn its_en(&mut self) -> ITS_EN_W<'_>

Bit 13 - Enable Time Slice Interrupt

pub fn itf_en(&mut self) -> ITF_EN_W<'_>

Bit 14 - Enable (Extended) Time Frame Interrupt

pub fn itp_en(&mut self) -> ITP_EN_W<'_>

Bit 15 - Enable Autoscan Time Period Interrupt

pub fn clk_ps(&mut self) -> CLK_PS_W<'_>

Bits 16:31 - LEDTS-Counter Clock Pre-Scale Factor

impl W<u32, Reg<u32, _FNCTL>>

pub fn padt(&mut self) -> PADT_W<'_>

Bits 0:2 - Touch-Sense TSIN Pad Turn

pub fn padtsw(&mut self) -> PADTSW_W<'_>

Bit 3 - Software Control for Touch-Sense Pad Turn

pub fn epull(&mut self) -> EPULL_W<'_>

Bit 4 - Enable External Pull-up Configuration on Pin COLA

pub fn acccnt(&mut self) -> ACCCNT_W<'_>

Bits 16:19 - Accumulate Count on Touch-Sense Input

pub fn tsccmp(&mut self) -> TSCCMP_W<'_>

Bit 20 - Common Compare Enable for Touch-Sense

pub fn tsoext(&mut self) -> TSOEXT_W<'_>

Bits 21:22 - Extension for Touch-Sense Output for Pin-Low-Level

pub fn tsctrr(&mut self) -> TSCTRR_W<'_>

Bit 23 - TS-Counter Auto Reset

pub fn tsctrsat(&mut self) -> TSCTRSAT_W<'_>

Bit 24 - Saturation of TS-Counter

pub fn nr_tsin(&mut self) -> NR_TSIN_W<'_>

Bits 25:27 - Number of Touch-Sense Input

pub fn collev(&mut self) -> COLLEV_W<'_>

Bit 28 - Active Level of LED Column

pub fn nr_ledcol(&mut self) -> NR_LEDCOL_W<'_>

Bits 29:31 - Number of LED Columns

impl W<u32, Reg<u32, _EVFR>>

pub fn ctsf(&mut self) -> CTSF_W<'_>

Bit 16 - Clear Time Slice Interrupt Flag

pub fn ctff(&mut self) -> CTFF_W<'_>

Bit 17 - Clear (Extended) Time Frame Interrupt Flag

pub fn ctpf(&mut self) -> CTPF_W<'_>

Bit 18 - Clear Autoscan Time Period Interrupt Flag

impl W<u32, Reg<u32, _TSVAL>>

pub fn tsctrval(&mut self) -> TSCTRVAL_W<'_>

Bits 16:31 - TS-Counter Value

impl W<u32, Reg<u32, _LINE0>>

pub fn line_0(&mut self) -> LINE_0_W<'_>

Bits 0:7 - Output on LINE[x]

pub fn line_1(&mut self) -> LINE_1_W<'_>

Bits 8:15 - Output on LINE[x]

pub fn line_2(&mut self) -> LINE_2_W<'_>

Bits 16:23 - Output on LINE[x]

pub fn line_3(&mut self) -> LINE_3_W<'_>

Bits 24:31 - Output on LINE[x]

impl W<u32, Reg<u32, _LINE1>>

pub fn line_4(&mut self) -> LINE_4_W<'_>

Bits 0:7 - Output on LINE[x]

pub fn line_5(&mut self) -> LINE_5_W<'_>

Bits 8:15 - Output on LINE[x]

pub fn line_6(&mut self) -> LINE_6_W<'_>

Bits 16:23 - Output on LINE[x]

pub fn line_a(&mut self) -> LINE_A_W<'_>

Bits 24:31 - Output on LINE[x]

impl W<u32, Reg<u32, _LDCMP0>>

pub fn cmp_ld0(&mut self) -> CMP_LD0_W<'_>

Bits 0:7 - Compare Value for LED COL[x]

pub fn cmp_ld1(&mut self) -> CMP_LD1_W<'_>

Bits 8:15 - Compare Value for LED COL[x]

pub fn cmp_ld2(&mut self) -> CMP_LD2_W<'_>

Bits 16:23 - Compare Value for LED COL[x]

pub fn cmp_ld3(&mut self) -> CMP_LD3_W<'_>

Bits 24:31 - Compare Value for LED COL[x]

impl W<u32, Reg<u32, _LDCMP1>>

pub fn cmp_ld4(&mut self) -> CMP_LD4_W<'_>

Bits 0:7 - Compare Value for LED COL[x]

pub fn cmp_ld5(&mut self) -> CMP_LD5_W<'_>

Bits 8:15 - Compare Value for LED COL[x]

pub fn cmp_ld6(&mut self) -> CMP_LD6_W<'_>

Bits 16:23 - Compare Value for LED COL[x]

pub fn cmp_lda_tscom(&mut self) -> CMP_LDA_TSCOM_W<'_>

Bits 24:31 - Compare Value for LED COLA / Common Compare Value for Touch-sense Pad Turns

impl W<u32, Reg<u32, _TSCMP0>>

pub fn cmp_ts0(&mut self) -> CMP_TS0_W<'_>

Bits 0:7 - Compare Value for Touch-Sense TSIN[x]

pub fn cmp_ts1(&mut self) -> CMP_TS1_W<'_>

Bits 8:15 - Compare Value for Touch-Sense TSIN[x]

pub fn cmp_ts2(&mut self) -> CMP_TS2_W<'_>

Bits 16:23 - Compare Value for Touch-Sense TSIN[x]

pub fn cmp_ts3(&mut self) -> CMP_TS3_W<'_>

Bits 24:31 - Compare Value for Touch-Sense TSIN[x]

impl W<u32, Reg<u32, _TSCMP1>>

pub fn cmp_ts4(&mut self) -> CMP_TS4_W<'_>

Bits 0:7 - Compare Value for Touch-Sense TSIN[x]

pub fn cmp_ts5(&mut self) -> CMP_TS5_W<'_>

Bits 8:15 - Compare Value for Touch-Sense TSIN[x]

pub fn cmp_ts6(&mut self) -> CMP_TS6_W<'_>

Bits 16:23 - Compare Value for Touch-Sense TSIN[x]

pub fn cmp_ts7(&mut self) -> CMP_TS7_W<'_>

Bits 24:31 - Compare Value for Touch-Sense TSIN[x]

impl W<u32, Reg<u32, _GAHBCFG>>

pub fn glbl_intr_msk(&mut self) -> GLBLINTRMSK_W<'_>

Bit 0 - Global Interrupt Mask

pub fn hbst_len(&mut self) -> HBSTLEN_W<'_>

Bits 1:4 - Burst Length/Type

pub fn dmaen(&mut self) -> DMAEN_W<'_>

Bit 5 - DMA Enable

pub fn nptx_femp_lvl(&mut self) -> NPTXFEMPLVL_W<'_>

Bit 7 - Non-Periodic TxFIFO Empty Level

pub fn ahbsingle(&mut self) -> AHBSINGLE_W<'_>

Bit 23 - AHB Single Support

impl W<u32, Reg<u32, _GUSBCFG>>

pub fn tout_cal(&mut self) -> TOUTCAL_W<'_>

Bits 0:2 - FS Timeout Calibration

pub fn usbtrd_tim(&mut self) -> USBTRDTIM_W<'_>

Bits 10:13 - USB Turnaround Time

pub fn tx_end_delay(&mut self) -> TXENDDELAY_W<'_>

Bit 28 - Tx End Delay

pub fn force_dev_mode(&mut self) -> FORCEDEVMODE_W<'_>

Bit 30 - Force Device Mode

pub fn ctp(&mut self) -> CTP_W<'_>

Bit 31 - Corrupt Tx packet

impl W<u32, Reg<u32, _GRSTCTL>>

pub fn csft_rst(&mut self) -> CSFTRST_W<'_>

Bit 0 - Core Soft Reset

pub fn rx_fflsh(&mut self) -> RXFFLSH_W<'_>

Bit 4 - RxFIFO Flush

pub fn tx_fflsh(&mut self) -> TXFFLSH_W<'_>

Bit 5 - TxFIFO Flush

pub fn tx_fnum(&mut self) -> TXFNUM_W<'_>

Bits 6:10 - TxFIFO Number

impl W<u32, Reg<u32, _GINTSTS>>

pub fn sof(&mut self) -> SOF_W<'_>

Bit 3 - Start of Frame

pub fn erly_susp(&mut self) -> ERLYSUSP_W<'_>

Bit 10 - Early Suspend

pub fn usbsusp(&mut self) -> USBSUSP_W<'_>

Bit 11 - USB Suspend

pub fn usbrst(&mut self) -> USBRST_W<'_>

Bit 12 - USB Reset

pub fn enum_done(&mut self) -> ENUMDONE_W<'_>

Bit 13 - Enumeration Done

pub fn isoout_drop(&mut self) -> ISOOUTDROP_W<'_>

Bit 14 - Isochronous OUT Packet Dropped Interrupt

pub fn eopf(&mut self) -> EOPF_W<'_>

Bit 15 - End of Periodic Frame Interrupt

pub fn incomp_isoin(&mut self) -> INCOMPISOIN_W<'_>

Bit 20 - Incomplete Isochronous IN Transfer

pub fn incompl_soout(&mut self) -> INCOMPLSOOUT_W<'_>

Bit 21 - Incomplete Isochronous OUT Transfer

pub fn wk_up_int(&mut self) -> WKUPINT_W<'_>

Bit 31 - Resume/Remote Wakeup Detected Interrupt

impl W<u32, Reg<u32, _GINTMSK>>

pub fn sof_msk(&mut self) -> SOFMSK_W<'_>

Bit 3 - Start of Frame Mask

pub fn rx_flvl_msk(&mut self) -> RXFLVLMSK_W<'_>

Bit 4 - Receive FIFO Non-Empty Mask

pub fn ginnak_eff_msk(&mut self) -> GINNAKEFFMSK_W<'_>

Bit 6 - Global Non-periodic IN NAK Effective Mask

pub fn goutnak_eff_msk(&mut self) -> GOUTNAKEFFMSK_W<'_>

Bit 7 - Global OUT NAK Effective Mask

pub fn erly_susp_msk(&mut self) -> ERLYSUSPMSK_W<'_>

Bit 10 - Early Suspend Mask

pub fn usbsusp_msk(&mut self) -> USBSUSPMSK_W<'_>

Bit 11 - USB Suspend Mask

pub fn usbrst_msk(&mut self) -> USBRSTMSK_W<'_>

Bit 12 - USB Reset Mask

pub fn enum_done_msk(&mut self) -> ENUMDONEMSK_W<'_>

Bit 13 - Enumeration Done Mask

pub fn isoout_drop_msk(&mut self) -> ISOOUTDROPMSK_W<'_>

Bit 14 - Isochronous OUT Packet Dropped Interrupt Mask

pub fn eopfmsk(&mut self) -> EOPFMSK_W<'_>

Bit 15 - End of Periodic Frame Interrupt Mask

pub fn iepint_msk(&mut self) -> IEPINTMSK_W<'_>

Bit 18 - IN Endpoints Interrupt Mask

pub fn oepint_msk(&mut self) -> OEPINTMSK_W<'_>

Bit 19 - OUT Endpoints Interrupt Mask

pub fn incomp_isoinmsk(&mut self) -> INCOMPISOINMSK_W<'_>

Bit 20 - Incomplete Isochronous IN Transfer Mask

pub fn incompl_sooutmsk(&mut self) -> INCOMPLSOOUTMSK_W<'_>

Bit 21 - Incomplete Isochronous OUT Transfer Mask

pub fn wk_up_int_msk(&mut self) -> WKUPINTMSK_W<'_>

Bit 31 - Resume/Remote Wakeup Detected Interrupt Mask

impl W<u32, Reg<u32, _GRXFSIZ>>

pub fn rx_fdep(&mut self) -> RXFDEP_W<'_>

Bits 0:15 - RxFIFO Depth

impl W<u32, Reg<u32, _GNPTXFSIZ>>

pub fn ineptx_f0st_addr(&mut self) -> INEPTXF0STADDR_W<'_>

Bits 0:15 - IN Endpoint FIFO0 Transmit RAM Start Address

pub fn ineptx_f0dep(&mut self) -> INEPTXF0DEP_W<'_>

Bits 16:31 - IN Endpoint TxFIFO 0 Depth

impl W<u32, Reg<u32, _GUID>>

pub fn mod_rev(&mut self) -> MOD_REV_W<'_>

Bits 0:7 - Module Revision

pub fn mod_type(&mut self) -> MOD_TYPE_W<'_>

Bits 8:15 - Module Type

pub fn mod_number(&mut self) -> MOD_NUMBER_W<'_>

Bits 16:31 - Module Number

impl W<u32, Reg<u32, _GDFIFOCFG>>

pub fn gdfifocfg(&mut self) -> GDFIFOCFG_W<'_>

Bits 0:15 - GDFIFOCfg

pub fn epinfo_base_addr(&mut self) -> EPINFOBASEADDR_W<'_>

Bits 16:31 - EPInfoBaseAddr

impl W<u32, Reg<u32, _DIEPTXF1>>

pub fn inepn_tx_fst_addr(&mut self) -> INEPNTXFSTADDR_W<'_>

Bits 0:15 - IN Endpoint FIFOn Transmit RAM Start Address

pub fn inepn_tx_fdep(&mut self) -> INEPNTXFDEP_W<'_>

Bits 16:31 - IN Endpoint TxFIFO Depth

impl W<u32, Reg<u32, _DIEPTXF2>>

pub fn inepn_tx_fst_addr(&mut self) -> INEPNTXFSTADDR_W<'_>

Bits 0:15 - IN Endpoint FIFOn Transmit RAM Start Address

pub fn inepn_tx_fdep(&mut self) -> INEPNTXFDEP_W<'_>

Bits 16:31 - IN Endpoint TxFIFO Depth

impl W<u32, Reg<u32, _DIEPTXF3>>

pub fn inepn_tx_fst_addr(&mut self) -> INEPNTXFSTADDR_W<'_>

Bits 0:15 - IN Endpoint FIFOn Transmit RAM Start Address

pub fn inepn_tx_fdep(&mut self) -> INEPNTXFDEP_W<'_>

Bits 16:31 - IN Endpoint TxFIFO Depth

impl W<u32, Reg<u32, _DIEPTXF4>>

pub fn inepn_tx_fst_addr(&mut self) -> INEPNTXFSTADDR_W<'_>

Bits 0:15 - IN Endpoint FIFOn Transmit RAM Start Address

pub fn inepn_tx_fdep(&mut self) -> INEPNTXFDEP_W<'_>

Bits 16:31 - IN Endpoint TxFIFO Depth

impl W<u32, Reg<u32, _DIEPTXF5>>

pub fn inepn_tx_fst_addr(&mut self) -> INEPNTXFSTADDR_W<'_>

Bits 0:15 - IN Endpoint FIFOn Transmit RAM Start Address

pub fn inepn_tx_fdep(&mut self) -> INEPNTXFDEP_W<'_>

Bits 16:31 - IN Endpoint TxFIFO Depth

impl W<u32, Reg<u32, _DIEPTXF6>>

pub fn inepn_tx_fst_addr(&mut self) -> INEPNTXFSTADDR_W<'_>

Bits 0:15 - IN Endpoint FIFOn Transmit RAM Start Address

pub fn inepn_tx_fdep(&mut self) -> INEPNTXFDEP_W<'_>

Bits 16:31 - IN Endpoint TxFIFO Depth

impl W<u32, Reg<u32, _DCFG>>

pub fn dev_spd(&mut self) -> DEVSPD_W<'_>

Bits 0:1 - Device Speed

pub fn nzsts_outhshk(&mut self) -> NZSTSOUTHSHK_W<'_>

Bit 2 - Non-Zero-Length Status OUT Handshake

pub fn dev_addr(&mut self) -> DEVADDR_W<'_>

Bits 4:10 - Device Address

pub fn per_fr_int(&mut self) -> PERFRINT_W<'_>

Bits 11:12 - Periodic Frame Interval

pub fn desc_dma(&mut self) -> DESCDMA_W<'_>

Bit 23 - Enable Scatter/Gather DMA in Device mode.

pub fn per_sch_intvl(&mut self) -> PERSCHINTVL_W<'_>

Bits 24:25 - Periodic Scheduling Interval

impl W<u32, Reg<u32, _DCTL>>

pub fn rmt_wk_up_sig(&mut self) -> RMTWKUPSIG_W<'_>

Bit 0 - Remote Wakeup Signaling

pub fn sft_discon(&mut self) -> SFTDISCON_W<'_>

Bit 1 - Soft Disconnect

pub fn sgnpin_nak(&mut self) -> SGNPINNAK_W<'_>

Bit 7 - Set Global Non-periodic IN NAK

pub fn cgnpin_nak(&mut self) -> CGNPINNAK_W<'_>

Bit 8 - Clear Global Non-periodic IN NAK

pub fn sgoutnak(&mut self) -> SGOUTNAK_W<'_>

Bit 9 - Set Global OUT NAK

pub fn cgoutnak(&mut self) -> CGOUTNAK_W<'_>

Bit 10 - Clear Global OUT NAK

pub fn gmc(&mut self) -> GMC_W<'_>

Bits 13:14 - Global Multi Count

pub fn ignr_frm_num(&mut self) -> IGNRFRMNUM_W<'_>

Bit 15 - Ignore frame number for isochronous endpoints in case of Scatter/Gather DMA

pub fn nak_on_bble(&mut self) -> NAKONBBLE_W<'_>

Bit 16 - Set NAK automatically on babble

pub fn en_cont_on_bna(&mut self) -> ENCONTONBNA_W<'_>

Bit 17 - Enable continue on BNA

impl W<u32, Reg<u32, _DIEPMSK>>

pub fn xfer_compl_msk(&mut self) -> XFERCOMPLMSK_W<'_>

Bit 0 - Transfer Completed Interrupt Mask

pub fn epdisbld_msk(&mut self) -> EPDISBLDMSK_W<'_>

Bit 1 - Endpoint Disabled Interrupt Mask

pub fn ahberr_msk(&mut self) -> AHBERRMSK_W<'_>

Bit 2 - AHB Error Mask

pub fn time_outmsk(&mut self) -> TIMEOUTMSK_W<'_>

Bit 3 - Timeout Condition Mask

pub fn intkn_txfemp_msk(&mut self) -> INTKNTXFEMPMSK_W<'_>

Bit 4 - IN Token Received When TxFIFO Empty Mask

pub fn inepnak_eff_msk(&mut self) -> INEPNAKEFFMSK_W<'_>

Bit 6 - IN Endpoint NAK Effective Mask

pub fn txfifo_undrn_msk(&mut self) -> TXFIFOUNDRNMSK_W<'_>

Bit 8 - Fifo Underrun Mask

pub fn bnain_intr_msk(&mut self) -> BNAININTRMSK_W<'_>

Bit 9 - BNA Interrupt Mask

pub fn nakmsk(&mut self) -> NAKMSK_W<'_>

Bit 13 - NAK interrupt Mask

impl W<u32, Reg<u32, _DOEPMSK>>

pub fn xfer_compl_msk(&mut self) -> XFERCOMPLMSK_W<'_>

Bit 0 - Transfer Completed Interrupt Mask

pub fn epdisbld_msk(&mut self) -> EPDISBLDMSK_W<'_>

Bit 1 - Endpoint Disabled Interrupt Mask

pub fn ahberr_msk(&mut self) -> AHBERRMSK_W<'_>

Bit 2 - AHB Error

pub fn set_upmsk(&mut self) -> SETUPMSK_W<'_>

Bit 3 - SETUP Phase Done Mask

pub fn outtkn_epdis_msk(&mut self) -> OUTTKNEPDISMSK_W<'_>

Bit 4 - OUT Token Received when Endpoint Disabled Mask

pub fn back2back_setup(&mut self) -> BACK2BACKSETUP_W<'_>

Bit 6 - Back-to-Back SETUP Packets Received Mask

pub fn out_pkt_err_msk(&mut self) -> OUTPKTERRMSK_W<'_>

Bit 8 - OUT Packet Error Mask

pub fn bna_out_intr_msk(&mut self) -> BNAOUTINTRMSK_W<'_>

Bit 9 - BNA interrupt Mask

pub fn bble_err_msk(&mut self) -> BBLEERRMSK_W<'_>

Bit 12 - Babble Interrupt Mask

pub fn nakmsk(&mut self) -> NAKMSK_W<'_>

Bit 13 - NAK Interrupt Mask

pub fn nyetmsk(&mut self) -> NYETMSK_W<'_>

Bit 14 - NYET Interrupt Mask

impl W<u32, Reg<u32, _DAINTMSK>>

pub fn in_ep_msk(&mut self) -> INEPMSK_W<'_>

Bits 0:15 - IN EP Interrupt Mask Bits

pub fn out_ep_msk(&mut self) -> OUTEPMSK_W<'_>

Bits 16:31 - OUT EP Interrupt Mask Bits

impl W<u32, Reg<u32, _DVBUSDIS>>

pub fn dvbusdis(&mut self) -> DVBUSDIS_W<'_>

Bits 0:15 - Device Vbus Discharge Time

impl W<u32, Reg<u32, _DVBUSPULSE>>

pub fn dvbuspulse(&mut self) -> DVBUSPULSE_W<'_>

Bits 0:11 - Device Vbus Pulsing Time

impl W<u32, Reg<u32, _DIEPEMPMSK>>

pub fn in_ep_txf_emp_msk(&mut self) -> INEPTXFEMPMSK_W<'_>

Bits 0:15 - IN EP Tx FIFO Empty Interrupt Mask Bits

impl W<u32, Reg<u32, _PCGCCTL>>

pub fn stop_pclk(&mut self) -> STOPPCLK_W<'_>

Bit 0 - Stop Pclk

pub fn gate_hclk(&mut self) -> GATEHCLK_W<'_>

Bit 1 - Gate Hclk

impl W<u32, Reg<u32, _DIEPCTL0>>

pub fn mps(&mut self) -> MPS_W<'_>

Bits 0:1 - Maximum Packet Size

pub fn stall(&mut self) -> STALL_W<'_>

Bit 21 - STALL Handshake

pub fn tx_fnum(&mut self) -> TXFNUM_W<'_>

Bits 22:25 - TxFIFO Number

pub fn cnak(&mut self) -> CNAK_W<'_>

Bit 26 - Clear NAK

pub fn snak(&mut self) -> SNAK_W<'_>

Bit 27 - Set NAK

pub fn epdis(&mut self) -> EPDIS_W<'_>

Bit 30 - Endpoint Disable

pub fn epena(&mut self) -> EPENA_W<'_>

Bit 31 - Endpoint Enable

impl W<u32, Reg<u32, _DIEPINT0>>

pub fn xfer_compl(&mut self) -> XFERCOMPL_W<'_>

Bit 0 - Transfer Completed Interrupt

pub fn epdisbld(&mut self) -> EPDISBLD_W<'_>

Bit 1 - Endpoint Disabled Interrupt

pub fn ahberr(&mut self) -> AHBERR_W<'_>

Bit 2 - AHB Error

pub fn time_out(&mut self) -> TIMEOUT_W<'_>

Bit 3 - Timeout Condition

pub fn intkn_txfemp(&mut self) -> INTKNTXFEMP_W<'_>

Bit 4 - IN Token Received When TxFIFO is Empty

pub fn inepnak_eff(&mut self) -> INEPNAKEFF_W<'_>

Bit 6 - IN Endpoint NAK Effective

pub fn bnaintr(&mut self) -> BNAINTR_W<'_>

Bit 9 - BNA (Buffer Not Available) Interrupt

impl W<u32, Reg<u32, _DIEPTSIZ0>>

pub fn xfer_size(&mut self) -> XFERSIZE_W<'_>

Bits 0:6 - Transfer Size

pub fn pkt_cnt(&mut self) -> PKTCNT_W<'_>

Bits 19:20 - Packet Count

impl W<u32, Reg<u32, _DIEPDMA0>>

pub fn dmaaddr(&mut self) -> DMAADDR_W<'_>

Bits 0:31 - DMA Address

impl W<u32, Reg<u32, _DOEPCTL0>>

pub fn snp(&mut self) -> SNP_W<'_>

Bit 20 - Snoop Mode

pub fn stall(&mut self) -> STALL_W<'_>

Bit 21 - STALL Handshake

pub fn cnak(&mut self) -> CNAK_W<'_>

Bit 26 - Clear NAK

pub fn snak(&mut self) -> SNAK_W<'_>

Bit 27 - Set NAK

pub fn epena(&mut self) -> EPENA_W<'_>

Bit 31 - Endpoint Enable

impl W<u32, Reg<u32, _DOEPINT0>>

pub fn xfer_compl(&mut self) -> XFERCOMPL_W<'_>

Bit 0 - Transfer Completed Interrupt

pub fn epdisbld(&mut self) -> EPDISBLD_W<'_>

Bit 1 - Endpoint Disabled Interrupt

pub fn ahberr(&mut self) -> AHBERR_W<'_>

Bit 2 - AHB Error

pub fn set_up(&mut self) -> SETUP_W<'_>

Bit 3 - SETUP Phase Done

pub fn outtkn_epdis(&mut self) -> OUTTKNEPDIS_W<'_>

Bit 4 - OUT Token Received When Endpoint Disabled

pub fn sts_phse_rcvd(&mut self) -> STSPHSERCVD_W<'_>

Bit 5 - Status Phase Received For Control Write

pub fn back2back_setup(&mut self) -> BACK2BACKSETUP_W<'_>

Bit 6 - Back-to-Back SETUP Packets Received

pub fn bnaintr(&mut self) -> BNAINTR_W<'_>

Bit 9 - BNA (Buffer Not Available) Interrupt

pub fn pkt_drp_sts(&mut self) -> PKTDRPSTS_W<'_>

Bit 11 - Packet Dropped Status

pub fn bble_err_intrpt(&mut self) -> BBLEERRINTRPT_W<'_>

Bit 12 - BbleErr (Babble Error) interrupt

pub fn nakintrpt(&mut self) -> NAKINTRPT_W<'_>

Bit 13 - NAK interrupt

pub fn nyetintrpt(&mut self) -> NYETINTRPT_W<'_>

Bit 14 - NYET interrupt

impl W<u32, Reg<u32, _DOEPTSIZ0>>

pub fn xfer_size(&mut self) -> XFERSIZE_W<'_>

Bits 0:6 - Transfer Size

pub fn pkt_cnt(&mut self) -> PKTCNT_W<'_>

Bits 19:20 - Packet Count

pub fn supcnt(&mut self) -> SUPCNT_W<'_>

Bits 29:30 - SETUP Packet Count

impl W<u32, Reg<u32, _DOEPDMA0>>

pub fn dmaaddr(&mut self) -> DMAADDR_W<'_>

Bits 0:31 - DMA Address

impl W<u32, Reg<u32, _DIEPCTL_ISOCONT>>

pub fn mps(&mut self) -> MPS_W<'_>

Bits 0:10 - Maximum Packet Size

pub fn usbact_ep(&mut self) -> USBACTEP_W<'_>

Bit 15 - USB Active Endpoint

pub fn eptype(&mut self) -> EPTYPE_W<'_>

Bits 18:19 - Endpoint Type

pub fn snp(&mut self) -> SNP_W<'_>

Bit 20 - Snoop Mode

pub fn stall(&mut self) -> STALL_W<'_>

Bit 21 - STALL Handshake

pub fn tx_fnum(&mut self) -> TXFNUM_W<'_>

Bits 22:25 - TxFIFO Number

pub fn cnak(&mut self) -> CNAK_W<'_>

Bit 26 - Clear NAK

pub fn snak(&mut self) -> SNAK_W<'_>

Bit 27 - Set NAK

pub fn set_even_fr(&mut self) -> SETEVENFR_W<'_>

Bit 28 - In non-Scatter/Gather DMA mode: Set Even frame

pub fn set_odd_fr(&mut self) -> SETODDFR_W<'_>

Bit 29 - Set Odd frame

pub fn epdis(&mut self) -> EPDIS_W<'_>

Bit 30 - Endpoint Disable

pub fn epena(&mut self) -> EPENA_W<'_>

Bit 31 - Endpoint Enable

impl W<u32, Reg<u32, _DIEPCTL_INTBULK>>

pub fn mps(&mut self) -> MPS_W<'_>

Bits 0:10 - Maximum Packet Size

pub fn usbact_ep(&mut self) -> USBACTEP_W<'_>

Bit 15 - USB Active Endpoint

pub fn eptype(&mut self) -> EPTYPE_W<'_>

Bits 18:19 - Endpoint Type

pub fn snp(&mut self) -> SNP_W<'_>

Bit 20 - Snoop Mode

pub fn stall(&mut self) -> STALL_W<'_>

Bit 21 - STALL Handshake

pub fn tx_fnum(&mut self) -> TXFNUM_W<'_>

Bits 22:25 - TxFIFO Number

pub fn cnak(&mut self) -> CNAK_W<'_>

Bit 26 - Clear NAK

pub fn snak(&mut self) -> SNAK_W<'_>

Bit 27 - Set NAK

pub fn set_d0pid(&mut self) -> SETD0PID_W<'_>

Bit 28 - Set DATA0 PID

pub fn set_d1pid(&mut self) -> SETD1PID_W<'_>

Bit 29 - 29 Set DATA1 PID

pub fn epdis(&mut self) -> EPDIS_W<'_>

Bit 30 - Endpoint Disable

pub fn epena(&mut self) -> EPENA_W<'_>

Bit 31 - Endpoint Enable

impl W<u32, Reg<u32, _DIEPINT>>

pub fn xfer_compl(&mut self) -> XFERCOMPL_W<'_>

Bit 0 - Transfer Completed Interrupt

pub fn epdisbld(&mut self) -> EPDISBLD_W<'_>

Bit 1 - Endpoint Disabled Interrupt

pub fn ahberr(&mut self) -> AHBERR_W<'_>

Bit 2 - AHB Error

pub fn time_out(&mut self) -> TIMEOUT_W<'_>

Bit 3 - Timeout Condition

pub fn intkn_txfemp(&mut self) -> INTKNTXFEMP_W<'_>

Bit 4 - IN Token Received When TxFIFO is Empty

pub fn inepnak_eff(&mut self) -> INEPNAKEFF_W<'_>

Bit 6 - IN Endpoint NAK Effective

pub fn bnaintr(&mut self) -> BNAINTR_W<'_>

Bit 9 - BNA (Buffer Not Available) Interrupt

impl W<u32, Reg<u32, _DIEPTSIZ>>

pub fn xfer_size(&mut self) -> XFERSIZE_W<'_>

Bits 0:18 - Transfer Size

pub fn pkt_cnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet Count

impl W<u32, Reg<u32, _DIEPDMA>>

pub fn dmaaddr(&mut self) -> DMAADDR_W<'_>

Bits 0:31 - DMA Address

impl W<u32, Reg<u32, _DOEPCTL_ISOCONT>>

pub fn mps(&mut self) -> MPS_W<'_>

Bits 0:10 - Maximum Packet Size

pub fn usbact_ep(&mut self) -> USBACTEP_W<'_>

Bit 15 - USB Active Endpoint

pub fn eptype(&mut self) -> EPTYPE_W<'_>

Bits 18:19 - Endpoint Type

pub fn snp(&mut self) -> SNP_W<'_>

Bit 20 - Snoop Mode

pub fn stall(&mut self) -> STALL_W<'_>

Bit 21 - STALL Handshake

pub fn tx_fnum(&mut self) -> TXFNUM_W<'_>

Bits 22:25 - TxFIFO Number

pub fn cnak(&mut self) -> CNAK_W<'_>

Bit 26 - Clear NAK

pub fn snak(&mut self) -> SNAK_W<'_>

Bit 27 - Set NAK

pub fn set_even_fr(&mut self) -> SETEVENFR_W<'_>

Bit 28 - In non-Scatter/Gather DMA mode: Set Even frame

pub fn set_odd_fr(&mut self) -> SETODDFR_W<'_>

Bit 29 - Set Odd frame

pub fn epdis(&mut self) -> EPDIS_W<'_>

Bit 30 - Endpoint Disable

pub fn epena(&mut self) -> EPENA_W<'_>

Bit 31 - Endpoint Enable

impl W<u32, Reg<u32, _DOEPCTL_INTBULK>>

pub fn mps(&mut self) -> MPS_W<'_>

Bits 0:10 - Maximum Packet Size

pub fn usbact_ep(&mut self) -> USBACTEP_W<'_>

Bit 15 - USB Active Endpoint

pub fn eptype(&mut self) -> EPTYPE_W<'_>

Bits 18:19 - Endpoint Type

pub fn snp(&mut self) -> SNP_W<'_>

Bit 20 - Snoop Mode

pub fn stall(&mut self) -> STALL_W<'_>

Bit 21 - STALL Handshake

pub fn tx_fnum(&mut self) -> TXFNUM_W<'_>

Bits 22:25 - TxFIFO Number

pub fn cnak(&mut self) -> CNAK_W<'_>

Bit 26 - Clear NAK

pub fn snak(&mut self) -> SNAK_W<'_>

Bit 27 - Set NAK

pub fn set_d0pid(&mut self) -> SETD0PID_W<'_>

Bit 28 - Set DATA0 PID

pub fn set_d1pid(&mut self) -> SETD1PID_W<'_>

Bit 29 - 29 Set DATA1 PID

pub fn epdis(&mut self) -> EPDIS_W<'_>

Bit 30 - Endpoint Disable

pub fn epena(&mut self) -> EPENA_W<'_>

Bit 31 - Endpoint Enable

impl W<u32, Reg<u32, _DOEPINT>>

pub fn xfer_compl(&mut self) -> XFERCOMPL_W<'_>

Bit 0 - Transfer Completed Interrupt

pub fn epdisbld(&mut self) -> EPDISBLD_W<'_>

Bit 1 - Endpoint Disabled Interrupt

pub fn ahberr(&mut self) -> AHBERR_W<'_>

Bit 2 - AHB Error

pub fn set_up(&mut self) -> SETUP_W<'_>

Bit 3 - SETUP Phase Done

pub fn outtkn_epdis(&mut self) -> OUTTKNEPDIS_W<'_>

Bit 4 - OUT Token Received When Endpoint Disabled

pub fn sts_phse_rcvd(&mut self) -> STSPHSERCVD_W<'_>

Bit 5 - Status Phase Received For Control Write

pub fn back2back_setup(&mut self) -> BACK2BACKSETUP_W<'_>

Bit 6 - Back-to-Back SETUP Packets Received

pub fn bnaintr(&mut self) -> BNAINTR_W<'_>

Bit 9 - BNA (Buffer Not Available) Interrupt

pub fn pkt_drp_sts(&mut self) -> PKTDRPSTS_W<'_>

Bit 11 - Packet Dropped Status

pub fn bble_err_intrpt(&mut self) -> BBLEERRINTRPT_W<'_>

Bit 12 - BbleErr (Babble Error) interrupt

pub fn nakintrpt(&mut self) -> NAKINTRPT_W<'_>

Bit 13 - NAK interrupt

pub fn nyetintrpt(&mut self) -> NYETINTRPT_W<'_>

Bit 14 - NYET interrupt

impl W<u32, Reg<u32, _DOEPTSIZ_ISO>>

pub fn xfer_size(&mut self) -> XFERSIZE_W<'_>

Bits 0:18 - Transfer Size

pub fn pkt_cnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet Count

impl W<u32, Reg<u32, _DOEPTSIZ_CONTROL>>

pub fn xfer_size(&mut self) -> XFERSIZE_W<'_>

Bits 0:18 - Transfer Size

pub fn pkt_cnt(&mut self) -> PKTCNT_W<'_>

Bits 19:28 - Packet Count

pub fn supcnt(&mut self) -> SUPCNT_W<'_>

Bits 29:30 - SETUP Packet Count

impl W<u32, Reg<u32, _DOEPDMA>>

pub fn dmaaddr(&mut self) -> DMAADDR_W<'_>

Bits 0:31 - DMA Address

impl W<u32, Reg<u32, _KSCFG>>

pub fn moden(&mut self) -> MODEN_W<'_>

Bit 0 - Module Enable

pub fn bpmoden(&mut self) -> BPMODEN_W<'_>

Bit 1 - Bit Protection for MODEN

pub fn nomcfg(&mut self) -> NOMCFG_W<'_>

Bits 4:5 - Normal Operation Mode Configuration

pub fn bpnom(&mut self) -> BPNOM_W<'_>

Bit 7 - Bit Protection for NOMCFG

pub fn sumcfg(&mut self) -> SUMCFG_W<'_>

Bits 8:9 - Suspend Mode Configuration

pub fn bpsum(&mut self) -> BPSUM_W<'_>

Bit 11 - Bit Protection for SUMCFG

impl W<u32, Reg<u32, _FDR>>

pub fn step(&mut self) -> STEP_W<'_>

Bits 0:9 - Step Value

pub fn dm(&mut self) -> DM_W<'_>

Bits 14:15 - Divider Mode

impl W<u32, Reg<u32, _BRG>>

pub fn clksel(&mut self) -> CLKSEL_W<'_>

Bits 0:1 - Clock Selection

pub fn tmen(&mut self) -> TMEN_W<'_>

Bit 3 - Timing Measurement Enable

pub fn pppen(&mut self) -> PPPEN_W<'_>

Bit 4 - Enable 2:1 Divider for fPPP

pub fn ctqsel(&mut self) -> CTQSEL_W<'_>

Bits 6:7 - Input Selection for CTQ

pub fn pctq(&mut self) -> PCTQ_W<'_>

Bits 8:9 - Pre-Divider for Time Quanta Counter

pub fn dctq(&mut self) -> DCTQ_W<'_>

Bits 10:14 - Denominator for Time Quanta Counter

pub fn pdiv(&mut self) -> PDIV_W<'_>

Bits 16:25 - Divider Mode: Divider Factor to Generate fPDIV

pub fn sclkosel(&mut self) -> SCLKOSEL_W<'_>

Bit 28 - Shift Clock Output Select

pub fn mclkcfg(&mut self) -> MCLKCFG_W<'_>

Bit 29 - Master Clock Configuration

pub fn sclkcfg(&mut self) -> SCLKCFG_W<'_>

Bits 30:31 - Shift Clock Output Configuration

impl W<u32, Reg<u32, _INPR>>

pub fn tsinp(&mut self) -> TSINP_W<'_>

Bits 0:2 - Transmit Shift Interrupt Node Pointer

pub fn tbinp(&mut self) -> TBINP_W<'_>

Bits 4:6 - Transmit Buffer Interrupt Node Pointer

pub fn rinp(&mut self) -> RINP_W<'_>

Bits 8:10 - Receive Interrupt Node Pointer

pub fn ainp(&mut self) -> AINP_W<'_>

Bits 12:14 - Alternative Receive Interrupt Node Pointer

pub fn pinp(&mut self) -> PINP_W<'_>

Bits 16:18 - Transmit Shift Interrupt Node Pointer

impl W<u32, Reg<u32, _DX0CR>>

pub fn dsel(&mut self) -> DSEL_W<'_>

Bits 0:2 - Data Selection for Input Signal

pub fn insw(&mut self) -> INSW_W<'_>

Bit 4 - Input Switch

pub fn dfen(&mut self) -> DFEN_W<'_>

Bit 5 - Digital Filter Enable

pub fn dsen(&mut self) -> DSEN_W<'_>

Bit 6 - Data Synchronization Enable

pub fn dpol(&mut self) -> DPOL_W<'_>

Bit 8 - Data Polarity for DXn

pub fn sfsel(&mut self) -> SFSEL_W<'_>

Bit 9 - Sampling Frequency Selection

pub fn cm(&mut self) -> CM_W<'_>

Bits 10:11 - Combination Mode

impl W<u32, Reg<u32, _DX1CR>>

pub fn dsel(&mut self) -> DSEL_W<'_>

Bits 0:2 - Data Selection for Input Signal

pub fn dcen(&mut self) -> DCEN_W<'_>

Bit 3 - Delay Compensation Enable

pub fn insw(&mut self) -> INSW_W<'_>

Bit 4 - Input Switch

pub fn dfen(&mut self) -> DFEN_W<'_>

Bit 5 - Digital Filter Enable

pub fn dsen(&mut self) -> DSEN_W<'_>

Bit 6 - Data Synchronization Enable

pub fn dpol(&mut self) -> DPOL_W<'_>

Bit 8 - Data Polarity for DXn

pub fn sfsel(&mut self) -> SFSEL_W<'_>

Bit 9 - Sampling Frequency Selection

pub fn cm(&mut self) -> CM_W<'_>

Bits 10:11 - Combination Mode

impl W<u32, Reg<u32, _DX2CR>>

pub fn dsel(&mut self) -> DSEL_W<'_>

Bits 0:2 - Data Selection for Input Signal

pub fn insw(&mut self) -> INSW_W<'_>

Bit 4 - Input Switch

pub fn dfen(&mut self) -> DFEN_W<'_>

Bit 5 - Digital Filter Enable

pub fn dsen(&mut self) -> DSEN_W<'_>

Bit 6 - Data Synchronization Enable

pub fn dpol(&mut self) -> DPOL_W<'_>

Bit 8 - Data Polarity for DXn

pub fn sfsel(&mut self) -> SFSEL_W<'_>

Bit 9 - Sampling Frequency Selection

pub fn cm(&mut self) -> CM_W<'_>

Bits 10:11 - Combination Mode

impl W<u32, Reg<u32, _DX3CR>>

pub fn dsel(&mut self) -> DSEL_W<'_>

Bits 0:2 - Data Selection for Input Signal

pub fn insw(&mut self) -> INSW_W<'_>

Bit 4 - Input Switch

pub fn dfen(&mut self) -> DFEN_W<'_>

Bit 5 - Digital Filter Enable

pub fn dsen(&mut self) -> DSEN_W<'_>

Bit 6 - Data Synchronization Enable

pub fn dpol(&mut self) -> DPOL_W<'_>

Bit 8 - Data Polarity for DXn

pub fn sfsel(&mut self) -> SFSEL_W<'_>

Bit 9 - Sampling Frequency Selection

pub fn cm(&mut self) -> CM_W<'_>

Bits 10:11 - Combination Mode

impl W<u32, Reg<u32, _DX4CR>>

pub fn dsel(&mut self) -> DSEL_W<'_>

Bits 0:2 - Data Selection for Input Signal

pub fn insw(&mut self) -> INSW_W<'_>

Bit 4 - Input Switch

pub fn dfen(&mut self) -> DFEN_W<'_>

Bit 5 - Digital Filter Enable

pub fn dsen(&mut self) -> DSEN_W<'_>

Bit 6 - Data Synchronization Enable

pub fn dpol(&mut self) -> DPOL_W<'_>

Bit 8 - Data Polarity for DXn

pub fn sfsel(&mut self) -> SFSEL_W<'_>

Bit 9 - Sampling Frequency Selection

pub fn cm(&mut self) -> CM_W<'_>

Bits 10:11 - Combination Mode

impl W<u32, Reg<u32, _DX5CR>>

pub fn dsel(&mut self) -> DSEL_W<'_>

Bits 0:2 - Data Selection for Input Signal

pub fn insw(&mut self) -> INSW_W<'_>

Bit 4 - Input Switch

pub fn dfen(&mut self) -> DFEN_W<'_>

Bit 5 - Digital Filter Enable

pub fn dsen(&mut self) -> DSEN_W<'_>

Bit 6 - Data Synchronization Enable

pub fn dpol(&mut self) -> DPOL_W<'_>

Bit 8 - Data Polarity for DXn

pub fn sfsel(&mut self) -> SFSEL_W<'_>

Bit 9 - Sampling Frequency Selection

pub fn cm(&mut self) -> CM_W<'_>

Bits 10:11 - Combination Mode

impl W<u32, Reg<u32, _SCTR>>

pub fn sdir(&mut self) -> SDIR_W<'_>

Bit 0 - Shift Direction

pub fn pdl(&mut self) -> PDL_W<'_>

Bit 1 - Passive Data Level

pub fn dsm(&mut self) -> DSM_W<'_>

Bits 2:3 - Data Shift Mode

pub fn hpcdir(&mut self) -> HPCDIR_W<'_>

Bit 4 - Port Control Direction

pub fn docfg(&mut self) -> DOCFG_W<'_>

Bits 6:7 - Data Output Configuration

pub fn trm(&mut self) -> TRM_W<'_>

Bits 8:9 - Transmission Mode

pub fn fle(&mut self) -> FLE_W<'_>

Bits 16:21 - Frame Length

pub fn wle(&mut self) -> WLE_W<'_>

Bits 24:27 - Word Length

impl W<u32, Reg<u32, _TCSR>>

pub fn wlemd(&mut self) -> WLEMD_W<'_>

Bit 0 - WLE Mode

pub fn selmd(&mut self) -> SELMD_W<'_>

Bit 1 - Select Mode

pub fn flemd(&mut self) -> FLEMD_W<'_>

Bit 2 - FLE Mode

pub fn wamd(&mut self) -> WAMD_W<'_>

Bit 3 - WA Mode

pub fn hpcmd(&mut self) -> HPCMD_W<'_>

Bit 4 - Hardware Port Control Mode

pub fn sof(&mut self) -> SOF_W<'_>

Bit 5 - Start Of Frame

pub fn eof(&mut self) -> EOF_W<'_>

Bit 6 - End Of Frame

pub fn tdssm(&mut self) -> TDSSM_W<'_>

Bit 8 - TBUF Data Single Shot Mode

pub fn tden(&mut self) -> TDEN_W<'_>

Bits 10:11 - TBUF Data Enable

pub fn tdvtr(&mut self) -> TDVTR_W<'_>

Bit 12 - TBUF Data Valid Trigger

pub fn wa(&mut self) -> WA_W<'_>

Bit 13 - Word Address

impl W<u32, Reg<u32, _PCR>>

pub fn ctr0(&mut self) -> CTR0_W<'_>

Bit 0 - Protocol Control Bit 0

pub fn ctr1(&mut self) -> CTR1_W<'_>

Bit 1 - Protocol Control Bit 1

pub fn ctr2(&mut self) -> CTR2_W<'_>

Bit 2 - Protocol Control Bit 2

pub fn ctr3(&mut self) -> CTR3_W<'_>

Bit 3 - Protocol Control Bit 3

pub fn ctr4(&mut self) -> CTR4_W<'_>

Bit 4 - Protocol Control Bit 4

pub fn ctr5(&mut self) -> CTR5_W<'_>

Bit 5 - Protocol Control Bit 5

pub fn ctr6(&mut self) -> CTR6_W<'_>

Bit 6 - Protocol Control Bit 6

pub fn ctr7(&mut self) -> CTR7_W<'_>

Bit 7 - Protocol Control Bit 7

pub fn ctr8(&mut self) -> CTR8_W<'_>

Bit 8 - Protocol Control Bit 8

pub fn ctr9(&mut self) -> CTR9_W<'_>

Bit 9 - Protocol Control Bit 9

pub fn ctr10(&mut self) -> CTR10_W<'_>

Bit 10 - Protocol Control Bit 10

pub fn ctr11(&mut self) -> CTR11_W<'_>

Bit 11 - Protocol Control Bit 11

pub fn ctr12(&mut self) -> CTR12_W<'_>

Bit 12 - Protocol Control Bit 12

pub fn ctr13(&mut self) -> CTR13_W<'_>

Bit 13 - Protocol Control Bit 13

pub fn ctr14(&mut self) -> CTR14_W<'_>

Bit 14 - Protocol Control Bit 14

pub fn ctr15(&mut self) -> CTR15_W<'_>

Bit 15 - Protocol Control Bit 15

pub fn ctr16(&mut self) -> CTR16_W<'_>

Bit 16 - Protocol Control Bit 16

pub fn ctr17(&mut self) -> CTR17_W<'_>

Bit 17 - Protocol Control Bit 17

pub fn ctr18(&mut self) -> CTR18_W<'_>

Bit 18 - Protocol Control Bit 18

pub fn ctr19(&mut self) -> CTR19_W<'_>

Bit 19 - Protocol Control Bit 19

pub fn ctr20(&mut self) -> CTR20_W<'_>

Bit 20 - Protocol Control Bit 20

pub fn ctr21(&mut self) -> CTR21_W<'_>

Bit 21 - Protocol Control Bit 21

pub fn ctr22(&mut self) -> CTR22_W<'_>

Bit 22 - Protocol Control Bit 22

pub fn ctr23(&mut self) -> CTR23_W<'_>

Bit 23 - Protocol Control Bit 23

pub fn ctr24(&mut self) -> CTR24_W<'_>

Bit 24 - Protocol Control Bit 24

pub fn ctr25(&mut self) -> CTR25_W<'_>

Bit 25 - Protocol Control Bit 25

pub fn ctr26(&mut self) -> CTR26_W<'_>

Bit 26 - Protocol Control Bit 26

pub fn ctr27(&mut self) -> CTR27_W<'_>

Bit 27 - Protocol Control Bit 27

pub fn ctr28(&mut self) -> CTR28_W<'_>

Bit 28 - Protocol Control Bit 28

pub fn ctr29(&mut self) -> CTR29_W<'_>

Bit 29 - Protocol Control Bit 29

pub fn ctr30(&mut self) -> CTR30_W<'_>

Bit 30 - Protocol Control Bit 30

pub fn ctr31(&mut self) -> CTR31_W<'_>

Bit 31 - Protocol Control Bit 31

impl W<u32, Reg<u32, _PCR_ASCMODE>>

pub fn smd(&mut self) -> SMD_W<'_>

Bit 0 - Sample Mode

pub fn stpb(&mut self) -> STPB_W<'_>

Bit 1 - Stop Bits

pub fn idm(&mut self) -> IDM_W<'_>

Bit 2 - Idle Detection Mode

pub fn sbien(&mut self) -> SBIEN_W<'_>

Bit 3 - Synchronization Break Interrupt Enable

pub fn cden(&mut self) -> CDEN_W<'_>

Bit 4 - Collision Detection Enable

pub fn rnien(&mut self) -> RNIEN_W<'_>

Bit 5 - Receiver Noise Detection Interrupt Enable

pub fn feien(&mut self) -> FEIEN_W<'_>

Bit 6 - Format Error Interrupt Enable

pub fn ffien(&mut self) -> FFIEN_W<'_>

Bit 7 - Frame Finished Interrupt Enable

pub fn sp(&mut self) -> SP_W<'_>

Bits 8:12 - Sample Point

pub fn pl(&mut self) -> PL_W<'_>

Bits 13:15 - Pulse Length

pub fn rsten(&mut self) -> RSTEN_W<'_>

Bit 16 - Receiver Status Enable

pub fn tsten(&mut self) -> TSTEN_W<'_>

Bit 17 - Transmitter Status Enable

pub fn mclk(&mut self) -> MCLK_W<'_>

Bit 31 - Master Clock Enable

impl W<u32, Reg<u32, _PCR_SSCMODE>>

pub fn mslsen(&mut self) -> MSLSEN_W<'_>

Bit 0 - MSLS Enable

pub fn selctr(&mut self) -> SELCTR_W<'_>

Bit 1 - Select Control

pub fn selinv(&mut self) -> SELINV_W<'_>

Bit 2 - Select Inversion

pub fn fem(&mut self) -> FEM_W<'_>

Bit 3 - Frame End Mode

pub fn ctqsel1(&mut self) -> CTQSEL1_W<'_>

Bits 4:5 - Input Frequency Selection

pub fn pctq1(&mut self) -> PCTQ1_W<'_>

Bits 6:7 - Divider Factor PCTQ1 for Tiw and Tnf

pub fn dctq1(&mut self) -> DCTQ1_W<'_>

Bits 8:12 - Divider Factor DCTQ1 for Tiw and Tnf

pub fn parien(&mut self) -> PARIEN_W<'_>

Bit 13 - Parity Error Interrupt Enable

pub fn mslsien(&mut self) -> MSLSIEN_W<'_>

Bit 14 - MSLS Interrupt Enable

pub fn dx2tien(&mut self) -> DX2TIEN_W<'_>

Bit 15 - DX2T Interrupt Enable

pub fn selo(&mut self) -> SELO_W<'_>

Bits 16:23 - Select Output

pub fn tiwen(&mut self) -> TIWEN_W<'_>

Bit 24 - Enable Inter-Word Delay Tiw

pub fn slphsel(&mut self) -> SLPHSEL_W<'_>

Bit 25 - Slave Mode Clock Phase Select

pub fn mclk(&mut self) -> MCLK_W<'_>

Bit 31 - Master Clock Enable

impl W<u32, Reg<u32, _PCR_IICMODE>>

pub fn slad(&mut self) -> SLAD_W<'_>

Bits 0:15 - Slave Address

pub fn ack00(&mut self) -> ACK00_W<'_>

Bit 16 - Acknowledge 00H

pub fn stim(&mut self) -> STIM_W<'_>

Bit 17 - Symbol Timing

pub fn scrien(&mut self) -> SCRIEN_W<'_>

Bit 18 - Start Condition Received Interrupt Enable

pub fn rscrien(&mut self) -> RSCRIEN_W<'_>

Bit 19 - Repeated Start Condition Received Interrupt Enable

pub fn pcrien(&mut self) -> PCRIEN_W<'_>

Bit 20 - Stop Condition Received Interrupt Enable

pub fn nackien(&mut self) -> NACKIEN_W<'_>

Bit 21 - Non-Acknowledge Interrupt Enable

pub fn arlien(&mut self) -> ARLIEN_W<'_>

Bit 22 - Arbitration Lost Interrupt Enable

pub fn srrien(&mut self) -> SRRIEN_W<'_>

Bit 23 - Slave Read Request Interrupt Enable

pub fn errien(&mut self) -> ERRIEN_W<'_>

Bit 24 - Error Interrupt Enable

pub fn sackdis(&mut self) -> SACKDIS_W<'_>

Bit 25 - Slave Acknowledge Disable

pub fn hdel(&mut self) -> HDEL_W<'_>

Bits 26:29 - Hardware Delay

pub fn ackien(&mut self) -> ACKIEN_W<'_>

Bit 30 - Acknowledge Interrupt Enable

pub fn mclk(&mut self) -> MCLK_W<'_>

Bit 31 - Master Clock Enable

impl W<u32, Reg<u32, _PCR_IISMODE>>

pub fn wagen(&mut self) -> WAGEN_W<'_>

Bit 0 - WA Generation Enable

pub fn dten(&mut self) -> DTEN_W<'_>

Bit 1 - Data Transfers Enable

pub fn selinv(&mut self) -> SELINV_W<'_>

Bit 2 - Select Inversion

pub fn wafeien(&mut self) -> WAFEIEN_W<'_>

Bit 4 - WA Falling Edge Interrupt Enable

pub fn wareien(&mut self) -> WAREIEN_W<'_>

Bit 5 - WA Rising Edge Interrupt Enable

pub fn endien(&mut self) -> ENDIEN_W<'_>

Bit 6 - END Interrupt Enable

pub fn dx2tien(&mut self) -> DX2TIEN_W<'_>

Bit 15 - DX2T Interrupt Enable

pub fn tdel(&mut self) -> TDEL_W<'_>

Bits 16:21 - Transfer Delay

pub fn mclk(&mut self) -> MCLK_W<'_>

Bit 31 - Master Clock Enable

impl W<u32, Reg<u32, _CCR>>

pub fn mode(&mut self) -> MODE_W<'_>

Bits 0:3 - Operating Mode

pub fn hpcen(&mut self) -> HPCEN_W<'_>

Bits 6:7 - Hardware Port Control Enable

pub fn pm(&mut self) -> PM_W<'_>

Bits 8:9 - Parity Mode

pub fn rsien(&mut self) -> RSIEN_W<'_>

Bit 10 - Receiver Start Interrupt Enable

pub fn dlien(&mut self) -> DLIEN_W<'_>

Bit 11 - Data Lost Interrupt Enable

pub fn tsien(&mut self) -> TSIEN_W<'_>

Bit 12 - Transmit Shift Interrupt Enable

pub fn tbien(&mut self) -> TBIEN_W<'_>

Bit 13 - Transmit Buffer Interrupt Enable

pub fn rien(&mut self) -> RIEN_W<'_>

Bit 14 - Receive Interrupt Enable

pub fn aien(&mut self) -> AIEN_W<'_>

Bit 15 - Alternative Receive Interrupt Enable

pub fn brgien(&mut self) -> BRGIEN_W<'_>

Bit 16 - Baud Rate Generator Interrupt Enable

impl W<u32, Reg<u32, _CMTR>>

pub fn ctv(&mut self) -> CTV_W<'_>

Bits 0:9 - Captured Timer Value

impl W<u32, Reg<u32, _PSR>>

pub fn st0(&mut self) -> ST0_W<'_>

Bit 0 - Protocol Status Flag 0

pub fn st1(&mut self) -> ST1_W<'_>

Bit 1 - Protocol Status Flag 1

pub fn st2(&mut self) -> ST2_W<'_>

Bit 2 - Protocol Status Flag 2

pub fn st3(&mut self) -> ST3_W<'_>

Bit 3 - Protocol Status Flag 3

pub fn st4(&mut self) -> ST4_W<'_>

Bit 4 - Protocol Status Flag 4

pub fn st5(&mut self) -> ST5_W<'_>

Bit 5 - Protocol Status Flag 5

pub fn st6(&mut self) -> ST6_W<'_>

Bit 6 - Protocol Status Flag 6

pub fn st7(&mut self) -> ST7_W<'_>

Bit 7 - Protocol Status Flag 7

pub fn st8(&mut self) -> ST8_W<'_>

Bit 8 - Protocol Status Flag 8

pub fn st9(&mut self) -> ST9_W<'_>

Bit 9 - Protocol Status Flag 9

pub fn rsif(&mut self) -> RSIF_W<'_>

Bit 10 - Receiver Start Indication Flag

pub fn dlif(&mut self) -> DLIF_W<'_>

Bit 11 - Data Lost Indication Flag

pub fn tsif(&mut self) -> TSIF_W<'_>

Bit 12 - Transmit Shift Indication Flag

pub fn tbif(&mut self) -> TBIF_W<'_>

Bit 13 - Transmit Buffer Indication Flag

pub fn rif(&mut self) -> RIF_W<'_>

Bit 14 - Receive Indication Flag

pub fn aif(&mut self) -> AIF_W<'_>

Bit 15 - Alternative Receive Indication Flag

pub fn brgif(&mut self) -> BRGIF_W<'_>

Bit 16 - Baud Rate Generator Indication Flag

impl W<u32, Reg<u32, _PSR_ASCMODE>>

pub fn txidle(&mut self) -> TXIDLE_W<'_>

Bit 0 - Transmission Idle

pub fn rxidle(&mut self) -> RXIDLE_W<'_>

Bit 1 - Reception Idle

pub fn sbd(&mut self) -> SBD_W<'_>

Bit 2 - Synchronization Break Detected

pub fn col(&mut self) -> COL_W<'_>

Bit 3 - Collision Detected

pub fn rns(&mut self) -> RNS_W<'_>

Bit 4 - Receiver Noise Detected

pub fn fer0(&mut self) -> FER0_W<'_>

Bit 5 - Format Error in Stop Bit 0

pub fn fer1(&mut self) -> FER1_W<'_>

Bit 6 - Format Error in Stop Bit 1

pub fn rff(&mut self) -> RFF_W<'_>

Bit 7 - Receive Frame Finished

pub fn tff(&mut self) -> TFF_W<'_>

Bit 8 - Transmitter Frame Finished

pub fn rsif(&mut self) -> RSIF_W<'_>

Bit 10 - Receiver Start Indication Flag

pub fn dlif(&mut self) -> DLIF_W<'_>

Bit 11 - Data Lost Indication Flag

pub fn tsif(&mut self) -> TSIF_W<'_>

Bit 12 - Transmit Shift Indication Flag

pub fn tbif(&mut self) -> TBIF_W<'_>

Bit 13 - Transmit Buffer Indication Flag

pub fn rif(&mut self) -> RIF_W<'_>

Bit 14 - Receive Indication Flag

pub fn aif(&mut self) -> AIF_W<'_>

Bit 15 - Alternative Receive Indication Flag

pub fn brgif(&mut self) -> BRGIF_W<'_>

Bit 16 - Baud Rate Generator Indication Flag

impl W<u32, Reg<u32, _PSR_SSCMODE>>

pub fn msls(&mut self) -> MSLS_W<'_>

Bit 0 - MSLS Status

pub fn dx2s(&mut self) -> DX2S_W<'_>

Bit 1 - DX2S Status

pub fn mslsev(&mut self) -> MSLSEV_W<'_>

Bit 2 - MSLS Event Detected

pub fn dx2tev(&mut self) -> DX2TEV_W<'_>

Bit 3 - DX2T Event Detected

pub fn parerr(&mut self) -> PARERR_W<'_>

Bit 4 - Parity Error Event Detected

pub fn rsif(&mut self) -> RSIF_W<'_>

Bit 10 - Receiver Start Indication Flag

pub fn dlif(&mut self) -> DLIF_W<'_>

Bit 11 - Data Lost Indication Flag

pub fn tsif(&mut self) -> TSIF_W<'_>

Bit 12 - Transmit Shift Indication Flag

pub fn tbif(&mut self) -> TBIF_W<'_>

Bit 13 - Transmit Buffer Indication Flag

pub fn rif(&mut self) -> RIF_W<'_>

Bit 14 - Receive Indication Flag

pub fn aif(&mut self) -> AIF_W<'_>

Bit 15 - Alternative Receive Indication Flag

pub fn brgif(&mut self) -> BRGIF_W<'_>

Bit 16 - Baud Rate Generator Indication Flag

impl W<u32, Reg<u32, _PSR_IICMODE>>

pub fn slsel(&mut self) -> SLSEL_W<'_>

Bit 0 - Slave Select

pub fn wtdf(&mut self) -> WTDF_W<'_>

Bit 1 - Wrong TDF Code Found

pub fn scr(&mut self) -> SCR_W<'_>

Bit 2 - Start Condition Received

pub fn rscr(&mut self) -> RSCR_W<'_>

Bit 3 - Repeated Start Condition Received

pub fn pcr(&mut self) -> PCR_W<'_>

Bit 4 - Stop Condition Received

pub fn nack(&mut self) -> NACK_W<'_>

Bit 5 - Non-Acknowledge Received

pub fn arl(&mut self) -> ARL_W<'_>

Bit 6 - Arbitration Lost

pub fn srr(&mut self) -> SRR_W<'_>

Bit 7 - Slave Read Request

pub fn err(&mut self) -> ERR_W<'_>

Bit 8 - Error

pub fn ack(&mut self) -> ACK_W<'_>

Bit 9 - Acknowledge Received

pub fn rsif(&mut self) -> RSIF_W<'_>

Bit 10 - Receiver Start Indication Flag

pub fn dlif(&mut self) -> DLIF_W<'_>

Bit 11 - Data Lost Indication Flag

pub fn tsif(&mut self) -> TSIF_W<'_>

Bit 12 - Transmit Shift Indication Flag

pub fn tbif(&mut self) -> TBIF_W<'_>

Bit 13 - Transmit Buffer Indication Flag

pub fn rif(&mut self) -> RIF_W<'_>

Bit 14 - Receive Indication Flag

pub fn aif(&mut self) -> AIF_W<'_>

Bit 15 - Alternative Receive Indication Flag

pub fn brgif(&mut self) -> BRGIF_W<'_>

Bit 16 - Baud Rate Generator Indication Flag

impl W<u32, Reg<u32, _PSR_IISMODE>>

pub fn wa(&mut self) -> WA_W<'_>

Bit 0 - Word Address

pub fn dx2s(&mut self) -> DX2S_W<'_>

Bit 1 - DX2S Status

pub fn dx2tev(&mut self) -> DX2TEV_W<'_>

Bit 3 - DX2T Event Detected

pub fn wafe(&mut self) -> WAFE_W<'_>

Bit 4 - WA Falling Edge Event

pub fn ware(&mut self) -> WARE_W<'_>

Bit 5 - WA Rising Edge Event

pub fn end(&mut self) -> END_W<'_>

Bit 6 - WA Generation End

pub fn rsif(&mut self) -> RSIF_W<'_>

Bit 10 - Receiver Start Indication Flag

pub fn dlif(&mut self) -> DLIF_W<'_>

Bit 11 - Data Lost Indication Flag

pub fn tsif(&mut self) -> TSIF_W<'_>

Bit 12 - Transmit Shift Indication Flag

pub fn tbif(&mut self) -> TBIF_W<'_>

Bit 13 - Transmit Buffer Indication Flag

pub fn rif(&mut self) -> RIF_W<'_>

Bit 14 - Receive Indication Flag

pub fn aif(&mut self) -> AIF_W<'_>

Bit 15 - Alternative Receive Indication Flag

pub fn brgif(&mut self) -> BRGIF_W<'_>

Bit 16 - Baud Rate Generator Indication Flag

impl W<u32, Reg<u32, _PSCR>>

pub fn cst0(&mut self) -> CST0_W<'_>

Bit 0 - Clear Status Flag 0 in PSR

pub fn cst1(&mut self) -> CST1_W<'_>

Bit 1 - Clear Status Flag 1 in PSR

pub fn cst2(&mut self) -> CST2_W<'_>

Bit 2 - Clear Status Flag 2 in PSR

pub fn cst3(&mut self) -> CST3_W<'_>

Bit 3 - Clear Status Flag 3 in PSR

pub fn cst4(&mut self) -> CST4_W<'_>

Bit 4 - Clear Status Flag 4 in PSR

pub fn cst5(&mut self) -> CST5_W<'_>

Bit 5 - Clear Status Flag 5 in PSR

pub fn cst6(&mut self) -> CST6_W<'_>

Bit 6 - Clear Status Flag 6 in PSR

pub fn cst7(&mut self) -> CST7_W<'_>

Bit 7 - Clear Status Flag 7 in PSR

pub fn cst8(&mut self) -> CST8_W<'_>

Bit 8 - Clear Status Flag 8 in PSR

pub fn cst9(&mut self) -> CST9_W<'_>

Bit 9 - Clear Status Flag 9 in PSR

pub fn crsif(&mut self) -> CRSIF_W<'_>

Bit 10 - Clear Receiver Start Indication Flag

pub fn cdlif(&mut self) -> CDLIF_W<'_>

Bit 11 - Clear Data Lost Indication Flag

pub fn ctsif(&mut self) -> CTSIF_W<'_>

Bit 12 - Clear Transmit Shift Indication Flag

pub fn ctbif(&mut self) -> CTBIF_W<'_>

Bit 13 - Clear Transmit Buffer Indication Flag

pub fn crif(&mut self) -> CRIF_W<'_>

Bit 14 - Clear Receive Indication Flag

pub fn caif(&mut self) -> CAIF_W<'_>

Bit 15 - Clear Alternative Receive Indication Flag

pub fn cbrgif(&mut self) -> CBRGIF_W<'_>

Bit 16 - Clear Baud Rate Generator Indication Flag

impl W<u32, Reg<u32, _FMR>>

pub fn mtdv(&mut self) -> MTDV_W<'_>

Bits 0:1 - Modify Transmit Data Valid

pub fn atvc(&mut self) -> ATVC_W<'_>

Bit 4 - Activate Bit TVC

pub fn crdv0(&mut self) -> CRDV0_W<'_>

Bit 14 - Clear Bits RDV for RBUF0

pub fn crdv1(&mut self) -> CRDV1_W<'_>

Bit 15 - Clear Bit RDV for RBUF1

pub fn sio0(&mut self) -> SIO0_W<'_>

Bit 16 - Set Interrupt Output SRx

pub fn sio1(&mut self) -> SIO1_W<'_>

Bit 17 - Set Interrupt Output SRx

pub fn sio2(&mut self) -> SIO2_W<'_>

Bit 18 - Set Interrupt Output SRx

pub fn sio3(&mut self) -> SIO3_W<'_>

Bit 19 - Set Interrupt Output SRx

pub fn sio4(&mut self) -> SIO4_W<'_>

Bit 20 - Set Interrupt Output SRx

pub fn sio5(&mut self) -> SIO5_W<'_>

Bit 21 - Set Interrupt Output SRx

impl W<u32, Reg<u32, _TBUF>>

pub fn tdata(&mut self) -> TDATA_W<'_>

Bits 0:15 - Transmit Data

impl W<u32, Reg<u32, _BYP>>

pub fn bdata(&mut self) -> BDATA_W<'_>

Bits 0:15 - Bypass Data

impl W<u32, Reg<u32, _BYPCR>>

pub fn bwle(&mut self) -> BWLE_W<'_>

Bits 0:3 - Bypass Word Length

pub fn bdssm(&mut self) -> BDSSM_W<'_>

Bit 8 - Bypass Data Single Shot Mode

pub fn bden(&mut self) -> BDEN_W<'_>

Bits 10:11 - Bypass Data Enable

pub fn bdvtr(&mut self) -> BDVTR_W<'_>

Bit 12 - Bypass Data Valid Trigger

pub fn bprio(&mut self) -> BPRIO_W<'_>

Bit 13 - Bypass Priority

pub fn bselo(&mut self) -> BSELO_W<'_>

Bits 16:20 - Bypass Select Outputs

pub fn bhpc(&mut self) -> BHPC_W<'_>

Bits 21:23 - Bypass Hardware Port Control

impl W<u32, Reg<u32, _TBCTR>>

pub fn dptr(&mut self) -> DPTR_W<'_>

Bits 0:5 - Data Pointer

pub fn limit(&mut self) -> LIMIT_W<'_>

Bits 8:13 - Limit For Interrupt Generation

pub fn stbtm(&mut self) -> STBTM_W<'_>

Bit 14 - Standard Transmit Buffer Trigger Mode

pub fn stbten(&mut self) -> STBTEN_W<'_>

Bit 15 - Standard Transmit Buffer Trigger Enable

pub fn stbinp(&mut self) -> STBINP_W<'_>

Bits 16:18 - Standard Transmit Buffer Interrupt Node Pointer

pub fn atbinp(&mut self) -> ATBINP_W<'_>

Bits 19:21 - Alternative Transmit Buffer Interrupt Node Pointer

pub fn size(&mut self) -> SIZE_W<'_>

Bits 24:26 - Buffer Size

pub fn lof(&mut self) -> LOF_W<'_>

Bit 28 - Buffer Event on Limit Overflow

pub fn stbien(&mut self) -> STBIEN_W<'_>

Bit 30 - Standard Transmit Buffer Interrupt Enable

pub fn tberien(&mut self) -> TBERIEN_W<'_>

Bit 31 - Transmit Buffer Error Interrupt Enable

impl W<u32, Reg<u32, _RBCTR>>

pub fn dptr(&mut self) -> DPTR_W<'_>

Bits 0:5 - Data Pointer

pub fn limit(&mut self) -> LIMIT_W<'_>

Bits 8:13 - Limit For Interrupt Generation

pub fn srbtm(&mut self) -> SRBTM_W<'_>

Bit 14 - Standard Receive Buffer Trigger Mode

pub fn srbten(&mut self) -> SRBTEN_W<'_>

Bit 15 - Standard Receive Buffer Trigger Enable

pub fn srbinp(&mut self) -> SRBINP_W<'_>

Bits 16:18 - Standard Receive Buffer Interrupt Node Pointer

pub fn arbinp(&mut self) -> ARBINP_W<'_>

Bits 19:21 - Alternative Receive Buffer Interrupt Node Pointer

pub fn rcim(&mut self) -> RCIM_W<'_>

Bits 22:23 - Receiver Control Information Mode

pub fn size(&mut self) -> SIZE_W<'_>

Bits 24:26 - Buffer Size

pub fn rnm(&mut self) -> RNM_W<'_>

Bit 27 - Receiver Notification Mode

pub fn lof(&mut self) -> LOF_W<'_>

Bit 28 - Buffer Event on Limit Overflow

pub fn arbien(&mut self) -> ARBIEN_W<'_>

Bit 29 - Alternative Receive Buffer Interrupt Enable

pub fn srbien(&mut self) -> SRBIEN_W<'_>

Bit 30 - Standard Receive Buffer Interrupt Enable

pub fn rberien(&mut self) -> RBERIEN_W<'_>

Bit 31 - Receive Buffer Error Interrupt Enable

impl W<u32, Reg<u32, _TRBSR>>

pub fn srbi(&mut self) -> SRBI_W<'_>

Bit 0 - Standard Receive Buffer Event

pub fn rberi(&mut self) -> RBERI_W<'_>

Bit 1 - Receive Buffer Error Event

pub fn arbi(&mut self) -> ARBI_W<'_>

Bit 2 - Alternative Receive Buffer Event

pub fn stbi(&mut self) -> STBI_W<'_>

Bit 8 - Standard Transmit Buffer Event

pub fn tberi(&mut self) -> TBERI_W<'_>

Bit 9 - Transmit Buffer Error Event

impl W<u32, Reg<u32, _TRBSCR>>

pub fn csrbi(&mut self) -> CSRBI_W<'_>

Bit 0 - Clear Standard Receive Buffer Event

pub fn crberi(&mut self) -> CRBERI_W<'_>

Bit 1 - Clear Receive Buffer Error Event

pub fn carbi(&mut self) -> CARBI_W<'_>

Bit 2 - Clear Alternative Receive Buffer Event

pub fn cstbi(&mut self) -> CSTBI_W<'_>

Bit 8 - Clear Standard Transmit Buffer Event

pub fn ctberi(&mut self) -> CTBERI_W<'_>

Bit 9 - Clear Transmit Buffer Error Event

pub fn cbdv(&mut self) -> CBDV_W<'_>

Bit 10 - Clear Bypass Data Valid

pub fn flushrb(&mut self) -> FLUSHRB_W<'_>

Bit 14 - Flush Receive Buffer

pub fn flushtb(&mut self) -> FLUSHTB_W<'_>

Bit 15 - Flush Transmit Buffer

impl W<u32, Reg<u32, _IN>>

pub fn tdata(&mut self) -> TDATA_W<'_>

Bits 0:15 - Transmit Data

impl W<u32, Reg<u32, _CLC>>

pub fn disr(&mut self) -> DISR_W<'_>

Bit 0 - Module Disable Request Bit

pub fn edis(&mut self) -> EDIS_W<'_>

Bit 3 - Sleep Mode Enable Control

pub fn sbwe(&mut self) -> SBWE_W<'_>

Bit 4 - Module Suspend Bit Write Enable for OCDS

impl W<u32, Reg<u32, _FDR>>

pub fn step(&mut self) -> STEP_W<'_>

Bits 0:9 - Step Value

pub fn sm(&mut self) -> SM_W<'_>

Bit 11 - Suspend Mode

pub fn sc(&mut self) -> SC_W<'_>

Bits 12:13 - Suspend Control

pub fn dm(&mut self) -> DM_W<'_>

Bits 14:15 - Divider Mode

pub fn enhw(&mut self) -> ENHW_W<'_>

Bit 30 - Enable Hardware Clock Control

pub fn disclk(&mut self) -> DISCLK_W<'_>

Bit 31 - Disable Clock

impl W<u32, Reg<u32, _MSPND>>

pub fn pnd(&mut self) -> PND_W<'_>

Bits 0:31 - Message Pending

impl W<u32, Reg<u32, _MSIMASK>>

pub fn im(&mut self) -> IM_W<'_>

Bits 0:31 - Message Index Mask

impl W<u32, Reg<u32, _PANCTR>>

pub fn pancmd(&mut self) -> PANCMD_W<'_>

Bits 0:7 - Panel Command

pub fn panar1(&mut self) -> PANAR1_W<'_>

Bits 16:23 - Panel Argument 1

pub fn panar2(&mut self) -> PANAR2_W<'_>

Bits 24:31 - Panel Argument 2

impl W<u32, Reg<u32, _MCR>>

pub fn mpsel(&mut self) -> MPSEL_W<'_>

Bits 12:15 - Message Pending Selector

impl W<u32, Reg<u32, _MITR>>

pub fn it(&mut self) -> IT_W<'_>

Bits 0:7 - Interrupt Trigger

impl W<u32, Reg<u32, _NCR>>

pub fn init(&mut self) -> INIT_W<'_>

Bit 0 - Node Initialization

pub fn trie(&mut self) -> TRIE_W<'_>

Bit 1 - Transfer Interrupt Enable

pub fn lecie(&mut self) -> LECIE_W<'_>

Bit 2 - LEC Indicated Error Interrupt Enable

pub fn alie(&mut self) -> ALIE_W<'_>

Bit 3 - Alert Interrupt Enable

pub fn candis(&mut self) -> CANDIS_W<'_>

Bit 4 - CAN Disable

pub fn cce(&mut self) -> CCE_W<'_>

Bit 6 - Configuration Change Enable

pub fn calm(&mut self) -> CALM_W<'_>

Bit 7 - CAN Analyzer Mode

pub fn susen(&mut self) -> SUSEN_W<'_>

Bit 8 - Suspend Enable

impl W<u32, Reg<u32, _NSR>>

pub fn lec(&mut self) -> LEC_W<'_>

Bits 0:2 - Last Error Code

pub fn txok(&mut self) -> TXOK_W<'_>

Bit 3 - Message Transmitted Successfully

pub fn rxok(&mut self) -> RXOK_W<'_>

Bit 4 - Message Received Successfully

pub fn alert(&mut self) -> ALERT_W<'_>

Bit 5 - Alert Warning

pub fn lle(&mut self) -> LLE_W<'_>

Bit 8 - List Length Error

pub fn loe(&mut self) -> LOE_W<'_>

Bit 9 - List Object Error

impl W<u32, Reg<u32, _NIPR>>

pub fn alinp(&mut self) -> ALINP_W<'_>

Bits 0:2 - Alert Interrupt Node Pointer

pub fn lecinp(&mut self) -> LECINP_W<'_>

Bits 4:6 - Last Error Code Interrupt Node Pointer

pub fn trinp(&mut self) -> TRINP_W<'_>

Bits 8:10 - Transfer OK Interrupt Node Pointer

pub fn cfcinp(&mut self) -> CFCINP_W<'_>

Bits 12:14 - Frame Counter Interrupt Node Pointer

impl W<u32, Reg<u32, _NPCR>>

pub fn rxsel(&mut self) -> RXSEL_W<'_>

Bits 0:2 - Receive Select

pub fn lbm(&mut self) -> LBM_W<'_>

Bit 8 - Loop-Back Mode

impl W<u32, Reg<u32, _NBTR>>

pub fn brp(&mut self) -> BRP_W<'_>

Bits 0:5 - Baud Rate Prescaler

pub fn sjw(&mut self) -> SJW_W<'_>

Bits 6:7 - (Re) Synchronization Jump Width

pub fn tseg1(&mut self) -> TSEG1_W<'_>

Bits 8:11 - Time Segment Before Sample Point

pub fn tseg2(&mut self) -> TSEG2_W<'_>

Bits 12:14 - Time Segment After Sample Point

pub fn div8(&mut self) -> DIV8_W<'_>

Bit 15 - Divide Prescaler Clock by 8

impl W<u32, Reg<u32, _NECNT>>

pub fn rec(&mut self) -> REC_W<'_>

Bits 0:7 - Receive Error Counter

pub fn tec(&mut self) -> TEC_W<'_>

Bits 8:15 - Transmit Error Counter

pub fn ewrnlvl(&mut self) -> EWRNLVL_W<'_>

Bits 16:23 - Error Warning Level

impl W<u32, Reg<u32, _NFCR>>

pub fn cfc(&mut self) -> CFC_W<'_>

Bits 0:15 - CAN Frame Counter

pub fn cfsel(&mut self) -> CFSEL_W<'_>

Bits 16:18 - CAN Frame Count Selection

pub fn cfmod(&mut self) -> CFMOD_W<'_>

Bits 19:20 - CAN Frame Counter Mode

pub fn cfcie(&mut self) -> CFCIE_W<'_>

Bit 22 - CAN Frame Count Interrupt Enable

pub fn cfcov(&mut self) -> CFCOV_W<'_>

Bit 23 - CAN Frame Counter Overflow Flag

impl W<u32, Reg<u32, _MOFCR>>

pub fn mmc(&mut self) -> MMC_W<'_>

Bits 0:3 - Message Mode Control

pub fn gdfs(&mut self) -> GDFS_W<'_>

Bit 8 - Gateway Data Frame Send

pub fn idc(&mut self) -> IDC_W<'_>

Bit 9 - Identifier Copy

pub fn dlcc(&mut self) -> DLCC_W<'_>

Bit 10 - Data Length Code Copy

pub fn datc(&mut self) -> DATC_W<'_>

Bit 11 - Data Copy

pub fn rxie(&mut self) -> RXIE_W<'_>

Bit 16 - Receive Interrupt Enable

pub fn txie(&mut self) -> TXIE_W<'_>

Bit 17 - Transmit Interrupt Enable

pub fn ovie(&mut self) -> OVIE_W<'_>

Bit 18 - Overflow Interrupt Enable

pub fn frren(&mut self) -> FRREN_W<'_>

Bit 20 - Foreign Remote Request Enable

pub fn rmm(&mut self) -> RMM_W<'_>

Bit 21 - Transmit Object Remote Monitoring

pub fn sdt(&mut self) -> SDT_W<'_>

Bit 22 - Single Data Transfer

pub fn stt(&mut self) -> STT_W<'_>

Bit 23 - Single Transmit Trial

pub fn dlc(&mut self) -> DLC_W<'_>

Bits 24:27 - Data Length Code

impl W<u32, Reg<u32, _MOFGPR>>

pub fn bot(&mut self) -> BOT_W<'_>

Bits 0:7 - Bottom Pointer

pub fn top(&mut self) -> TOP_W<'_>

Bits 8:15 - Top Pointer

pub fn cur(&mut self) -> CUR_W<'_>

Bits 16:23 - Current Object Pointer

pub fn sel(&mut self) -> SEL_W<'_>

Bits 24:31 - Object Select Pointer

impl W<u32, Reg<u32, _MOIPR>>

pub fn rxinp(&mut self) -> RXINP_W<'_>

Bits 0:2 - Receive Interrupt Node Pointer

pub fn txinp(&mut self) -> TXINP_W<'_>

Bits 4:6 - Transmit Interrupt Node Pointer

pub fn mpn(&mut self) -> MPN_W<'_>

Bits 8:15 - Message Pending Number

pub fn cfcval(&mut self) -> CFCVAL_W<'_>

Bits 16:31 - CAN Frame Counter Value

impl W<u32, Reg<u32, _MOAMR>>

pub fn am(&mut self) -> AM_W<'_>

Bits 0:28 - Acceptance Mask for Message Identifier

pub fn mide(&mut self) -> MIDE_W<'_>

Bit 29 - Acceptance Mask Bit for Message IDE Bit

impl W<u32, Reg<u32, _MODATAL>>

pub fn db0(&mut self) -> DB0_W<'_>

Bits 0:7 - Data Byte 0 of Message Object n

pub fn db1(&mut self) -> DB1_W<'_>

Bits 8:15 - Data Byte 1 of Message Object n

pub fn db2(&mut self) -> DB2_W<'_>

Bits 16:23 - Data Byte 2 of Message Object n

pub fn db3(&mut self) -> DB3_W<'_>

Bits 24:31 - Data Byte 3 of Message Object n

impl W<u32, Reg<u32, _MODATAH>>

pub fn db4(&mut self) -> DB4_W<'_>

Bits 0:7 - Data Byte 4 of Message Object n

pub fn db5(&mut self) -> DB5_W<'_>

Bits 8:15 - Data Byte 5 of Message Object n

pub fn db6(&mut self) -> DB6_W<'_>

Bits 16:23 - Data Byte 6 of Message Object n

pub fn db7(&mut self) -> DB7_W<'_>

Bits 24:31 - Data Byte 7 of Message Object n

impl W<u32, Reg<u32, _MOAR>>

pub fn id(&mut self) -> ID_W<'_>

Bits 0:28 - CAN Identifier of Message Object n

pub fn ide(&mut self) -> IDE_W<'_>

Bit 29 - Identifier Extension Bit of Message Object n

pub fn pri(&mut self) -> PRI_W<'_>

Bits 30:31 - Priority Class

impl W<u32, Reg<u32, _MOCTR>>

pub fn resrxpnd(&mut self) -> RESRXPND_W<'_>

Bit 0 - Reset/Set Receive Pending

pub fn setrxpnd(&mut self) -> SETRXPND_W<'_>

Bit 16 - Reset/Set Receive Pending

pub fn restxpnd(&mut self) -> RESTXPND_W<'_>

Bit 1 - Reset/Set Transmit Pending

pub fn settxpnd(&mut self) -> SETTXPND_W<'_>

Bit 17 - Reset/Set Transmit Pending

pub fn resrxupd(&mut self) -> RESRXUPD_W<'_>

Bit 2 - Reset/Set Receive Updating

pub fn setrxupd(&mut self) -> SETRXUPD_W<'_>

Bit 18 - Reset/Set Receive Updating

pub fn resnewdat(&mut self) -> RESNEWDAT_W<'_>

Bit 3 - Reset/Set New Data

pub fn setnewdat(&mut self) -> SETNEWDAT_W<'_>

Bit 19 - Reset/Set New Data

pub fn resmsglst(&mut self) -> RESMSGLST_W<'_>

Bit 4 - Reset/Set Message Lost

pub fn setmsglst(&mut self) -> SETMSGLST_W<'_>

Bit 20 - Reset/Set Message Lost

pub fn resmsgval(&mut self) -> RESMSGVAL_W<'_>

Bit 5 - Reset/Set Message Valid

pub fn setmsgval(&mut self) -> SETMSGVAL_W<'_>

Bit 21 - Reset/Set Message Valid

pub fn resrtsel(&mut self) -> RESRTSEL_W<'_>

Bit 6 - Reset/Set Receive/Transmit Selected

pub fn setrtsel(&mut self) -> SETRTSEL_W<'_>

Bit 22 - Reset/Set Receive/Transmit Selected

pub fn resrxen(&mut self) -> RESRXEN_W<'_>

Bit 7 - Reset/Set Receive Enable

pub fn setrxen(&mut self) -> SETRXEN_W<'_>

Bit 23 - Reset/Set Receive Enable

pub fn restxrq(&mut self) -> RESTXRQ_W<'_>

Bit 8 - Reset/Set Transmit Request

pub fn settxrq(&mut self) -> SETTXRQ_W<'_>

Bit 24 - Reset/Set Transmit Request

pub fn restxen0(&mut self) -> RESTXEN0_W<'_>

Bit 9 - Reset/Set Transmit Enable 0

pub fn settxen0(&mut self) -> SETTXEN0_W<'_>

Bit 25 - Reset/Set Transmit Enable 0

pub fn restxen1(&mut self) -> RESTXEN1_W<'_>

Bit 10 - Reset/Set Transmit Enable 1

pub fn settxen1(&mut self) -> SETTXEN1_W<'_>

Bit 26 - Reset/Set Transmit Enable 1

pub fn resdir(&mut self) -> RESDIR_W<'_>

Bit 11 - Reset/Set Message Direction

pub fn setdir(&mut self) -> SETDIR_W<'_>

Bit 27 - Reset/Set Message Direction

impl W<u32, Reg<u32, _CLC>>

pub fn disr(&mut self) -> DISR_W<'_>

Bit 0 - Module Disable Request Bit

pub fn edis(&mut self) -> EDIS_W<'_>

Bit 3 - Sleep Mode Enable Control

impl W<u32, Reg<u32, _OCS>>

pub fn tgs(&mut self) -> TGS_W<'_>

Bits 0:1 - Trigger Set for OTGB0/1

pub fn tgb(&mut self) -> TGB_W<'_>

Bit 2 - OTGB0/1 Bus Select

pub fn tg_p(&mut self) -> TG_P_W<'_>

Bit 3 - TGS, TGB Write Protection

pub fn sus(&mut self) -> SUS_W<'_>

Bits 24:27 - OCDS Suspend Control

pub fn sus_p(&mut self) -> SUS_P_W<'_>

Bit 28 - SUS Write Protection

impl W<u32, Reg<u32, _GLOBCFG>>

pub fn diva(&mut self) -> DIVA_W<'_>

Bits 0:4 - Divider Factor for the Analog Internal Clock

pub fn dcmsb(&mut self) -> DCMSB_W<'_>

Bit 7 - Double Clock for the MSB Conversion

pub fn divd(&mut self) -> DIVD_W<'_>

Bits 8:9 - Divider Factor for the Arbiter Clock

pub fn divwc(&mut self) -> DIVWC_W<'_>

Bit 15 - Write Control for Divider Parameters

pub fn dpcal0(&mut self) -> DPCAL0_W<'_>

Bit 16 - Disable Post-Calibration

pub fn dpcal1(&mut self) -> DPCAL1_W<'_>

Bit 17 - Disable Post-Calibration

pub fn dpcal2(&mut self) -> DPCAL2_W<'_>

Bit 18 - Disable Post-Calibration

pub fn dpcal3(&mut self) -> DPCAL3_W<'_>

Bit 19 - Disable Post-Calibration

pub fn sucal(&mut self) -> SUCAL_W<'_>

Bit 31 - Start-Up Calibration

impl W<u32, Reg<u32, _GLOBICLASS>>

pub fn stcs(&mut self) -> STCS_W<'_>

Bits 0:4 - Sample Time Control for Standard Conversions

pub fn cms(&mut self) -> CMS_W<'_>

Bits 8:10 - Conversion Mode for Standard Conversions

pub fn stce(&mut self) -> STCE_W<'_>

Bits 16:20 - Sample Time Control for EMUX Conversions

pub fn cme(&mut self) -> CME_W<'_>

Bits 24:26 - Conversion Mode for EMUX Conversions

impl W<u32, Reg<u32, _GLOBBOUND>>

pub fn boundary0(&mut self) -> BOUNDARY0_W<'_>

Bits 0:11 - Boundary Value 0 for Limit Checking

pub fn boundary1(&mut self) -> BOUNDARY1_W<'_>

Bits 16:27 - Boundary Value 1 for Limit Checking

impl W<u32, Reg<u32, _GLOBEFLAG>>

pub fn sevglb(&mut self) -> SEVGLB_W<'_>

Bit 0 - Source Event (Background)

pub fn revglb(&mut self) -> REVGLB_W<'_>

Bit 8 - Global Result Event

pub fn sevglbclr(&mut self) -> SEVGLBCLR_W<'_>

Bit 16 - Clear Source Event (Background)

pub fn revglbclr(&mut self) -> REVGLBCLR_W<'_>

Bit 24 - Clear Global Result Event

impl W<u32, Reg<u32, _GLOBEVNP>>

pub fn sev0np(&mut self) -> SEV0NP_W<'_>

Bits 0:3 - Service Request Node Pointer Backgr. Source

pub fn rev0np(&mut self) -> REV0NP_W<'_>

Bits 16:19 - Service Request Node Pointer Backgr. Result

impl W<u32, Reg<u32, _GLOBTF>>

pub fn cdgr(&mut self) -> CDGR_W<'_>

Bits 4:7 - Converter Diagnostics Group

pub fn cden(&mut self) -> CDEN_W<'_>

Bit 8 - Converter Diagnostics Enable

pub fn cdsel(&mut self) -> CDSEL_W<'_>

Bits 9:10 - Converter Diagnostics Pull-Devices Select

pub fn cdwc(&mut self) -> CDWC_W<'_>

Bit 15 - Write Control for Conversion Diagnostics

pub fn pdd(&mut self) -> PDD_W<'_>

Bit 16 - Pull-Down Diagnostics Enable

pub fn mdwc(&mut self) -> MDWC_W<'_>

Bit 23 - Write Control for Multiplexer Diagnostics

impl W<u32, Reg<u32, _BRSSEL>>

pub fn chselg0(&mut self) -> CHSELG0_W<'_>

Bit 0 - Channel Selection Group x

pub fn chselg1(&mut self) -> CHSELG1_W<'_>

Bit 1 - Channel Selection Group x

pub fn chselg2(&mut self) -> CHSELG2_W<'_>

Bit 2 - Channel Selection Group x

pub fn chselg3(&mut self) -> CHSELG3_W<'_>

Bit 3 - Channel Selection Group x

pub fn chselg4(&mut self) -> CHSELG4_W<'_>

Bit 4 - Channel Selection Group x

pub fn chselg5(&mut self) -> CHSELG5_W<'_>

Bit 5 - Channel Selection Group x

pub fn chselg6(&mut self) -> CHSELG6_W<'_>

Bit 6 - Channel Selection Group x

pub fn chselg7(&mut self) -> CHSELG7_W<'_>

Bit 7 - Channel Selection Group x

impl W<u32, Reg<u32, _BRSPND>>

pub fn chpndg0(&mut self) -> CHPNDG0_W<'_>

Bit 0 - Channels Pending Group x

pub fn chpndg1(&mut self) -> CHPNDG1_W<'_>

Bit 1 - Channels Pending Group x

pub fn chpndg2(&mut self) -> CHPNDG2_W<'_>

Bit 2 - Channels Pending Group x

pub fn chpndg3(&mut self) -> CHPNDG3_W<'_>

Bit 3 - Channels Pending Group x

pub fn chpndg4(&mut self) -> CHPNDG4_W<'_>

Bit 4 - Channels Pending Group x

pub fn chpndg5(&mut self) -> CHPNDG5_W<'_>

Bit 5 - Channels Pending Group x

pub fn chpndg6(&mut self) -> CHPNDG6_W<'_>

Bit 6 - Channels Pending Group x

pub fn chpndg7(&mut self) -> CHPNDG7_W<'_>

Bit 7 - Channels Pending Group x

impl W<u32, Reg<u32, _BRSCTRL>>

pub fn srcresreg(&mut self) -> SRCRESREG_W<'_>

Bits 0:3 - Source-specific Result Register

pub fn xtsel(&mut self) -> XTSEL_W<'_>

Bits 8:11 - External Trigger Input Selection

pub fn xtmode(&mut self) -> XTMODE_W<'_>

Bits 13:14 - Trigger Operating Mode

pub fn xtwc(&mut self) -> XTWC_W<'_>

Bit 15 - Write Control for Trigger Configuration

pub fn gtsel(&mut self) -> GTSEL_W<'_>

Bits 16:19 - Gate Input Selection

pub fn gtwc(&mut self) -> GTWC_W<'_>

Bit 23 - Write Control for Gate Configuration

impl W<u32, Reg<u32, _BRSMR>>

pub fn engt(&mut self) -> ENGT_W<'_>

Bits 0:1 - Enable Gate

pub fn entr(&mut self) -> ENTR_W<'_>

Bit 2 - Enable External Trigger

pub fn ensi(&mut self) -> ENSI_W<'_>

Bit 3 - Enable Source Interrupt

pub fn scan(&mut self) -> SCAN_W<'_>

Bit 4 - Autoscan Enable

pub fn ldm(&mut self) -> LDM_W<'_>

Bit 5 - Autoscan Source Load Event Mode

pub fn clrpnd(&mut self) -> CLRPND_W<'_>

Bit 8 - Clear Pending Bits

pub fn ldev(&mut self) -> LDEV_W<'_>

Bit 9 - Generate Load Event

pub fn rptdis(&mut self) -> RPTDIS_W<'_>

Bit 16 - Repeat Disable

impl W<u32, Reg<u32, _GLOBRCR>>

pub fn drctr(&mut self) -> DRCTR_W<'_>

Bits 16:19 - Data Reduction Control

pub fn wfr(&mut self) -> WFR_W<'_>

Bit 24 - Wait-for-Read Mode Enable

pub fn srgen(&mut self) -> SRGEN_W<'_>

Bit 31 - Service Request Generation Enable

impl W<u32, Reg<u32, _GLOBRES>>

pub fn result(&mut self) -> RESULT_W<'_>

Bits 0:15 - Result of most recent conversion

pub fn vf(&mut self) -> VF_W<'_>

Bit 31 - Valid Flag

impl W<u32, Reg<u32, _GLOBRESD>>

pub fn result(&mut self) -> RESULT_W<'_>

Bits 0:15 - Result of most recent conversion

pub fn vf(&mut self) -> VF_W<'_>

Bit 31 - Valid Flag

impl W<u32, Reg<u32, _EMUXSEL>>

pub fn emuxgrp0(&mut self) -> EMUXGRP0_W<'_>

Bits 0:3 - External Multiplexer Group for Interface x

pub fn emuxgrp1(&mut self) -> EMUXGRP1_W<'_>

Bits 4:7 - External Multiplexer Group for Interface x

impl W<u32, Reg<u32, _ARBCFG>>

pub fn anonc(&mut self) -> ANONC_W<'_>

Bits 0:1 - Analog Converter Control

pub fn arbrnd(&mut self) -> ARBRND_W<'_>

Bits 4:5 - Arbitration Round Length

pub fn arbm(&mut self) -> ARBM_W<'_>

Bit 7 - Arbitration Mode

impl W<u32, Reg<u32, _ARBPR>>

pub fn prio0(&mut self) -> PRIO0_W<'_>

Bits 0:1 - Priority of Request Source x

pub fn prio1(&mut self) -> PRIO1_W<'_>

Bits 4:5 - Priority of Request Source x

pub fn prio2(&mut self) -> PRIO2_W<'_>

Bits 8:9 - Priority of Request Source x

pub fn csm0(&mut self) -> CSM0_W<'_>

Bit 3 - Conversion Start Mode of Request Source x

pub fn csm1(&mut self) -> CSM1_W<'_>

Bit 7 - Conversion Start Mode of Request Source x

pub fn csm2(&mut self) -> CSM2_W<'_>

Bit 11 - Conversion Start Mode of Request Source x

pub fn asen0(&mut self) -> ASEN0_W<'_>

Bit 24 - Arbitration Slot 0 Enable

pub fn asen1(&mut self) -> ASEN1_W<'_>

Bit 25 - Arbitration Slot 1 Enable

pub fn asen2(&mut self) -> ASEN2_W<'_>

Bit 26 - Arbitration Slot 2 Enable

impl W<u32, Reg<u32, _CHASS>>

pub fn assch0(&mut self) -> ASSCH0_W<'_>

Bit 0 - Assignment for Channel 0

pub fn assch1(&mut self) -> ASSCH1_W<'_>

Bit 1 - Assignment for Channel 1

pub fn assch2(&mut self) -> ASSCH2_W<'_>

Bit 2 - Assignment for Channel 2

pub fn assch3(&mut self) -> ASSCH3_W<'_>

Bit 3 - Assignment for Channel 3

pub fn assch4(&mut self) -> ASSCH4_W<'_>

Bit 4 - Assignment for Channel 4

pub fn assch5(&mut self) -> ASSCH5_W<'_>

Bit 5 - Assignment for Channel 5

pub fn assch6(&mut self) -> ASSCH6_W<'_>

Bit 6 - Assignment for Channel 6

pub fn assch7(&mut self) -> ASSCH7_W<'_>

Bit 7 - Assignment for Channel 7

impl W<u32, Reg<u32, _ICLASS>>

pub fn stcs(&mut self) -> STCS_W<'_>

Bits 0:4 - Sample Time Control for Standard Conversions

pub fn cms(&mut self) -> CMS_W<'_>

Bits 8:10 - Conversion Mode for Standard Conversions

pub fn stce(&mut self) -> STCE_W<'_>

Bits 16:20 - Sample Time Control for EMUX Conversions

pub fn cme(&mut self) -> CME_W<'_>

Bits 24:26 - Conversion Mode for EMUX Conversions

impl W<u32, Reg<u32, _ALIAS>>

pub fn alias0(&mut self) -> ALIAS0_W<'_>

Bits 0:4 - Alias Value for CH0 Conversion Requests

pub fn alias1(&mut self) -> ALIAS1_W<'_>

Bits 8:12 - Alias Value for CH1 Conversion Requests

impl W<u32, Reg<u32, _BOUND>>

pub fn boundary0(&mut self) -> BOUNDARY0_W<'_>

Bits 0:11 - Boundary Value 0 for Limit Checking

pub fn boundary1(&mut self) -> BOUNDARY1_W<'_>

Bits 16:27 - Boundary Value 1 for Limit Checking

impl W<u32, Reg<u32, _SYNCTR>>

pub fn stsel(&mut self) -> STSEL_W<'_>

Bits 0:1 - Start Selection

pub fn evalr1(&mut self) -> EVALR1_W<'_>

Bit 4 - Evaluate Ready Input Rx

pub fn evalr2(&mut self) -> EVALR2_W<'_>

Bit 5 - Evaluate Ready Input Rx

pub fn evalr3(&mut self) -> EVALR3_W<'_>

Bit 6 - Evaluate Ready Input Rx

impl W<u32, Reg<u32, _BFL>>

pub fn bfa0(&mut self) -> BFA0_W<'_>

Bit 8 - Boundary Flag 0 Activation Select

pub fn bfa1(&mut self) -> BFA1_W<'_>

Bit 9 - Boundary Flag 1 Activation Select

pub fn bfa2(&mut self) -> BFA2_W<'_>

Bit 10 - Boundary Flag 2 Activation Select

pub fn bfa3(&mut self) -> BFA3_W<'_>

Bit 11 - Boundary Flag 3 Activation Select

pub fn bfi0(&mut self) -> BFI0_W<'_>

Bit 16 - Boundary Flag 0 Inversion Control

pub fn bfi1(&mut self) -> BFI1_W<'_>

Bit 17 - Boundary Flag 1 Inversion Control

pub fn bfi2(&mut self) -> BFI2_W<'_>

Bit 18 - Boundary Flag 2 Inversion Control

pub fn bfi3(&mut self) -> BFI3_W<'_>

Bit 19 - Boundary Flag 3 Inversion Control

impl W<u32, Reg<u32, _BFLS>>

pub fn bfc0(&mut self) -> BFC0_W<'_>

Bit 0 - Boundary Flag 0 Clear

pub fn bfc1(&mut self) -> BFC1_W<'_>

Bit 1 - Boundary Flag 1 Clear

pub fn bfc2(&mut self) -> BFC2_W<'_>

Bit 2 - Boundary Flag 2 Clear

pub fn bfc3(&mut self) -> BFC3_W<'_>

Bit 3 - Boundary Flag 3 Clear

pub fn bfs0(&mut self) -> BFS0_W<'_>

Bit 16 - Boundary Flag 0 Set

pub fn bfs1(&mut self) -> BFS1_W<'_>

Bit 17 - Boundary Flag 1 Set

pub fn bfs2(&mut self) -> BFS2_W<'_>

Bit 18 - Boundary Flag 2 Set

pub fn bfs3(&mut self) -> BFS3_W<'_>

Bit 19 - Boundary Flag 3 Set

impl W<u32, Reg<u32, _BFLC>>

pub fn bfm0(&mut self) -> BFM0_W<'_>

Bits 0:3 - Boundary Flag y Mode Control

pub fn bfm1(&mut self) -> BFM1_W<'_>

Bits 4:7 - Boundary Flag y Mode Control

pub fn bfm2(&mut self) -> BFM2_W<'_>

Bits 8:11 - Boundary Flag y Mode Control

pub fn bfm3(&mut self) -> BFM3_W<'_>

Bits 12:15 - Boundary Flag y Mode Control

impl W<u32, Reg<u32, _BFLNP>>

pub fn bfl0np(&mut self) -> BFL0NP_W<'_>

Bits 0:3 - Boundary Flag y Node Pointer

pub fn bfl1np(&mut self) -> BFL1NP_W<'_>

Bits 4:7 - Boundary Flag y Node Pointer

pub fn bfl2np(&mut self) -> BFL2NP_W<'_>

Bits 8:11 - Boundary Flag y Node Pointer

pub fn bfl3np(&mut self) -> BFL3NP_W<'_>

Bits 12:15 - Boundary Flag y Node Pointer

impl W<u32, Reg<u32, _QCTRL0>>

pub fn srcresreg(&mut self) -> SRCRESREG_W<'_>

Bits 0:3 - Source-specific Result Register

pub fn xtsel(&mut self) -> XTSEL_W<'_>

Bits 8:11 - External Trigger Input Selection

pub fn xtmode(&mut self) -> XTMODE_W<'_>

Bits 13:14 - Trigger Operating Mode

pub fn xtwc(&mut self) -> XTWC_W<'_>

Bit 15 - Write Control for Trigger Configuration

pub fn gtsel(&mut self) -> GTSEL_W<'_>

Bits 16:19 - Gate Input Selection

pub fn gtwc(&mut self) -> GTWC_W<'_>

Bit 23 - Write Control for Gate Configuration

pub fn tmen(&mut self) -> TMEN_W<'_>

Bit 28 - Timer Mode Enable

pub fn tmwc(&mut self) -> TMWC_W<'_>

Bit 31 - Write Control for Timer Mode

impl W<u32, Reg<u32, _QMR0>>

pub fn engt(&mut self) -> ENGT_W<'_>

Bits 0:1 - Enable Gate

pub fn entr(&mut self) -> ENTR_W<'_>

Bit 2 - Enable External Trigger

pub fn clrv(&mut self) -> CLRV_W<'_>

Bit 8 - Clear Valid Bit

pub fn trev(&mut self) -> TREV_W<'_>

Bit 9 - Trigger Event

pub fn flush(&mut self) -> FLUSH_W<'_>

Bit 10 - Flush Queue

pub fn cev(&mut self) -> CEV_W<'_>

Bit 11 - Clear Event Flag

pub fn rptdis(&mut self) -> RPTDIS_W<'_>

Bit 16 - Repeat Disable

impl W<u32, Reg<u32, _QINR0>>

pub fn reqchnr(&mut self) -> REQCHNR_W<'_>

Bits 0:4 - Request Channel Number

pub fn rf(&mut self) -> RF_W<'_>

Bit 5 - Refill

pub fn ensi(&mut self) -> ENSI_W<'_>

Bit 6 - Enable Source Interrupt

pub fn extr(&mut self) -> EXTR_W<'_>

Bit 7 - External Trigger

impl W<u32, Reg<u32, _ASCTRL>>

pub fn srcresreg(&mut self) -> SRCRESREG_W<'_>

Bits 0:3 - Source-specific Result Register

pub fn xtsel(&mut self) -> XTSEL_W<'_>

Bits 8:11 - External Trigger Input Selection

pub fn xtmode(&mut self) -> XTMODE_W<'_>

Bits 13:14 - Trigger Operating Mode

pub fn xtwc(&mut self) -> XTWC_W<'_>

Bit 15 - Write Control for Trigger Configuration

pub fn gtsel(&mut self) -> GTSEL_W<'_>

Bits 16:19 - Gate Input Selection

pub fn gtwc(&mut self) -> GTWC_W<'_>

Bit 23 - Write Control for Gate Configuration

pub fn tmen(&mut self) -> TMEN_W<'_>

Bit 28 - Timer Mode Enable

pub fn tmwc(&mut self) -> TMWC_W<'_>

Bit 31 - Write Control for Timer Mode

impl W<u32, Reg<u32, _ASMR>>

pub fn engt(&mut self) -> ENGT_W<'_>

Bits 0:1 - Enable Gate

pub fn entr(&mut self) -> ENTR_W<'_>

Bit 2 - Enable External Trigger

pub fn ensi(&mut self) -> ENSI_W<'_>

Bit 3 - Enable Source Interrupt

pub fn scan(&mut self) -> SCAN_W<'_>

Bit 4 - Autoscan Enable

pub fn ldm(&mut self) -> LDM_W<'_>

Bit 5 - Autoscan Source Load Event Mode

pub fn clrpnd(&mut self) -> CLRPND_W<'_>

Bit 8 - Clear Pending Bits

pub fn ldev(&mut self) -> LDEV_W<'_>

Bit 9 - Generate Load Event

pub fn rptdis(&mut self) -> RPTDIS_W<'_>

Bit 16 - Repeat Disable

impl W<u32, Reg<u32, _ASSEL>>

pub fn chsel0(&mut self) -> CHSEL0_W<'_>

Bit 0 - Channel Selection

pub fn chsel1(&mut self) -> CHSEL1_W<'_>

Bit 1 - Channel Selection

pub fn chsel2(&mut self) -> CHSEL2_W<'_>

Bit 2 - Channel Selection

pub fn chsel3(&mut self) -> CHSEL3_W<'_>

Bit 3 - Channel Selection

pub fn chsel4(&mut self) -> CHSEL4_W<'_>

Bit 4 - Channel Selection

pub fn chsel5(&mut self) -> CHSEL5_W<'_>

Bit 5 - Channel Selection

pub fn chsel6(&mut self) -> CHSEL6_W<'_>

Bit 6 - Channel Selection

pub fn chsel7(&mut self) -> CHSEL7_W<'_>

Bit 7 - Channel Selection

impl W<u32, Reg<u32, _ASPND>>

pub fn chpnd0(&mut self) -> CHPND0_W<'_>

Bit 0 - Channels Pending

pub fn chpnd1(&mut self) -> CHPND1_W<'_>

Bit 1 - Channels Pending

pub fn chpnd2(&mut self) -> CHPND2_W<'_>

Bit 2 - Channels Pending

pub fn chpnd3(&mut self) -> CHPND3_W<'_>

Bit 3 - Channels Pending

pub fn chpnd4(&mut self) -> CHPND4_W<'_>

Bit 4 - Channels Pending

pub fn chpnd5(&mut self) -> CHPND5_W<'_>

Bit 5 - Channels Pending

pub fn chpnd6(&mut self) -> CHPND6_W<'_>

Bit 6 - Channels Pending

pub fn chpnd7(&mut self) -> CHPND7_W<'_>

Bit 7 - Channels Pending

impl W<u32, Reg<u32, _CEFLAG>>

pub fn cev0(&mut self) -> CEV0_W<'_>

Bit 0 - Channel Event for Channel 0

pub fn cev1(&mut self) -> CEV1_W<'_>

Bit 1 - Channel Event for Channel 1

pub fn cev2(&mut self) -> CEV2_W<'_>

Bit 2 - Channel Event for Channel 2

pub fn cev3(&mut self) -> CEV3_W<'_>

Bit 3 - Channel Event for Channel 3

pub fn cev4(&mut self) -> CEV4_W<'_>

Bit 4 - Channel Event for Channel 4

pub fn cev5(&mut self) -> CEV5_W<'_>

Bit 5 - Channel Event for Channel 5

pub fn cev6(&mut self) -> CEV6_W<'_>

Bit 6 - Channel Event for Channel 6

pub fn cev7(&mut self) -> CEV7_W<'_>

Bit 7 - Channel Event for Channel 7

impl W<u32, Reg<u32, _REFLAG>>

pub fn rev0(&mut self) -> REV0_W<'_>

Bit 0 - Result Event for Result Register 0

pub fn rev1(&mut self) -> REV1_W<'_>

Bit 1 - Result Event for Result Register 1

pub fn rev2(&mut self) -> REV2_W<'_>

Bit 2 - Result Event for Result Register 2

pub fn rev3(&mut self) -> REV3_W<'_>

Bit 3 - Result Event for Result Register 3

pub fn rev4(&mut self) -> REV4_W<'_>

Bit 4 - Result Event for Result Register 4

pub fn rev5(&mut self) -> REV5_W<'_>

Bit 5 - Result Event for Result Register 5

pub fn rev6(&mut self) -> REV6_W<'_>

Bit 6 - Result Event for Result Register 6

pub fn rev7(&mut self) -> REV7_W<'_>

Bit 7 - Result Event for Result Register 7

pub fn rev8(&mut self) -> REV8_W<'_>

Bit 8 - Result Event for Result Register 8

pub fn rev9(&mut self) -> REV9_W<'_>

Bit 9 - Result Event for Result Register 9

pub fn rev10(&mut self) -> REV10_W<'_>

Bit 10 - Result Event for Result Register 10

pub fn rev11(&mut self) -> REV11_W<'_>

Bit 11 - Result Event for Result Register 11

pub fn rev12(&mut self) -> REV12_W<'_>

Bit 12 - Result Event for Result Register 12

pub fn rev13(&mut self) -> REV13_W<'_>

Bit 13 - Result Event for Result Register 13

pub fn rev14(&mut self) -> REV14_W<'_>

Bit 14 - Result Event for Result Register 14

pub fn rev15(&mut self) -> REV15_W<'_>

Bit 15 - Result Event for Result Register 15

impl W<u32, Reg<u32, _SEFLAG>>

pub fn sev0(&mut self) -> SEV0_W<'_>

Bit 0 - Source Event 0/1

pub fn sev1(&mut self) -> SEV1_W<'_>

Bit 1 - Source Event 0/1

impl W<u32, Reg<u32, _CEFCLR>>

pub fn cev0(&mut self) -> CEV0_W<'_>

Bit 0 - Clear Channel Event for Channel 0

pub fn cev1(&mut self) -> CEV1_W<'_>

Bit 1 - Clear Channel Event for Channel 1

pub fn cev2(&mut self) -> CEV2_W<'_>

Bit 2 - Clear Channel Event for Channel 2

pub fn cev3(&mut self) -> CEV3_W<'_>

Bit 3 - Clear Channel Event for Channel 3

pub fn cev4(&mut self) -> CEV4_W<'_>

Bit 4 - Clear Channel Event for Channel 4

pub fn cev5(&mut self) -> CEV5_W<'_>

Bit 5 - Clear Channel Event for Channel 5

pub fn cev6(&mut self) -> CEV6_W<'_>

Bit 6 - Clear Channel Event for Channel 6

pub fn cev7(&mut self) -> CEV7_W<'_>

Bit 7 - Clear Channel Event for Channel 7

impl W<u32, Reg<u32, _REFCLR>>

pub fn rev0(&mut self) -> REV0_W<'_>

Bit 0 - Clear Result Event for Result Register 0

pub fn rev1(&mut self) -> REV1_W<'_>

Bit 1 - Clear Result Event for Result Register 1

pub fn rev2(&mut self) -> REV2_W<'_>

Bit 2 - Clear Result Event for Result Register 2

pub fn rev3(&mut self) -> REV3_W<'_>

Bit 3 - Clear Result Event for Result Register 3

pub fn rev4(&mut self) -> REV4_W<'_>

Bit 4 - Clear Result Event for Result Register 4

pub fn rev5(&mut self) -> REV5_W<'_>

Bit 5 - Clear Result Event for Result Register 5

pub fn rev6(&mut self) -> REV6_W<'_>

Bit 6 - Clear Result Event for Result Register 6

pub fn rev7(&mut self) -> REV7_W<'_>

Bit 7 - Clear Result Event for Result Register 7

pub fn rev8(&mut self) -> REV8_W<'_>

Bit 8 - Clear Result Event for Result Register 8

pub fn rev9(&mut self) -> REV9_W<'_>

Bit 9 - Clear Result Event for Result Register 9

pub fn rev10(&mut self) -> REV10_W<'_>

Bit 10 - Clear Result Event for Result Register 10

pub fn rev11(&mut self) -> REV11_W<'_>

Bit 11 - Clear Result Event for Result Register 11

pub fn rev12(&mut self) -> REV12_W<'_>

Bit 12 - Clear Result Event for Result Register 12

pub fn rev13(&mut self) -> REV13_W<'_>

Bit 13 - Clear Result Event for Result Register 13

pub fn rev14(&mut self) -> REV14_W<'_>

Bit 14 - Clear Result Event for Result Register 14

pub fn rev15(&mut self) -> REV15_W<'_>

Bit 15 - Clear Result Event for Result Register 15

impl W<u32, Reg<u32, _SEFCLR>>

pub fn sev0(&mut self) -> SEV0_W<'_>

Bit 0 - Clear Source Event 0/1

pub fn sev1(&mut self) -> SEV1_W<'_>

Bit 1 - Clear Source Event 0/1

impl W<u32, Reg<u32, _CEVNP0>>

pub fn cev0np(&mut self) -> CEV0NP_W<'_>

Bits 0:3 - Service Request Node Pointer Channel Event i

pub fn cev1np(&mut self) -> CEV1NP_W<'_>

Bits 4:7 - Service Request Node Pointer Channel Event i

pub fn cev2np(&mut self) -> CEV2NP_W<'_>

Bits 8:11 - Service Request Node Pointer Channel Event i

pub fn cev3np(&mut self) -> CEV3NP_W<'_>

Bits 12:15 - Service Request Node Pointer Channel Event i

pub fn cev4np(&mut self) -> CEV4NP_W<'_>

Bits 16:19 - Service Request Node Pointer Channel Event i

pub fn cev5np(&mut self) -> CEV5NP_W<'_>

Bits 20:23 - Service Request Node Pointer Channel Event i

pub fn cev6np(&mut self) -> CEV6NP_W<'_>

Bits 24:27 - Service Request Node Pointer Channel Event i

pub fn cev7np(&mut self) -> CEV7NP_W<'_>

Bits 28:31 - Service Request Node Pointer Channel Event i

impl W<u32, Reg<u32, _REVNP0>>

pub fn rev0np(&mut self) -> REV0NP_W<'_>

Bits 0:3 - Service Request Node Pointer Result Event i

pub fn rev1np(&mut self) -> REV1NP_W<'_>

Bits 4:7 - Service Request Node Pointer Result Event i

pub fn rev2np(&mut self) -> REV2NP_W<'_>

Bits 8:11 - Service Request Node Pointer Result Event i

pub fn rev3np(&mut self) -> REV3NP_W<'_>

Bits 12:15 - Service Request Node Pointer Result Event i

pub fn rev4np(&mut self) -> REV4NP_W<'_>

Bits 16:19 - Service Request Node Pointer Result Event i

pub fn rev5np(&mut self) -> REV5NP_W<'_>

Bits 20:23 - Service Request Node Pointer Result Event i

pub fn rev6np(&mut self) -> REV6NP_W<'_>

Bits 24:27 - Service Request Node Pointer Result Event i

pub fn rev7np(&mut self) -> REV7NP_W<'_>

Bits 28:31 - Service Request Node Pointer Result Event i

impl W<u32, Reg<u32, _REVNP1>>

pub fn rev8np(&mut self) -> REV8NP_W<'_>

Bits 0:3 - Service Request Node Pointer Result Event i

pub fn rev9np(&mut self) -> REV9NP_W<'_>

Bits 4:7 - Service Request Node Pointer Result Event i

pub fn rev10np(&mut self) -> REV10NP_W<'_>

Bits 8:11 - Service Request Node Pointer Result Event i

pub fn rev11np(&mut self) -> REV11NP_W<'_>

Bits 12:15 - Service Request Node Pointer Result Event i

pub fn rev12np(&mut self) -> REV12NP_W<'_>

Bits 16:19 - Service Request Node Pointer Result Event i

pub fn rev13np(&mut self) -> REV13NP_W<'_>

Bits 20:23 - Service Request Node Pointer Result Event i

pub fn rev14np(&mut self) -> REV14NP_W<'_>

Bits 24:27 - Service Request Node Pointer Result Event i

pub fn rev15np(&mut self) -> REV15NP_W<'_>

Bits 28:31 - Service Request Node Pointer Result Event i

impl W<u32, Reg<u32, _SEVNP>>

pub fn sev0np(&mut self) -> SEV0NP_W<'_>

Bits 0:3 - Service Request Node Pointer Source Event i

pub fn sev1np(&mut self) -> SEV1NP_W<'_>

Bits 4:7 - Service Request Node Pointer Source Event i

impl W<u32, Reg<u32, _SRACT>>

pub fn agsr0(&mut self) -> AGSR0_W<'_>

Bit 0 - Activate Group Service Request Node 0

pub fn agsr1(&mut self) -> AGSR1_W<'_>

Bit 1 - Activate Group Service Request Node 1

pub fn agsr2(&mut self) -> AGSR2_W<'_>

Bit 2 - Activate Group Service Request Node 2

pub fn agsr3(&mut self) -> AGSR3_W<'_>

Bit 3 - Activate Group Service Request Node 3

pub fn assr0(&mut self) -> ASSR0_W<'_>

Bit 8 - Activate Shared Service Request Node 0

pub fn assr1(&mut self) -> ASSR1_W<'_>

Bit 9 - Activate Shared Service Request Node 1

pub fn assr2(&mut self) -> ASSR2_W<'_>

Bit 10 - Activate Shared Service Request Node 2

pub fn assr3(&mut self) -> ASSR3_W<'_>

Bit 11 - Activate Shared Service Request Node 3

impl W<u32, Reg<u32, _EMUXCTR>>

pub fn emuxset(&mut self) -> EMUXSET_W<'_>

Bits 0:2 - External Multiplexer Start Selection

pub fn emuxch(&mut self) -> EMUXCH_W<'_>

Bits 16:25 - External Multiplexer Channel Select

pub fn emuxmode(&mut self) -> EMUXMODE_W<'_>

Bits 26:27 - External Multiplexer Mode

pub fn emxcod(&mut self) -> EMXCOD_W<'_>

Bit 28 - External Multiplexer Coding Scheme

pub fn emxst(&mut self) -> EMXST_W<'_>

Bit 29 - External Multiplexer Sample Time Control

pub fn emxwc(&mut self) -> EMXWC_W<'_>

Bit 31 - Write Control for EMUX Configuration

impl W<u32, Reg<u32, _VFR>>

pub fn vf0(&mut self) -> VF0_W<'_>

Bit 0 - Valid Flag of Result Register x

pub fn vf1(&mut self) -> VF1_W<'_>

Bit 1 - Valid Flag of Result Register x

pub fn vf2(&mut self) -> VF2_W<'_>

Bit 2 - Valid Flag of Result Register x

pub fn vf3(&mut self) -> VF3_W<'_>

Bit 3 - Valid Flag of Result Register x

pub fn vf4(&mut self) -> VF4_W<'_>

Bit 4 - Valid Flag of Result Register x

pub fn vf5(&mut self) -> VF5_W<'_>

Bit 5 - Valid Flag of Result Register x

pub fn vf6(&mut self) -> VF6_W<'_>

Bit 6 - Valid Flag of Result Register x

pub fn vf7(&mut self) -> VF7_W<'_>

Bit 7 - Valid Flag of Result Register x

pub fn vf8(&mut self) -> VF8_W<'_>

Bit 8 - Valid Flag of Result Register x

pub fn vf9(&mut self) -> VF9_W<'_>

Bit 9 - Valid Flag of Result Register x

pub fn vf10(&mut self) -> VF10_W<'_>

Bit 10 - Valid Flag of Result Register x

pub fn vf11(&mut self) -> VF11_W<'_>

Bit 11 - Valid Flag of Result Register x

pub fn vf12(&mut self) -> VF12_W<'_>

Bit 12 - Valid Flag of Result Register x

pub fn vf13(&mut self) -> VF13_W<'_>

Bit 13 - Valid Flag of Result Register x

pub fn vf14(&mut self) -> VF14_W<'_>

Bit 14 - Valid Flag of Result Register x

pub fn vf15(&mut self) -> VF15_W<'_>

Bit 15 - Valid Flag of Result Register x

impl W<u32, Reg<u32, _CHCTR>>

pub fn iclsel(&mut self) -> ICLSEL_W<'_>

Bits 0:1 - Input Class Select

pub fn bndsell(&mut self) -> BNDSELL_W<'_>

Bits 4:5 - Lower Boundary Select

pub fn bndselu(&mut self) -> BNDSELU_W<'_>

Bits 6:7 - Upper Boundary Select

pub fn chevmode(&mut self) -> CHEVMODE_W<'_>

Bits 8:9 - Channel Event Mode

pub fn sync(&mut self) -> SYNC_W<'_>

Bit 10 - Synchronization Request

pub fn refsel(&mut self) -> REFSEL_W<'_>

Bit 11 - Reference Input Selection

pub fn resreg(&mut self) -> RESREG_W<'_>

Bits 16:19 - Result Register

pub fn restbs(&mut self) -> RESTBS_W<'_>

Bit 20 - Result Target for Background Source

pub fn respos(&mut self) -> RESPOS_W<'_>

Bit 21 - Result Position

pub fn bwdch(&mut self) -> BWDCH_W<'_>

Bits 28:29 - Broken Wire Detection Channel

pub fn bwden(&mut self) -> BWDEN_W<'_>

Bit 30 - Broken Wire Detection Enable

impl W<u32, Reg<u32, _RCR>>

pub fn drctr(&mut self) -> DRCTR_W<'_>

Bits 16:19 - Data Reduction Control

pub fn dmm(&mut self) -> DMM_W<'_>

Bits 20:21 - Data Modification Mode

pub fn wfr(&mut self) -> WFR_W<'_>

Bit 24 - Wait-for-Read Mode Enable

pub fn fen(&mut self) -> FEN_W<'_>

Bits 25:26 - FIFO Mode Enable

pub fn srgen(&mut self) -> SRGEN_W<'_>

Bit 31 - Service Request Generation Enable

impl W<u32, Reg<u32, _RES>>

pub fn result(&mut self) -> RESULT_W<'_>

Bits 0:15 - Result of Most Recent Conversion

impl W<u32, Reg<u32, _DAC0CFG0>>

pub fn freq(&mut self) -> FREQ_W<'_>

Bits 0:19 - Integer Frequency Divider Value

pub fn mode(&mut self) -> MODE_W<'_>

Bits 20:22 - Enables and Sets the Mode for DAC0

pub fn sign(&mut self) -> SIGN_W<'_>

Bit 23 - Selects Between Signed and Unsigned DAC0 Mode

pub fn negate(&mut self) -> NEGATE_W<'_>

Bit 28 - Negates the DAC0 output

pub fn signen(&mut self) -> SIGNEN_W<'_>

Bit 29 - Enable Sign Output of DAC0 Pattern Generator

pub fn sren(&mut self) -> SREN_W<'_>

Bit 30 - Enable DAC0 service request interrupt generation

impl W<u32, Reg<u32, _DAC0CFG1>>

pub fn scale(&mut self) -> SCALE_W<'_>

Bits 0:2 - Scale value for up- or downscale of the DAC0 input data in steps by the power of 2 (=shift operation)

pub fn muldiv(&mut self) -> MULDIV_W<'_>

Bit 3 - Switch between up- and downscale of the DAC0 input data values

pub fn offs(&mut self) -> OFFS_W<'_>

Bits 4:11 - 8-bit offset value addition

pub fn trigsel(&mut self) -> TRIGSEL_W<'_>

Bits 12:14 - Selects one of the eight external trigger sources for DAC0

pub fn datmod(&mut self) -> DATMOD_W<'_>

Bit 15 - Switch between independent or simultaneous DAC mode and select the input data register for DAC0 and DAC1

pub fn swtrig(&mut self) -> SWTRIG_W<'_>

Bit 16 - Software Trigger

pub fn trigmod(&mut self) -> TRIGMOD_W<'_>

Bits 17:18 - Select the trigger source for channel 0

pub fn anacfg(&mut self) -> ANACFG_W<'_>

Bits 19:23 - DAC0 analog configuration/calibration parameters

pub fn anaen(&mut self) -> ANAEN_W<'_>

Bit 24 - Enable analog DAC for channel 0

pub fn refcfgl(&mut self) -> REFCFGL_W<'_>

Bits 28:31 - Lower 4 band-gap configuration/calibration parameters

impl W<u32, Reg<u32, _DAC1CFG0>>

pub fn freq(&mut self) -> FREQ_W<'_>

Bits 0:19 - Integer Frequency Divider Value

pub fn mode(&mut self) -> MODE_W<'_>

Bits 20:22 - Enables and sets the Mode for DAC1

pub fn sign(&mut self) -> SIGN_W<'_>

Bit 23 - Selects between signed and unsigned DAC1 mode

pub fn negate(&mut self) -> NEGATE_W<'_>

Bit 28 - Negates the DAC1 output

pub fn signen(&mut self) -> SIGNEN_W<'_>

Bit 29 - Enable sign output of DAC1 pattern generator

pub fn sren(&mut self) -> SREN_W<'_>

Bit 30 - Enable DAC1 service request interrupt generation

impl W<u32, Reg<u32, _DAC1CFG1>>

pub fn scale(&mut self) -> SCALE_W<'_>

Bits 0:2 - Scale value for up- or downscale of the DAC1 input data in steps by the power of 2 (=shift operation)

pub fn muldiv(&mut self) -> MULDIV_W<'_>

Bit 3 - Switch between up- and downscale of the DAC1 input data values

pub fn offs(&mut self) -> OFFS_W<'_>

Bits 4:11 - 8-bit offset value addition

pub fn trigsel(&mut self) -> TRIGSEL_W<'_>

Bits 12:14 - Selects one of the eight external trigger sources for DAC1

pub fn swtrig(&mut self) -> SWTRIG_W<'_>

Bit 16 - Software Trigger

pub fn trigmod(&mut self) -> TRIGMOD_W<'_>

Bits 17:18 - Select the trigger source for channel 1

pub fn anacfg(&mut self) -> ANACFG_W<'_>

Bits 19:23 - DAC1 analog configuration/calibration parameters

pub fn anaen(&mut self) -> ANAEN_W<'_>

Bit 24 - Enable analog DAC for channel 1

pub fn refcfgh(&mut self) -> REFCFGH_W<'_>

Bits 28:31 - Higher 4 band-gap configuration/calibration parameters

impl W<u32, Reg<u32, _DAC0DATA>>

pub fn data0(&mut self) -> DATA0_W<'_>

Bits 0:11 - DAC0 Data Bits

impl W<u32, Reg<u32, _DAC1DATA>>

pub fn data1(&mut self) -> DATA1_W<'_>

Bits 0:11 - DAC1 Data Bits

impl W<u32, Reg<u32, _DAC01DATA>>

pub fn data0(&mut self) -> DATA0_W<'_>

Bits 0:11 - DAC0 Data Bits

pub fn data1(&mut self) -> DATA1_W<'_>

Bits 16:27 - DAC1 Data Bits

impl W<u32, Reg<u32, _DAC0PATL>>

pub fn pat0(&mut self) -> PAT0_W<'_>

Bits 0:4 - Pattern Number 0 for PATGEN of DAC0

pub fn pat1(&mut self) -> PAT1_W<'_>

Bits 5:9 - Pattern Number 1 for PATGEN of DAC0

pub fn pat2(&mut self) -> PAT2_W<'_>

Bits 10:14 - Pattern Number 2 for PATGEN of DAC0

pub fn pat3(&mut self) -> PAT3_W<'_>

Bits 15:19 - Pattern Number 3 for PATGEN of DAC0

pub fn pat4(&mut self) -> PAT4_W<'_>

Bits 20:24 - Pattern Number 4 for PATGEN of DAC0

pub fn pat5(&mut self) -> PAT5_W<'_>

Bits 25:29 - Pattern Number 5 for PATGEN of DAC0

impl W<u32, Reg<u32, _DAC0PATH>>

pub fn pat6(&mut self) -> PAT6_W<'_>

Bits 0:4 - Pattern Number 6 for PATGEN of DAC0

pub fn pat7(&mut self) -> PAT7_W<'_>

Bits 5:9 - Pattern Number 7 for PATGEN of DAC0

pub fn pat8(&mut self) -> PAT8_W<'_>

Bits 10:14 - Pattern Number 8 for PATGEN of DAC0

impl W<u32, Reg<u32, _DAC1PATL>>

pub fn pat0(&mut self) -> PAT0_W<'_>

Bits 0:4 - Pattern Number 0 for PATGEN of DAC1

pub fn pat1(&mut self) -> PAT1_W<'_>

Bits 5:9 - Pattern Number 1 for PATGEN of DAC1

pub fn pat2(&mut self) -> PAT2_W<'_>

Bits 10:14 - Pattern Number 2 for PATGEN of DAC1

pub fn pat3(&mut self) -> PAT3_W<'_>

Bits 15:19 - Pattern Number 3 for PATGEN of DAC1

pub fn pat4(&mut self) -> PAT4_W<'_>

Bits 20:24 - Pattern Number 4 for PATGEN of DAC1

pub fn pat5(&mut self) -> PAT5_W<'_>

Bits 25:29 - Pattern Number 5 for PATGEN of DAC1

impl W<u32, Reg<u32, _DAC1PATH>>

pub fn pat6(&mut self) -> PAT6_W<'_>

Bits 0:4 - Pattern Number 6 for PATGEN of DAC1

pub fn pat7(&mut self) -> PAT7_W<'_>

Bits 5:9 - Pattern Number 7 for PATGEN of DAC1

pub fn pat8(&mut self) -> PAT8_W<'_>

Bits 10:14 - Pattern Number 8 for PATGEN of DAC1

impl W<u32, Reg<u32, _GCTRL>>

pub fn prbc(&mut self) -> PRBC_W<'_>

Bits 0:2 - Prescaler Clear Configuration

pub fn pcis(&mut self) -> PCIS_W<'_>

Bits 4:5 - Prescaler Input Clock Selection

pub fn suscfg(&mut self) -> SUSCFG_W<'_>

Bits 8:9 - Suspend Mode Configuration

pub fn mse0(&mut self) -> MSE0_W<'_>

Bit 10 - Slice 0 Multi Channel shadow transfer enable

pub fn mse1(&mut self) -> MSE1_W<'_>

Bit 11 - Slice 1 Multi Channel shadow transfer enable

pub fn mse2(&mut self) -> MSE2_W<'_>

Bit 12 - Slice 2 Multi Channel shadow transfer enable

pub fn mse3(&mut self) -> MSE3_W<'_>

Bit 13 - Slice 3 Multi Channel shadow transfer enable

pub fn msde(&mut self) -> MSDE_W<'_>

Bits 14:15 - Multi Channel shadow transfer request configuration

impl W<u32, Reg<u32, _GIDLS>>

pub fn ss0i(&mut self) -> SS0I_W<'_>

Bit 0 - CC40 IDLE mode set

pub fn ss1i(&mut self) -> SS1I_W<'_>

Bit 1 - CC41 IDLE mode set

pub fn ss2i(&mut self) -> SS2I_W<'_>

Bit 2 - CC42 IDLE mode set

pub fn ss3i(&mut self) -> SS3I_W<'_>

Bit 3 - CC43 IDLE mode set

pub fn cprb(&mut self) -> CPRB_W<'_>

Bit 8 - Prescaler Run Bit Clear

pub fn psic(&mut self) -> PSIC_W<'_>

Bit 9 - Prescaler clear

impl W<u32, Reg<u32, _GIDLC>>

pub fn cs0i(&mut self) -> CS0I_W<'_>

Bit 0 - CC40 IDLE mode clear

pub fn cs1i(&mut self) -> CS1I_W<'_>

Bit 1 - CC41 IDLE mode clear

pub fn cs2i(&mut self) -> CS2I_W<'_>

Bit 2 - CC42 IDLE mode clear

pub fn cs3i(&mut self) -> CS3I_W<'_>

Bit 3 - CC43 IDLE mode clear

pub fn sprb(&mut self) -> SPRB_W<'_>

Bit 8 - Prescaler Run Bit Set

impl W<u32, Reg<u32, _GCSS>>

pub fn s0se(&mut self) -> S0SE_W<'_>

Bit 0 - Slice 0 shadow transfer set enable

pub fn s0dse(&mut self) -> S0DSE_W<'_>

Bit 1 - Slice 0 Dither shadow transfer set enable

pub fn s0pse(&mut self) -> S0PSE_W<'_>

Bit 2 - Slice 0 Prescaler shadow transfer set enable

pub fn s1se(&mut self) -> S1SE_W<'_>

Bit 4 - Slice 1 shadow transfer set enable

pub fn s1dse(&mut self) -> S1DSE_W<'_>

Bit 5 - Slice 1 Dither shadow transfer set enable

pub fn s1pse(&mut self) -> S1PSE_W<'_>

Bit 6 - Slice 1 Prescaler shadow transfer set enable

pub fn s2se(&mut self) -> S2SE_W<'_>

Bit 8 - Slice 2 shadow transfer set enable

pub fn s2dse(&mut self) -> S2DSE_W<'_>

Bit 9 - Slice 2 Dither shadow transfer set enable

pub fn s2pse(&mut self) -> S2PSE_W<'_>

Bit 10 - Slice 2 Prescaler shadow transfer set enable

pub fn s3se(&mut self) -> S3SE_W<'_>

Bit 12 - Slice 3 shadow transfer set enable

pub fn s3dse(&mut self) -> S3DSE_W<'_>

Bit 13 - Slice 3 Dither shadow transfer set enable

pub fn s3pse(&mut self) -> S3PSE_W<'_>

Bit 14 - Slice 3 Prescaler shadow transfer set enable

pub fn s0sts(&mut self) -> S0STS_W<'_>

Bit 16 - Slice 0 status bit set

pub fn s1sts(&mut self) -> S1STS_W<'_>

Bit 17 - Slice 1 status bit set

pub fn s2sts(&mut self) -> S2STS_W<'_>

Bit 18 - Slice 2 status bit set

pub fn s3sts(&mut self) -> S3STS_W<'_>

Bit 19 - Slice 3 status bit set

impl W<u32, Reg<u32, _GCSC>>

pub fn s0sc(&mut self) -> S0SC_W<'_>

Bit 0 - Slice 0 shadow transfer clear

pub fn s0dsc(&mut self) -> S0DSC_W<'_>

Bit 1 - Slice 0 Dither shadow transfer clear

pub fn s0psc(&mut self) -> S0PSC_W<'_>

Bit 2 - Slice 0 Prescaler shadow transfer clear

pub fn s1sc(&mut self) -> S1SC_W<'_>

Bit 4 - Slice 1 shadow transfer clear

pub fn s1dsc(&mut self) -> S1DSC_W<'_>

Bit 5 - Slice 1 Dither shadow transfer clear

pub fn s1psc(&mut self) -> S1PSC_W<'_>

Bit 6 - Slice 1 Prescaler shadow transfer clear

pub fn s2sc(&mut self) -> S2SC_W<'_>

Bit 8 - Slice 2 shadow transfer clear

pub fn s2dsc(&mut self) -> S2DSC_W<'_>

Bit 9 - Slice 2 Dither shadow transfer clear

pub fn s2psc(&mut self) -> S2PSC_W<'_>

Bit 10 - Slice 2 Prescaler shadow transfer clear

pub fn s3sc(&mut self) -> S3SC_W<'_>

Bit 12 - Slice 3 shadow transfer clear

pub fn s3dsc(&mut self) -> S3DSC_W<'_>

Bit 13 - Slice 3 Dither shadow transfer clear

pub fn s3psc(&mut self) -> S3PSC_W<'_>

Bit 14 - Slice 3 Prescaler shadow transfer clear

pub fn s0stc(&mut self) -> S0STC_W<'_>

Bit 16 - Slice 0 status bit clear

pub fn s1stc(&mut self) -> S1STC_W<'_>

Bit 17 - Slice 1 status bit clear

pub fn s2stc(&mut self) -> S2STC_W<'_>

Bit 18 - Slice 2 status bit clear

pub fn s3stc(&mut self) -> S3STC_W<'_>

Bit 19 - Slice 3 status bit clear

impl W<u32, Reg<u32, _INS>>

pub fn ev0is(&mut self) -> EV0IS_W<'_>

Bits 0:3 - Event 0 signal selection

pub fn ev1is(&mut self) -> EV1IS_W<'_>

Bits 4:7 - Event 1 signal selection

pub fn ev2is(&mut self) -> EV2IS_W<'_>

Bits 8:11 - Event 2 signal selection

pub fn ev0em(&mut self) -> EV0EM_W<'_>

Bits 16:17 - Event 0 Edge Selection

pub fn ev1em(&mut self) -> EV1EM_W<'_>

Bits 18:19 - Event 1 Edge Selection

pub fn ev2em(&mut self) -> EV2EM_W<'_>

Bits 20:21 - Event 2 Edge Selection

pub fn ev0lm(&mut self) -> EV0LM_W<'_>

Bit 22 - Event 0 Level Selection

pub fn ev1lm(&mut self) -> EV1LM_W<'_>

Bit 23 - Event 1 Level Selection

pub fn ev2lm(&mut self) -> EV2LM_W<'_>

Bit 24 - Event 2 Level Selection

pub fn lpf0m(&mut self) -> LPF0M_W<'_>

Bits 25:26 - Event 0 Low Pass Filter Configuration

pub fn lpf1m(&mut self) -> LPF1M_W<'_>

Bits 27:28 - Event 1 Low Pass Filter Configuration

pub fn lpf2m(&mut self) -> LPF2M_W<'_>

Bits 29:30 - Event 2 Low Pass Filter Configuration

impl W<u32, Reg<u32, _CMC>>

pub fn strts(&mut self) -> STRTS_W<'_>

Bits 0:1 - External Start Functionality Selector

pub fn ends(&mut self) -> ENDS_W<'_>

Bits 2:3 - External Stop Functionality Selector

pub fn cap0s(&mut self) -> CAP0S_W<'_>

Bits 4:5 - External Capture 0 Functionality Selector

pub fn cap1s(&mut self) -> CAP1S_W<'_>

Bits 6:7 - External Capture 1 Functionality Selector

pub fn gates(&mut self) -> GATES_W<'_>

Bits 8:9 - External Gate Functionality Selector

pub fn uds(&mut self) -> UDS_W<'_>

Bits 10:11 - External Up/Down Functionality Selector

pub fn lds(&mut self) -> LDS_W<'_>

Bits 12:13 - External Timer Load Functionality Selector

pub fn cnts(&mut self) -> CNTS_W<'_>

Bits 14:15 - External Count Selector

pub fn ofs(&mut self) -> OFS_W<'_>

Bit 16 - Override Function Selector

pub fn ts(&mut self) -> TS_W<'_>

Bit 17 - Trap Function Selector

pub fn mos(&mut self) -> MOS_W<'_>

Bits 18:19 - External Modulation Functionality Selector

pub fn tce(&mut self) -> TCE_W<'_>

Bit 20 - Timer Concatenation Enable

impl W<u32, Reg<u32, _TCSET>>

pub fn trbs(&mut self) -> TRBS_W<'_>

Bit 0 - Timer Run Bit set

impl W<u32, Reg<u32, _TCCLR>>

pub fn trbc(&mut self) -> TRBC_W<'_>

Bit 0 - Timer Run Bit Clear

pub fn tcc(&mut self) -> TCC_W<'_>

Bit 1 - Timer Clear

pub fn ditc(&mut self) -> DITC_W<'_>

Bit 2 - Dither Counter Clear

impl W<u32, Reg<u32, _TC>>

pub fn tcm(&mut self) -> TCM_W<'_>

Bit 0 - Timer Counting Mode

pub fn tssm(&mut self) -> TSSM_W<'_>

Bit 1 - Timer Single Shot Mode

pub fn clst(&mut self) -> CLST_W<'_>

Bit 2 - Shadow Transfer on Clear

pub fn ecm(&mut self) -> ECM_W<'_>

Bit 4 - Extended Capture Mode

pub fn capc(&mut self) -> CAPC_W<'_>

Bits 5:6 - Clear on Capture Control

pub fn endm(&mut self) -> ENDM_W<'_>

Bits 8:9 - Extended Stop Function Control

pub fn strm(&mut self) -> STRM_W<'_>

Bit 10 - Extended Start Function Control

pub fn sce(&mut self) -> SCE_W<'_>

Bit 11 - Equal Capture Event enable

pub fn ccs(&mut self) -> CCS_W<'_>

Bit 12 - Continuous Capture Enable

pub fn dithe(&mut self) -> DITHE_W<'_>

Bits 13:14 - Dither Enable

pub fn dim(&mut self) -> DIM_W<'_>

Bit 15 - Dither input selector

pub fn fpe(&mut self) -> FPE_W<'_>

Bit 16 - Floating Prescaler enable

pub fn trape(&mut self) -> TRAPE_W<'_>

Bit 17 - TRAP enable

pub fn trpse(&mut self) -> TRPSE_W<'_>

Bit 21 - TRAP Synchronization Enable

pub fn trpsw(&mut self) -> TRPSW_W<'_>

Bit 22 - TRAP State Clear Control

pub fn ems(&mut self) -> EMS_W<'_>

Bit 23 - External Modulation Synchronization

pub fn emt(&mut self) -> EMT_W<'_>

Bit 24 - External Modulation Type

pub fn mcme(&mut self) -> MCME_W<'_>

Bit 25 - Multi Channel Mode Enable

impl W<u32, Reg<u32, _PSL>>

pub fn psl(&mut self) -> PSL_W<'_>

Bit 0 - Output Passive Level

impl W<u32, Reg<u32, _DITS>>

pub fn dcvs(&mut self) -> DCVS_W<'_>

Bits 0:3 - Dither Shadow Compare Value

impl W<u32, Reg<u32, _PSC>>

pub fn psiv(&mut self) -> PSIV_W<'_>

Bits 0:3 - Prescaler Initial Value

impl W<u32, Reg<u32, _FPC>>

pub fn pval(&mut self) -> PVAL_W<'_>

Bits 8:11 - Actual Prescaler Value

impl W<u32, Reg<u32, _FPCS>>

pub fn pcmp(&mut self) -> PCMP_W<'_>

Bits 0:3 - Floating Prescaler Shadow Compare Value

impl W<u32, Reg<u32, _PRS>>

pub fn prs(&mut self) -> PRS_W<'_>

Bits 0:15 - Period Register

impl W<u32, Reg<u32, _CRS>>

pub fn crs(&mut self) -> CRS_W<'_>

Bits 0:15 - Compare Register

impl W<u32, Reg<u32, _TIMER>>

pub fn tval(&mut self) -> TVAL_W<'_>

Bits 0:15 - Timer Value

impl W<u32, Reg<u32, _INTE>>

pub fn pme(&mut self) -> PME_W<'_>

Bit 0 - Period match while counting up enable

pub fn ome(&mut self) -> OME_W<'_>

Bit 1 - One match while counting down enable

pub fn cmue(&mut self) -> CMUE_W<'_>

Bit 2 - Compare match while counting up enable

pub fn cmde(&mut self) -> CMDE_W<'_>

Bit 3 - Compare match while counting down enable

pub fn e0ae(&mut self) -> E0AE_W<'_>

Bit 8 - Event 0 interrupt enable

pub fn e1ae(&mut self) -> E1AE_W<'_>

Bit 9 - Event 1 interrupt enable

pub fn e2ae(&mut self) -> E2AE_W<'_>

Bit 10 - Event 2 interrupt enable

impl W<u32, Reg<u32, _SRS>>

pub fn posr(&mut self) -> POSR_W<'_>

Bits 0:1 - Period/One match Service request selector

pub fn cmsr(&mut self) -> CMSR_W<'_>

Bits 2:3 - Compare match Service request selector

pub fn e0sr(&mut self) -> E0SR_W<'_>

Bits 8:9 - Event 0 Service request selector

pub fn e1sr(&mut self) -> E1SR_W<'_>

Bits 10:11 - Event 1 Service request selector

pub fn e2sr(&mut self) -> E2SR_W<'_>

Bits 12:13 - Event 2 Service request selector

impl W<u32, Reg<u32, _SWS>>

pub fn spm(&mut self) -> SPM_W<'_>

Bit 0 - Period match while counting up set

pub fn som(&mut self) -> SOM_W<'_>

Bit 1 - One match while counting down set

pub fn scmu(&mut self) -> SCMU_W<'_>

Bit 2 - Compare match while counting up set

pub fn scmd(&mut self) -> SCMD_W<'_>

Bit 3 - Compare match while counting down set

pub fn se0a(&mut self) -> SE0A_W<'_>

Bit 8 - Event 0 detection set

pub fn se1a(&mut self) -> SE1A_W<'_>

Bit 9 - Event 1 detection set

pub fn se2a(&mut self) -> SE2A_W<'_>

Bit 10 - Event 2 detection set

pub fn strpf(&mut self) -> STRPF_W<'_>

Bit 11 - Trap Flag status set

impl W<u32, Reg<u32, _SWR>>

pub fn rpm(&mut self) -> RPM_W<'_>

Bit 0 - Period match while counting up clear

pub fn rom(&mut self) -> ROM_W<'_>

Bit 1 - One match while counting down clear

pub fn rcmu(&mut self) -> RCMU_W<'_>

Bit 2 - Compare match while counting up clear

pub fn rcmd(&mut self) -> RCMD_W<'_>

Bit 3 - Compare match while counting down clear

pub fn re0a(&mut self) -> RE0A_W<'_>

Bit 8 - Event 0 detection clear

pub fn re1a(&mut self) -> RE1A_W<'_>

Bit 9 - Event 1 detection clear

pub fn re2a(&mut self) -> RE2A_W<'_>

Bit 10 - Event 2 detection clear

pub fn rtrpf(&mut self) -> RTRPF_W<'_>

Bit 11 - Trap Flag status clear

impl W<u32, Reg<u32, _GCTRL>>

pub fn prbc(&mut self) -> PRBC_W<'_>

Bits 0:2 - Prescaler Clear Configuration

pub fn pcis(&mut self) -> PCIS_W<'_>

Bits 4:5 - Prescaler Input Clock Selection

pub fn suscfg(&mut self) -> SUSCFG_W<'_>

Bits 8:9 - Suspend Mode Configuration

pub fn mse0(&mut self) -> MSE0_W<'_>

Bit 10 - Slice 0 Multi Channel shadow transfer enable

pub fn mse1(&mut self) -> MSE1_W<'_>

Bit 11 - Slice 1 Multi Channel shadow transfer enable

pub fn mse2(&mut self) -> MSE2_W<'_>

Bit 12 - Slice 2 Multi Channel shadow transfer enable

pub fn mse3(&mut self) -> MSE3_W<'_>

Bit 13 - Slice 3 Multi Channel shadow transfer enable

pub fn msde(&mut self) -> MSDE_W<'_>

Bits 14:15 - Multi Channel shadow transfer request configuration

impl W<u32, Reg<u32, _GIDLS>>

pub fn ss0i(&mut self) -> SS0I_W<'_>

Bit 0 - CC80 IDLE mode set

pub fn ss1i(&mut self) -> SS1I_W<'_>

Bit 1 - CC81 IDLE mode set

pub fn ss2i(&mut self) -> SS2I_W<'_>

Bit 2 - CC82 IDLE mode set

pub fn ss3i(&mut self) -> SS3I_W<'_>

Bit 3 - CC83 IDLE mode set

pub fn cprb(&mut self) -> CPRB_W<'_>

Bit 8 - Prescaler# Run Bit Clear

pub fn psic(&mut self) -> PSIC_W<'_>

Bit 9 - Prescaler clear

pub fn cpch(&mut self) -> CPCH_W<'_>

Bit 10 - Parity Checker Run bit clear

impl W<u32, Reg<u32, _GIDLC>>

pub fn cs0i(&mut self) -> CS0I_W<'_>

Bit 0 - CC80 IDLE mode clear

pub fn cs1i(&mut self) -> CS1I_W<'_>

Bit 1 - CC81 IDLE mode clear

pub fn cs2i(&mut self) -> CS2I_W<'_>

Bit 2 - CC82 IDLE mode clear

pub fn cs3i(&mut self) -> CS3I_W<'_>

Bit 3 - CC83 IDLE mode clear

pub fn sprb(&mut self) -> SPRB_W<'_>

Bit 8 - Prescaler Run Bit Set

pub fn spch(&mut self) -> SPCH_W<'_>

Bit 10 - Parity Checker run bit set

impl W<u32, Reg<u32, _GCSS>>

pub fn s0se(&mut self) -> S0SE_W<'_>

Bit 0 - Slice 0 shadow transfer set enable

pub fn s0dse(&mut self) -> S0DSE_W<'_>

Bit 1 - Slice 0 Dither shadow transfer set enable

pub fn s0pse(&mut self) -> S0PSE_W<'_>

Bit 2 - Slice 0 Prescaler shadow transfer set enable

pub fn s1se(&mut self) -> S1SE_W<'_>

Bit 4 - Slice 1 shadow transfer set enable

pub fn s1dse(&mut self) -> S1DSE_W<'_>

Bit 5 - Slice 1 Dither shadow transfer set enable

pub fn s1pse(&mut self) -> S1PSE_W<'_>

Bit 6 - Slice 1 Prescaler shadow transfer set enable

pub fn s2se(&mut self) -> S2SE_W<'_>

Bit 8 - Slice 2 shadow transfer set enable

pub fn s2dse(&mut self) -> S2DSE_W<'_>

Bit 9 - Slice 2 Dither shadow transfer set enable

pub fn s2pse(&mut self) -> S2PSE_W<'_>

Bit 10 - Slice 2 Prescaler shadow transfer set enable

pub fn s3se(&mut self) -> S3SE_W<'_>

Bit 12 - Slice 3 shadow transfer set enable

pub fn s3dse(&mut self) -> S3DSE_W<'_>

Bit 13 - Slice 3 Dither shadow transfer set enable

pub fn s3pse(&mut self) -> S3PSE_W<'_>

Bit 14 - Slice 3 Prescaler shadow transfer set enable

pub fn s0st1s(&mut self) -> S0ST1S_W<'_>

Bit 16 - Slice 0 status bit 1 set

pub fn s1st1s(&mut self) -> S1ST1S_W<'_>

Bit 17 - Slice 1 status bit 1 set

pub fn s2st1s(&mut self) -> S2ST1S_W<'_>

Bit 18 - Slice 2 status bit 1 set

pub fn s3st1s(&mut self) -> S3ST1S_W<'_>

Bit 19 - Slice 3 status bit 1 set

pub fn s0st2s(&mut self) -> S0ST2S_W<'_>

Bit 20 - Slice 0 status bit 2 set

pub fn s1st2s(&mut self) -> S1ST2S_W<'_>

Bit 21 - Slice 1 status bit 2 set

pub fn s2st2s(&mut self) -> S2ST2S_W<'_>

Bit 22 - Slice 2 status bit 2 set

pub fn s3st2s(&mut self) -> S3ST2S_W<'_>

Bit 23 - Slice 3 status bit 2 set

impl W<u32, Reg<u32, _GCSC>>

pub fn s0sc(&mut self) -> S0SC_W<'_>

Bit 0 - Slice 0 shadow transfer request clear

pub fn s0dsc(&mut self) -> S0DSC_W<'_>

Bit 1 - Slice 0 Dither shadow transfer clear

pub fn s0psc(&mut self) -> S0PSC_W<'_>

Bit 2 - Slice 0 Prescaler shadow transfer clear

pub fn s1sc(&mut self) -> S1SC_W<'_>

Bit 4 - Slice 1 shadow transfer clear

pub fn s1dsc(&mut self) -> S1DSC_W<'_>

Bit 5 - Slice 1 Dither shadow transfer clear

pub fn s1psc(&mut self) -> S1PSC_W<'_>

Bit 6 - Slice 1 Prescaler shadow transfer clear

pub fn s2sc(&mut self) -> S2SC_W<'_>

Bit 8 - Slice 2 shadow transfer clear

pub fn s2dsc(&mut self) -> S2DSC_W<'_>

Bit 9 - Slice 2 Dither shadow transfer clear

pub fn s2psc(&mut self) -> S2PSC_W<'_>

Bit 10 - Slice 2 Prescaler shadow transfer clear

pub fn s3sc(&mut self) -> S3SC_W<'_>

Bit 12 - Slice 3 shadow transfer clear

pub fn s3dsc(&mut self) -> S3DSC_W<'_>

Bit 13 - Slice 3 Dither shadow transfer clear

pub fn s3psc(&mut self) -> S3PSC_W<'_>

Bit 14 - Slice 3 Prescaler shadow transfer clear

pub fn s0st1c(&mut self) -> S0ST1C_W<'_>

Bit 16 - Slice 0 status bit 1 clear

pub fn s1st1c(&mut self) -> S1ST1C_W<'_>

Bit 17 - Slice 1 status bit 1 clear

pub fn s2st1c(&mut self) -> S2ST1C_W<'_>

Bit 18 - Slice 2 status bit 1 clear

pub fn s3st1c(&mut self) -> S3ST1C_W<'_>

Bit 19 - Slice 3 status bit 1 clear

pub fn s0st2c(&mut self) -> S0ST2C_W<'_>

Bit 20 - Slice 0 status bit 2 clear

pub fn s1st2c(&mut self) -> S1ST2C_W<'_>

Bit 21 - Slice 1 status bit 2 clear

pub fn s2st2c(&mut self) -> S2ST2C_W<'_>

Bit 22 - Slice 2 status bit 2 clear

pub fn s3st2c(&mut self) -> S3ST2C_W<'_>

Bit 23 - Slice 3 status bit 2 clear

impl W<u32, Reg<u32, _GPCHK>>

pub fn pase(&mut self) -> PASE_W<'_>

Bit 0 - Parity Checker Automatic start/stop

pub fn pacs(&mut self) -> PACS_W<'_>

Bits 1:2 - Parity Checker Automatic start/stop selector

pub fn pisel(&mut self) -> PISEL_W<'_>

Bits 3:4 - Driver Input signal selector

pub fn pcds(&mut self) -> PCDS_W<'_>

Bits 5:6 - Parity Checker Delay Input Selector

pub fn pcts(&mut self) -> PCTS_W<'_>

Bit 7 - Parity Checker type selector

pub fn pcsel0(&mut self) -> PCSEL0_W<'_>

Bits 16:19 - Parity Checker Slice 0 output selection

pub fn pcsel1(&mut self) -> PCSEL1_W<'_>

Bits 20:23 - Parity Checker Slice 1 output selection

pub fn pcsel2(&mut self) -> PCSEL2_W<'_>

Bits 24:27 - Parity Checker Slice 2 output selection

pub fn pcsel3(&mut self) -> PCSEL3_W<'_>

Bits 28:31 - Parity Checker Slice 3 output selection

impl W<u32, Reg<u32, _INS>>

pub fn ev0is(&mut self) -> EV0IS_W<'_>

Bits 0:3 - Event 0 signal selection

pub fn ev1is(&mut self) -> EV1IS_W<'_>

Bits 4:7 - Event 1 signal selection

pub fn ev2is(&mut self) -> EV2IS_W<'_>

Bits 8:11 - Event 2 signal selection

pub fn ev0em(&mut self) -> EV0EM_W<'_>

Bits 16:17 - Event 0 Edge Selection

pub fn ev1em(&mut self) -> EV1EM_W<'_>

Bits 18:19 - Event 1 Edge Selection

pub fn ev2em(&mut self) -> EV2EM_W<'_>

Bits 20:21 - Event 2 Edge Selection

pub fn ev0lm(&mut self) -> EV0LM_W<'_>

Bit 22 - Event 0 Level Selection

pub fn ev1lm(&mut self) -> EV1LM_W<'_>

Bit 23 - Event 1 Level Selection

pub fn ev2lm(&mut self) -> EV2LM_W<'_>

Bit 24 - Event 2 Level Selection

pub fn lpf0m(&mut self) -> LPF0M_W<'_>

Bits 25:26 - Event 0 Low Pass Filter Configuration

pub fn lpf1m(&mut self) -> LPF1M_W<'_>

Bits 27:28 - Event 1 Low Pass Filter Configuration

pub fn lpf2m(&mut self) -> LPF2M_W<'_>

Bits 29:30 - Event 2 Low Pass Filter Configuration

impl W<u32, Reg<u32, _CMC>>

pub fn strts(&mut self) -> STRTS_W<'_>

Bits 0:1 - External Start Functionality Selector

pub fn ends(&mut self) -> ENDS_W<'_>

Bits 2:3 - External Stop Functionality Selector

pub fn cap0s(&mut self) -> CAP0S_W<'_>

Bits 4:5 - External Capture 0 Functionality Selector

pub fn cap1s(&mut self) -> CAP1S_W<'_>

Bits 6:7 - External Capture 1 Functionality Selector

pub fn gates(&mut self) -> GATES_W<'_>

Bits 8:9 - External Gate Functionality Selector

pub fn uds(&mut self) -> UDS_W<'_>

Bits 10:11 - External Up/Down Functionality Selector

pub fn lds(&mut self) -> LDS_W<'_>

Bits 12:13 - External Timer Load Functionality Selector

pub fn cnts(&mut self) -> CNTS_W<'_>

Bits 14:15 - External Count Selector

pub fn ofs(&mut self) -> OFS_W<'_>

Bit 16 - Override Function Selector

pub fn ts(&mut self) -> TS_W<'_>

Bit 17 - Trap Function Selector

pub fn mos(&mut self) -> MOS_W<'_>

Bits 18:19 - External Modulation Functionality Selector

pub fn tce(&mut self) -> TCE_W<'_>

Bit 20 - Timer Concatenation Enable

impl W<u32, Reg<u32, _TCSET>>

pub fn trbs(&mut self) -> TRBS_W<'_>

Bit 0 - Timer Run Bit set

impl W<u32, Reg<u32, _TCCLR>>

pub fn trbc(&mut self) -> TRBC_W<'_>

Bit 0 - Timer Run Bit Clear

pub fn tcc(&mut self) -> TCC_W<'_>

Bit 1 - Timer Clear

pub fn ditc(&mut self) -> DITC_W<'_>

Bit 2 - Dither Counter Clear

pub fn dtc1c(&mut self) -> DTC1C_W<'_>

Bit 3 - Dead Time Counter 1 Clear

pub fn dtc2c(&mut self) -> DTC2C_W<'_>

Bit 4 - Dead Time Counter 2 Clear

impl W<u32, Reg<u32, _TC>>

pub fn tcm(&mut self) -> TCM_W<'_>

Bit 0 - Timer Counting Mode

pub fn tssm(&mut self) -> TSSM_W<'_>

Bit 1 - Timer Single Shot Mode

pub fn clst(&mut self) -> CLST_W<'_>

Bit 2 - Shadow Transfer on Clear

pub fn ecm(&mut self) -> ECM_W<'_>

Bit 4 - Extended Capture Mode

pub fn capc(&mut self) -> CAPC_W<'_>

Bits 5:6 - Clear on Capture Control

pub fn tls(&mut self) -> TLS_W<'_>

Bit 7 - Timer Load selector

pub fn endm(&mut self) -> ENDM_W<'_>

Bits 8:9 - Extended Stop Function Control

pub fn strm(&mut self) -> STRM_W<'_>

Bit 10 - Extended Start Function Control

pub fn sce(&mut self) -> SCE_W<'_>

Bit 11 - Equal Capture Event enable

pub fn ccs(&mut self) -> CCS_W<'_>

Bit 12 - Continuous Capture Enable

pub fn dithe(&mut self) -> DITHE_W<'_>

Bits 13:14 - Dither Enable

pub fn dim(&mut self) -> DIM_W<'_>

Bit 15 - Dither input selector

pub fn fpe(&mut self) -> FPE_W<'_>

Bit 16 - Floating Prescaler enable

pub fn trape0(&mut self) -> TRAPE0_W<'_>

Bit 17 - TRAP enable for CCU8x.OUTy0

pub fn trape1(&mut self) -> TRAPE1_W<'_>

Bit 18 - TRAP enable for CCU8x.OUTy1

pub fn trape2(&mut self) -> TRAPE2_W<'_>

Bit 19 - TRAP enable for CCU8x.OUTy2

pub fn trape3(&mut self) -> TRAPE3_W<'_>

Bit 20 - TRAP enable for CCU8x.OUTy3

pub fn trpse(&mut self) -> TRPSE_W<'_>

Bit 21 - TRAP Synchronization Enable

pub fn trpsw(&mut self) -> TRPSW_W<'_>

Bit 22 - TRAP State Clear Control

pub fn ems(&mut self) -> EMS_W<'_>

Bit 23 - External Modulation Synchronization

pub fn emt(&mut self) -> EMT_W<'_>

Bit 24 - External Modulation Type

pub fn mcme1(&mut self) -> MCME1_W<'_>

Bit 25 - Multi Channel Mode Enable for Channel 1

pub fn mcme2(&mut self) -> MCME2_W<'_>

Bit 26 - Multi Channel Mode Enable for Channel 2

pub fn eme(&mut self) -> EME_W<'_>

Bits 27:28 - External Modulation Channel enable

pub fn stos(&mut self) -> STOS_W<'_>

Bits 29:30 - Status bit output selector

impl W<u32, Reg<u32, _PSL>>

pub fn psl11(&mut self) -> PSL11_W<'_>

Bit 0 - Output Passive Level for CCU8x.OUTy0

pub fn psl12(&mut self) -> PSL12_W<'_>

Bit 1 - Output Passive Level for CCU8x.OUTy1

pub fn psl21(&mut self) -> PSL21_W<'_>

Bit 2 - Output Passive Level for CCU8x.OUTy2

pub fn psl22(&mut self) -> PSL22_W<'_>

Bit 3 - Output Passive Level for CCU8x.OUTy3

impl W<u32, Reg<u32, _DITS>>

pub fn dcvs(&mut self) -> DCVS_W<'_>

Bits 0:3 - Dither Shadow Compare Value

impl W<u32, Reg<u32, _PSC>>

pub fn psiv(&mut self) -> PSIV_W<'_>

Bits 0:3 - Prescaler Initial Value

impl W<u32, Reg<u32, _FPC>>

pub fn pval(&mut self) -> PVAL_W<'_>

Bits 8:11 - Actual Prescaler Value

impl W<u32, Reg<u32, _FPCS>>

pub fn pcmp(&mut self) -> PCMP_W<'_>

Bits 0:3 - Floating Prescaler Shadow Compare Value

impl W<u32, Reg<u32, _PRS>>

pub fn prs(&mut self) -> PRS_W<'_>

Bits 0:15 - Period Register

impl W<u32, Reg<u32, _CR1S>>

pub fn cr1s(&mut self) -> CR1S_W<'_>

Bits 0:15 - Shadow Compare Register for Channel 1

impl W<u32, Reg<u32, _CR2S>>

pub fn cr2s(&mut self) -> CR2S_W<'_>

Bits 0:15 - Shadow Compare Register for Channel 2

impl W<u32, Reg<u32, _CHC>>

pub fn ase(&mut self) -> ASE_W<'_>

Bit 0 - Asymmetric PWM mode Enable

pub fn ocs1(&mut self) -> OCS1_W<'_>

Bit 1 - Output selector for CCU8x.OUTy0

pub fn ocs2(&mut self) -> OCS2_W<'_>

Bit 2 - Output selector for CCU8x.OUTy1

pub fn ocs3(&mut self) -> OCS3_W<'_>

Bit 3 - Output selector for CCU8x.OUTy2

pub fn ocs4(&mut self) -> OCS4_W<'_>

Bit 4 - Output selector for CCU8x.OUTy3

impl W<u32, Reg<u32, _DTC>>

pub fn dte1(&mut self) -> DTE1_W<'_>

Bit 0 - Dead Time Enable for Channel 1

pub fn dte2(&mut self) -> DTE2_W<'_>

Bit 1 - Dead Time Enable for Channel 2

pub fn dcen1(&mut self) -> DCEN1_W<'_>

Bit 2 - Dead Time Enable for CC8yST1

pub fn dcen2(&mut self) -> DCEN2_W<'_>

Bit 3 - Dead Time Enable for inverted CC8yST1

pub fn dcen3(&mut self) -> DCEN3_W<'_>

Bit 4 - Dead Time Enable for CC8yST2

pub fn dcen4(&mut self) -> DCEN4_W<'_>

Bit 5 - Dead Time Enable for inverted CC8yST2

pub fn dtcc(&mut self) -> DTCC_W<'_>

Bits 6:7 - Dead Time clock control

impl W<u32, Reg<u32, _DC1R>>

pub fn dt1r(&mut self) -> DT1R_W<'_>

Bits 0:7 - Rise Value for Dead Time of Channel 1

pub fn dt1f(&mut self) -> DT1F_W<'_>

Bits 8:15 - Fall Value for Dead Time of Channel 1

impl W<u32, Reg<u32, _DC2R>>

pub fn dt2r(&mut self) -> DT2R_W<'_>

Bits 0:7 - Rise Value for Dead Time of Channel 2

pub fn dt2f(&mut self) -> DT2F_W<'_>

Bits 8:15 - Fall Value for Dead Time of Channel 2

impl W<u32, Reg<u32, _TIMER>>

pub fn tval(&mut self) -> TVAL_W<'_>

Bits 0:15 - Timer Value

impl W<u32, Reg<u32, _INTE>>

pub fn pme(&mut self) -> PME_W<'_>

Bit 0 - Period match while counting up enable

pub fn ome(&mut self) -> OME_W<'_>

Bit 1 - One match while counting down enable

pub fn cmu1e(&mut self) -> CMU1E_W<'_>

Bit 2 - Channel 1 Compare match while counting up enable

pub fn cmd1e(&mut self) -> CMD1E_W<'_>

Bit 3 - Channel 1 Compare match while counting down enable

pub fn cmu2e(&mut self) -> CMU2E_W<'_>

Bit 4 - Channel 2 Compare match while counting up enable

pub fn cmd2e(&mut self) -> CMD2E_W<'_>

Bit 5 - Channel 2 Compare match while counting down enable

pub fn e0ae(&mut self) -> E0AE_W<'_>

Bit 8 - Event 0 interrupt enable

pub fn e1ae(&mut self) -> E1AE_W<'_>

Bit 9 - Event 1 interrupt enable

pub fn e2ae(&mut self) -> E2AE_W<'_>

Bit 10 - Event 2 interrupt enable

impl W<u32, Reg<u32, _SRS>>

pub fn posr(&mut self) -> POSR_W<'_>

Bits 0:1 - Period/One match Service request selector

pub fn cm1sr(&mut self) -> CM1SR_W<'_>

Bits 2:3 - Channel 1 Compare match Service request selector

pub fn cm2sr(&mut self) -> CM2SR_W<'_>

Bits 4:5 - Channel 2 Compare match Service request selector

pub fn e0sr(&mut self) -> E0SR_W<'_>

Bits 8:9 - Event 0 Service request selector

pub fn e1sr(&mut self) -> E1SR_W<'_>

Bits 10:11 - Event 1 Service request selector

pub fn e2sr(&mut self) -> E2SR_W<'_>

Bits 12:13 - Event 2 Service request selector

impl W<u32, Reg<u32, _SWS>>

pub fn spm(&mut self) -> SPM_W<'_>

Bit 0 - Period match while counting up set

pub fn som(&mut self) -> SOM_W<'_>

Bit 1 - One match while counting down set

pub fn scm1u(&mut self) -> SCM1U_W<'_>

Bit 2 - Channel 1 Compare match while counting up set

pub fn scm1d(&mut self) -> SCM1D_W<'_>

Bit 3 - Channel 1 Compare match while counting down set

pub fn scm2u(&mut self) -> SCM2U_W<'_>

Bit 4 - Compare match while counting up set

pub fn scm2d(&mut self) -> SCM2D_W<'_>

Bit 5 - Compare match while counting down set

pub fn se0a(&mut self) -> SE0A_W<'_>

Bit 8 - Event 0 detection set

pub fn se1a(&mut self) -> SE1A_W<'_>

Bit 9 - Event 1 detection set

pub fn se2a(&mut self) -> SE2A_W<'_>

Bit 10 - Event 2 detection set

pub fn strpf(&mut self) -> STRPF_W<'_>

Bit 11 - Trap Flag status set

impl W<u32, Reg<u32, _SWR>>

pub fn rpm(&mut self) -> RPM_W<'_>

Bit 0 - Period match while counting up clear

pub fn rom(&mut self) -> ROM_W<'_>

Bit 1 - One match while counting down clear

pub fn rcm1u(&mut self) -> RCM1U_W<'_>

Bit 2 - Channel 1 Compare match while counting up clear

pub fn rcm1d(&mut self) -> RCM1D_W<'_>

Bit 3 - Channel 1 Compare match while counting down clear

pub fn rcm2u(&mut self) -> RCM2U_W<'_>

Bit 4 - Channel 2 Compare match while counting up clear

pub fn rcm2d(&mut self) -> RCM2D_W<'_>

Bit 5 - Channel 2 Compare match while counting down clear

pub fn re0a(&mut self) -> RE0A_W<'_>

Bit 8 - Event 0 detection clear

pub fn re1a(&mut self) -> RE1A_W<'_>

Bit 9 - Event 1 detection clear

pub fn re2a(&mut self) -> RE2A_W<'_>

Bit 10 - Event 2 detection clear

pub fn rtrpf(&mut self) -> RTRPF_W<'_>

Bit 11 - Trap Flag status clear

impl W<u32, Reg<u32, _STC>>

pub fn cse(&mut self) -> CSE_W<'_>

Bit 0 - Cascaded shadow transfer enable

pub fn stm(&mut self) -> STM_W<'_>

Bits 1:2 - Shadow transfer mode

impl W<u32, Reg<u32, _HRBSC>>

pub fn suscfg(&mut self) -> SUSCFG_W<'_>

Bits 0:2 - Suspend configuration

pub fn hrbe(&mut self) -> HRBE_W<'_>

Bit 8 - HRPWM bias enable

impl W<u32, Reg<u32, _GLBANA>>

pub fn sldly(&mut self) -> SLDLY_W<'_>

Bits 0:1 - Delay of lock detection

pub fn fup(&mut self) -> FUP_W<'_>

Bit 2 - Force chargepump up

pub fn fdn(&mut self) -> FDN_W<'_>

Bit 3 - Force chargepump down

pub fn slcp(&mut self) -> SLCP_W<'_>

Bits 6:8 - HRCs chargepump current selection

pub fn slibldo(&mut self) -> SLIBLDO_W<'_>

Bits 9:10 - HRCs LDO bias current

pub fn sliblf(&mut self) -> SLIBLF_W<'_>

Bits 11:12 - HRCs loop filter bias current

pub fn slvref(&mut self) -> SLVREF_W<'_>

Bits 13:15 - Reference voltage for chargepump and loop filter

pub fn tribias(&mut self) -> TRIBIAS_W<'_>

Bits 16:17 - Bias trimming

pub fn ghren(&mut self) -> GHREN_W<'_>

Bit 18 - Force chargepump down

impl W<u32, Reg<u32, _CSGCFG>>

pub fn c0pm(&mut self) -> C0PM_W<'_>

Bits 0:1 - CSG0 Power Mode

pub fn c1pm(&mut self) -> C1PM_W<'_>

Bits 2:3 - CSG1 Power Mode

pub fn c2pm(&mut self) -> C2PM_W<'_>

Bits 4:5 - CSG2 Power Mode

pub fn c0cd(&mut self) -> C0CD_W<'_>

Bit 16 - CSG0 Clock disable

pub fn c1cd(&mut self) -> C1CD_W<'_>

Bit 17 - CSG1 Clock disable

pub fn c2cd(&mut self) -> C2CD_W<'_>

Bit 18 - CSG2 Clock disable

impl W<u32, Reg<u32, _CSGSETG>>

pub fn sd0r(&mut self) -> SD0R_W<'_>

Bit 0 - DAC0 run bit set

pub fn sc0r(&mut self) -> SC0R_W<'_>

Bit 1 - CMP0 run bit set

pub fn sc0p(&mut self) -> SC0P_W<'_>

Bit 2 - CMP0 passive level set

pub fn sd1r(&mut self) -> SD1R_W<'_>

Bit 4 - DAC1 run bit set

pub fn sc1r(&mut self) -> SC1R_W<'_>

Bit 5 - CMP1 run bit set

pub fn sc1p(&mut self) -> SC1P_W<'_>

Bit 6 - CMP1 passive level set

pub fn sd2r(&mut self) -> SD2R_W<'_>

Bit 8 - DAC2 run bit set

pub fn sc2r(&mut self) -> SC2R_W<'_>

Bit 9 - CMP2 run bit set

pub fn sc2p(&mut self) -> SC2P_W<'_>

Bit 10 - CMP2 passive level set

impl W<u32, Reg<u32, _CSGCLRG>>

pub fn cd0r(&mut self) -> CD0R_W<'_>

Bit 0 - DAC0 run bit clear

pub fn cc0r(&mut self) -> CC0R_W<'_>

Bit 1 - CMP0 run bit clear

pub fn cc0p(&mut self) -> CC0P_W<'_>

Bit 2 - CMP0 passive level clear

pub fn cd1r(&mut self) -> CD1R_W<'_>

Bit 4 - DAC1 run bit clear

pub fn cc1r(&mut self) -> CC1R_W<'_>

Bit 5 - CMP1 run bit clear

pub fn cc1p(&mut self) -> CC1P_W<'_>

Bit 6 - CMP1 passive level clear

pub fn cd2r(&mut self) -> CD2R_W<'_>

Bit 8 - DAC2 run bit clear

pub fn cc2r(&mut self) -> CC2R_W<'_>

Bit 9 - CMP2 run bit clear

pub fn cc2p(&mut self) -> CC2P_W<'_>

Bit 10 - CMP2 passive level clear

impl W<u32, Reg<u32, _CSGFCG>>

pub fn s0str(&mut self) -> S0STR_W<'_>

Bit 0 - Slope 0 start

pub fn s0stp(&mut self) -> S0STP_W<'_>

Bit 1 - Slope 0 stop

pub fn ps0str(&mut self) -> PS0STR_W<'_>

Bit 2 - Prescaler 0 start

pub fn ps0stp(&mut self) -> PS0STP_W<'_>

Bit 3 - Prescaler 0 stop

pub fn ps0clr(&mut self) -> PS0CLR_W<'_>

Bit 4 - Prescaler 0 clear

pub fn s1str(&mut self) -> S1STR_W<'_>

Bit 8 - Slope 1 start

pub fn s1stp(&mut self) -> S1STP_W<'_>

Bit 9 - Slope 1 stop

pub fn ps1str(&mut self) -> PS1STR_W<'_>

Bit 10 - Prescaler 1 start

pub fn ps1stp(&mut self) -> PS1STP_W<'_>

Bit 11 - Prescaler 1 stop

pub fn ps1clr(&mut self) -> PS1CLR_W<'_>

Bit 12 - Prescaler 1 clear

pub fn s2str(&mut self) -> S2STR_W<'_>

Bit 16 - Slope 2 start

pub fn s2stp(&mut self) -> S2STP_W<'_>

Bit 17 - Slope 2 stop

pub fn ps2str(&mut self) -> PS2STR_W<'_>

Bit 18 - Prescaler 2 start

pub fn ps2stp(&mut self) -> PS2STP_W<'_>

Bit 19 - Prescaler 2 stop

pub fn ps2clr(&mut self) -> PS2CLR_W<'_>

Bit 20 - Prescaler 2 clear

impl W<u32, Reg<u32, _CSGTRG>>

pub fn d0ses(&mut self) -> D0SES_W<'_>

Bit 0 - DAC0 shadow transfer enable set

pub fn d0svs(&mut self) -> D0SVS_W<'_>

Bit 1 - CMP0 inverting input switch request

pub fn d1ses(&mut self) -> D1SES_W<'_>

Bit 4 - DAC1 shadow transfer enable set

pub fn d1svs(&mut self) -> D1SVS_W<'_>

Bit 5 - CMP1 inverting input switch request

pub fn d2ses(&mut self) -> D2SES_W<'_>

Bit 8 - DAC2 shadow transfer enable set

pub fn d2svs(&mut self) -> D2SVS_W<'_>

Bit 9 - CMP2 inverting input switch request

impl W<u32, Reg<u32, _CSGTRC>>

pub fn d0sec(&mut self) -> D0SEC_W<'_>

Bit 0 - DAC0 shadow transfer enable clear

pub fn d1sec(&mut self) -> D1SEC_W<'_>

Bit 4 - DAC1 shadow transfer enable clear

pub fn d2sec(&mut self) -> D2SEC_W<'_>

Bit 8 - DAC2 shadow transfer enable clear

impl W<u32, Reg<u32, _HRCCFG>>

pub fn hrcpm(&mut self) -> HRCPM_W<'_>

Bit 0 - High resolution channels power mode

pub fn hrc0e(&mut self) -> HRC0E_W<'_>

Bit 4 - HRC0 high resolution enable

pub fn hrc1e(&mut self) -> HRC1E_W<'_>

Bit 5 - HRC1 high resolution channel enable

pub fn hrc2e(&mut self) -> HRC2E_W<'_>

Bit 6 - HRC2 high resolution channel enable

pub fn hrc3e(&mut self) -> HRC3E_W<'_>

Bit 7 - HRC3 high resolution channel enable

pub fn clkc(&mut self) -> CLKC_W<'_>

Bits 16:18 - Clock information control

pub fn lrc0e(&mut self) -> LRC0E_W<'_>

Bit 20 - HRC0 low resolution channel enable

pub fn lrc1e(&mut self) -> LRC1E_W<'_>

Bit 21 - HRC1 low resolution channel enable

pub fn lrc2e(&mut self) -> LRC2E_W<'_>

Bit 22 - HRC2 low resolution channel enable

pub fn lrc3e(&mut self) -> LRC3E_W<'_>

Bit 23 - HRC3 low resolution channel enable

impl W<u32, Reg<u32, _HRCSTRG>>

pub fn h0es(&mut self) -> H0ES_W<'_>

Bit 0 - HRC0 high resolution values shadow transfer Enable Set

pub fn h0des(&mut self) -> H0DES_W<'_>

Bit 1 - HRC0 dead time value shadow transfer enable set

pub fn h1es(&mut self) -> H1ES_W<'_>

Bit 4 - HRC1 high resolution values shadow transfer Enable Set

pub fn h1des(&mut self) -> H1DES_W<'_>

Bit 5 - HRC0 dead time value shadow transfer enable set

pub fn h2es(&mut self) -> H2ES_W<'_>

Bit 8 - HRC2 high resolution values shadow transfer Enable Set

pub fn h2des(&mut self) -> H2DES_W<'_>

Bit 9 - HRC0 dead time value shadow transfer enable set

pub fn h3es(&mut self) -> H3ES_W<'_>

Bit 12 - HRC3 high resolution values shadow transfer Enable Set

pub fn h3des(&mut self) -> H3DES_W<'_>

Bit 13 - HRC0 dead time value shadow transfer enable set

impl W<u32, Reg<u32, _HRCCTRG>>

pub fn h0ec(&mut self) -> H0EC_W<'_>

Bit 0 - HRC0 high resolution values shadow transfer Enable Clear

pub fn h0dec(&mut self) -> H0DEC_W<'_>

Bit 1 - HRC0 dead time value shadow transfer Enable Clear

pub fn h1ec(&mut self) -> H1EC_W<'_>

Bit 4 - HRC1 high resolution values shadow transfer Enable Clear

pub fn h1dec(&mut self) -> H1DEC_W<'_>

Bit 5 - HRC1 dead time value shadow transfer Enable Clear

pub fn h2cec(&mut self) -> H2CEC_W<'_>

Bit 8 - HRC2 high resolution values shadow transfer Enable Clear

pub fn h2dec(&mut self) -> H2DEC_W<'_>

Bit 9 - HRC2 dead time value shadow transfer Enable Clear

pub fn h3ec(&mut self) -> H3EC_W<'_>

Bit 12 - HRC3 high resolution values shadow transfer Enable Clear

pub fn h3dec(&mut self) -> H3DEC_W<'_>

Bit 13 - HRC3 dead time value shadow transfer Enable Clear

impl W<u32, Reg<u32, _DCI>>

pub fn svis(&mut self) -> SVIS_W<'_>

Bits 0:3 - Value Selector input selection

pub fn stris(&mut self) -> STRIS_W<'_>

Bits 4:7 - Slope generation start control input selection

pub fn stpis(&mut self) -> STPIS_W<'_>

Bits 8:11 - Slope generation stop control input selection

pub fn trgis(&mut self) -> TRGIS_W<'_>

Bits 12:15 - External conversion trigger input selection

pub fn stis(&mut self) -> STIS_W<'_>

Bits 16:19 - External shadow request enable input selection

pub fn scs(&mut self) -> SCS_W<'_>

Bits 20:21 - Slope generation clock selection

impl W<u32, Reg<u32, _IES>>

pub fn svls(&mut self) -> SVLS_W<'_>

Bits 0:1 - External value switch function level selection

pub fn stres(&mut self) -> STRES_W<'_>

Bits 2:3 - External start function edge selection

pub fn stpes(&mut self) -> STPES_W<'_>

Bits 4:5 - External stop function edge selection

pub fn trges(&mut self) -> TRGES_W<'_>

Bits 6:7 - External trigger function edge selection

pub fn stes(&mut self) -> STES_W<'_>

Bits 8:9 - External shadow transfer enable edge selection

impl W<u32, Reg<u32, _SC>>

pub fn psrm(&mut self) -> PSRM_W<'_>

Bits 0:1 - Prescaler external start configuration

pub fn pstm(&mut self) -> PSTM_W<'_>

Bits 2:3 - Prescaler external stop configuration

pub fn fpd(&mut self) -> FPD_W<'_>

Bit 4 - Fixed division disable

pub fn psv(&mut self) -> PSV_W<'_>

Bits 5:6 - Prescaler division factor

pub fn scm(&mut self) -> SCM_W<'_>

Bits 8:9 - Slope control mode

pub fn ssrm(&mut self) -> SSRM_W<'_>

Bits 10:11 - Slope external start configuration

pub fn sstm(&mut self) -> SSTM_W<'_>

Bits 12:13 - Slope external stop configuration

pub fn svsc(&mut self) -> SVSC_W<'_>

Bits 14:15 - Slope reference value mode

pub fn swsm(&mut self) -> SWSM_W<'_>

Bits 16:17 - Initial DAC start mode

pub fn gcfg(&mut self) -> GCFG_W<'_>

Bits 18:19 - Slope step gain configuration

pub fn ist(&mut self) -> IST_W<'_>

Bit 20 - Immediate shadow transfer

pub fn pse(&mut self) -> PSE_W<'_>

Bit 21 - Pulse swallow enable

pub fn pswm(&mut self) -> PSWM_W<'_>

Bits 24:25 - Pulse swallow window mode

impl W<u32, Reg<u32, _DSV2>>

pub fn dsv2(&mut self) -> DSV2_W<'_>

Bits 0:9 - DAC reference value 2

impl W<u32, Reg<u32, _SDSV1>>

pub fn sdsv1(&mut self) -> SDSV1_W<'_>

Bits 0:9 - Shadow DAC reference value 1

impl W<u32, Reg<u32, _SPC>>

pub fn spswv(&mut self) -> SPSWV_W<'_>

Bits 0:5 - Shadow pulse swallow value

impl W<u32, Reg<u32, _CC>>

pub fn ibs(&mut self) -> IBS_W<'_>

Bits 0:3 - External blanking trigger selector

pub fn imcs(&mut self) -> IMCS_W<'_>

Bit 8 - Inverting comparator input selector

pub fn imcc(&mut self) -> IMCC_W<'_>

Bits 9:10 - Comparator input switching configuration

pub fn ese(&mut self) -> ESE_W<'_>

Bit 11 - External triggered switch enable

pub fn oie(&mut self) -> OIE_W<'_>

Bit 12 - Comparator output inversion enable

pub fn ose(&mut self) -> OSE_W<'_>

Bit 13 - Comparator output synchronization enable

pub fn blmc(&mut self) -> BLMC_W<'_>

Bits 14:15 - Blanking mode

pub fn ebe(&mut self) -> EBE_W<'_>

Bit 16 - External blanking trigger enabled

pub fn cofe(&mut self) -> COFE_W<'_>

Bit 17 - Comparator output filter enable

pub fn cofm(&mut self) -> COFM_W<'_>

Bits 18:21 - Comparator output filter window

pub fn cofc(&mut self) -> COFC_W<'_>

Bits 24:25 - Comparator output filter control

impl W<u32, Reg<u32, _PLC>>

pub fn ipls(&mut self) -> IPLS_W<'_>

Bits 0:3 - Clamping control signal selector

pub fn plcl(&mut self) -> PLCL_W<'_>

Bits 8:9 - Clamping control signal level selection

pub fn psl(&mut self) -> PSL_W<'_>

Bit 10 - Output passive level value

pub fn plsw(&mut self) -> PLSW_W<'_>

Bit 11 - Clamped state exit SW configuration

pub fn plec(&mut self) -> PLEC_W<'_>

Bits 12:13 - Passive level enter configuration

pub fn plxc(&mut self) -> PLXC_W<'_>

Bits 14:15 - Passive level exit configuration

impl W<u32, Reg<u32, _BLV>>

pub fn blv(&mut self) -> BLV_W<'_>

Bits 0:7 - Blanking value

impl W<u32, Reg<u32, _SRE>>

pub fn vls1e(&mut self) -> VLS1E_W<'_>

Bit 0 - Value switch from CSGyDSV1 to CSGyDSV2 interrupt enable

pub fn vls2e(&mut self) -> VLS2E_W<'_>

Bit 1 - Value switch from CSGyDSV2 to CSGyDSV1 interrupt enable

pub fn trgse(&mut self) -> TRGSE_W<'_>

Bit 2 - Conversion trigger interrupt enable

pub fn strse(&mut self) -> STRSE_W<'_>

Bit 3 - Start trigger interrupt enable

pub fn stpse(&mut self) -> STPSE_W<'_>

Bit 4 - Stop trigger interrupt enable

pub fn stde(&mut self) -> STDE_W<'_>

Bit 5 - Shadow transfer done interrupt enable

pub fn crse(&mut self) -> CRSE_W<'_>

Bit 6 - Comparator rise interrupt enable

pub fn cfse(&mut self) -> CFSE_W<'_>

Bit 7 - Comparator fall interrupt enable

pub fn csee(&mut self) -> CSEE_W<'_>

Bit 8 - Clamped state interrupt enable

impl W<u32, Reg<u32, _SRS>>

pub fn vls1s(&mut self) -> VLS1S_W<'_>

Bits 0:1 - Value switch from CSGyDSV1 to CSGyDSV2 interrupt line selection

pub fn vls2s(&mut self) -> VLS2S_W<'_>

Bits 2:3 - Value switch from CSGyDSV2 to CSGyDSV1 interrupt line selection

pub fn trls(&mut self) -> TRLS_W<'_>

Bits 4:5 - Conversion trigger interrupt line selection

pub fn ssls(&mut self) -> SSLS_W<'_>

Bits 6:7 - Start/Stop trigger interrupt line selection

pub fn stls(&mut self) -> STLS_W<'_>

Bits 8:9 - Shadow transfer done interrupt line selection

pub fn crfls(&mut self) -> CRFLS_W<'_>

Bits 10:11 - Comparator rise/fall interrupt line selection

pub fn csls(&mut self) -> CSLS_W<'_>

Bits 12:13 - Comparator clamped state interrupt line selection

impl W<u32, Reg<u32, _SWS>>

pub fn svls1(&mut self) -> SVLS1_W<'_>

Bit 0 - Value switch from CSGyDSV1 to CSGyDSV2 status set

pub fn svls2(&mut self) -> SVLS2_W<'_>

Bit 1 - Value switch from CSGyDSV2 to CSGyDSV1 status set

pub fn strgs(&mut self) -> STRGS_W<'_>

Bit 2 - Conversion trigger status set

pub fn sstrs(&mut self) -> SSTRS_W<'_>

Bit 3 - Start trigger status set

pub fn sstps(&mut self) -> SSTPS_W<'_>

Bit 4 - Stop trigger status set

pub fn sstd(&mut self) -> SSTD_W<'_>

Bit 5 - Shadow transfer status set

pub fn scrs(&mut self) -> SCRS_W<'_>

Bit 6 - Comparator rise status set

pub fn scfs(&mut self) -> SCFS_W<'_>

Bit 7 - Comparator fall status set

pub fn scss(&mut self) -> SCSS_W<'_>

Bit 8 - Comparator clamped state status set

impl W<u32, Reg<u32, _SWC>>

pub fn cvls1(&mut self) -> CVLS1_W<'_>

Bit 0 - Value switch from CSGyDSV1 to CSGyDSV2 status clear

pub fn cvls2(&mut self) -> CVLS2_W<'_>

Bit 1 - Value switch from CSGyDSV2 to CSGyDSV1 status clear

pub fn ctrgs(&mut self) -> CTRGS_W<'_>

Bit 2 - Conversion trigger status clear

pub fn cstrs(&mut self) -> CSTRS_W<'_>

Bit 3 - Start trigger status clear

pub fn cstps(&mut self) -> CSTPS_W<'_>

Bit 4 - Stop trigger status clear

pub fn cstd(&mut self) -> CSTD_W<'_>

Bit 5 - Shadow transfer status clear

pub fn ccrs(&mut self) -> CCRS_W<'_>

Bit 6 - Comparator rise status clear

pub fn ccfs(&mut self) -> CCFS_W<'_>

Bit 7 - Comparator fall status clear

pub fn ccss(&mut self) -> CCSS_W<'_>

Bit 8 - Comparator clamped status clear

impl W<u32, Reg<u32, _GC>>

pub fn hrm0(&mut self) -> HRM0_W<'_>

Bits 0:1 - HRCy high resolution mode configuration for source selector 0

pub fn hrm1(&mut self) -> HRM1_W<'_>

Bits 2:3 - HRCy high resolution mode configuration for source selector 1

pub fn dte(&mut self) -> DTE_W<'_>

Bit 8 - HRCy dead time enable

pub fn tr0e(&mut self) -> TR0E_W<'_>

Bit 9 - HRCy trap enable

pub fn tr1e(&mut self) -> TR1E_W<'_>

Bit 10 - HRCy complementary trap enable

pub fn stc(&mut self) -> STC_W<'_>

Bit 11 - HRCy shadow transfer configuration

pub fn dstc(&mut self) -> DSTC_W<'_>

Bit 12 - HRCy dead time shadow transfer configuration

pub fn ocs0(&mut self) -> OCS0_W<'_>

Bit 13 - HRPWMx.OUTy0 channel selector

pub fn ocs1(&mut self) -> OCS1_W<'_>

Bit 14 - HRPWMx.OUTy1 channel selector

pub fn dtus(&mut self) -> DTUS_W<'_>

Bit 16 - Dead Time update trigger selector

impl W<u32, Reg<u32, _PL>>

pub fn psl0(&mut self) -> PSL0_W<'_>

Bit 0 - HRPWMx.OUTy0 passive level

pub fn psl1(&mut self) -> PSL1_W<'_>

Bit 1 - HRPWMx.OUTy1 passive level

impl W<u32, Reg<u32, _GSEL>>

pub fn c0ss(&mut self) -> C0SS_W<'_>

Bits 0:2 - Source selector 0 comparator set configuration

pub fn c0cs(&mut self) -> C0CS_W<'_>

Bits 3:5 - Source selector 0 comparator clear configuration

pub fn s0m(&mut self) -> S0M_W<'_>

Bits 6:7 - Source selector 0 set configuration

pub fn c0m(&mut self) -> C0M_W<'_>

Bits 8:9 - Source selector 0 clear configuration

pub fn s0es(&mut self) -> S0ES_W<'_>

Bits 10:11 - Source selector 0 set edge configuration

pub fn c0es(&mut self) -> C0ES_W<'_>

Bits 12:13 - Source selector 0 clear edge configuration

pub fn c1ss(&mut self) -> C1SS_W<'_>

Bits 16:18 - Source selector 1 comparator set configuration

pub fn c1cs(&mut self) -> C1CS_W<'_>

Bits 19:21 - Source selector 1 comparator clear configuration

pub fn s1m(&mut self) -> S1M_W<'_>

Bits 22:23 - Source selector 1 set configuration

pub fn c1m(&mut self) -> C1M_W<'_>

Bits 24:25 - Source selector 1 clear configuration

pub fn s1es(&mut self) -> S1ES_W<'_>

Bits 26:27 - Source selector 1 set edge configuration

pub fn c1es(&mut self) -> C1ES_W<'_>

Bits 28:29 - Source selector 1 clear edge configuration

impl W<u32, Reg<u32, _TSEL>>

pub fn tsel0(&mut self) -> TSEL0_W<'_>

Bits 0:2 - Source Selector 0 Timer connection

pub fn tsel1(&mut self) -> TSEL1_W<'_>

Bits 3:5 - Source Selector 1 Timer connection

pub fn ts0e(&mut self) -> TS0E_W<'_>

Bit 16 - Source selector 0 TRAP enable

pub fn ts1e(&mut self) -> TS1E_W<'_>

Bit 17 - Source selector 1 TRAP enable

impl W<u32, Reg<u32, _SSC>>

pub fn sst(&mut self) -> SST_W<'_>

Bit 0 - Source selector for the shadow transfer

impl W<u32, Reg<u32, _SDCR>>

pub fn sdtrv(&mut self) -> SDTRV_W<'_>

Bits 0:15 - Shadow dead time rising value

impl W<u32, Reg<u32, _SDCF>>

pub fn sdtfv(&mut self) -> SDTFV_W<'_>

Bits 0:15 - Shadow dead time falling value

impl W<u32, Reg<u32, _SCR1>>

pub fn scr1(&mut self) -> SCR1_W<'_>

Bits 0:7 - High resolution falling edge value

impl W<u32, Reg<u32, _SCR2>>

pub fn scr2(&mut self) -> SCR2_W<'_>

Bits 0:7 - High resolution rising edge value

impl W<u32, Reg<u32, _PCONF>>

pub fn fsel(&mut self) -> FSEL_W<'_>

Bits 0:1 - Function Selector

pub fn qdcm(&mut self) -> QDCM_W<'_>

Bit 2 - Position Decoder Mode selection

pub fn hidg(&mut self) -> HIDG_W<'_>

Bit 4 - Idle generation enable

pub fn mcue(&mut self) -> MCUE_W<'_>

Bit 5 - Multi-Channel Pattern SW update enable

pub fn insel0(&mut self) -> INSEL0_W<'_>

Bits 8:9 - PhaseA/Hal input 1 selector

pub fn insel1(&mut self) -> INSEL1_W<'_>

Bits 10:11 - PhaseB/Hall input 2 selector

pub fn insel2(&mut self) -> INSEL2_W<'_>

Bits 12:13 - Index/Hall input 3 selector

pub fn dsel(&mut self) -> DSEL_W<'_>

Bit 16 - Delay Pin selector

pub fn spes(&mut self) -> SPES_W<'_>

Bit 17 - Edge selector for the sampling trigger

pub fn msets(&mut self) -> MSETS_W<'_>

Bits 18:20 - Pattern update signal select

pub fn mses(&mut self) -> MSES_W<'_>

Bit 21 - Multi-Channel pattern update trigger edge

pub fn msyns(&mut self) -> MSYNS_W<'_>

Bits 22:23 - PWM synchronization signal selector

pub fn ewis(&mut self) -> EWIS_W<'_>

Bits 24:25 - Wrong Hall Event selection

pub fn ewie(&mut self) -> EWIE_W<'_>

Bit 26 - External Wrong Hall Event enable

pub fn ewil(&mut self) -> EWIL_W<'_>

Bit 27 - External Wrong Hall Event active level

pub fn lpc(&mut self) -> LPC_W<'_>

Bits 28:30 - Low Pass Filters Configuration

impl W<u32, Reg<u32, _PSUS>>

pub fn qsus(&mut self) -> QSUS_W<'_>

Bits 0:1 - Quadrature Mode Suspend Config

pub fn msus(&mut self) -> MSUS_W<'_>

Bits 2:3 - Multi-Channel Mode Suspend Config

impl W<u32, Reg<u32, _PRUNS>>

pub fn srb(&mut self) -> SRB_W<'_>

Bit 0 - Set Run bit

impl W<u32, Reg<u32, _PRUNC>>

pub fn crb(&mut self) -> CRB_W<'_>

Bit 0 - Clear Run bit

pub fn csm(&mut self) -> CSM_W<'_>

Bit 1 - Clear Current internal status

impl W<u32, Reg<u32, _HALPS>>

pub fn hcps(&mut self) -> HCPS_W<'_>

Bits 0:2 - Shadow Hall Current Pattern

pub fn heps(&mut self) -> HEPS_W<'_>

Bits 3:5 - Shadow Hall expected Pattern

impl W<u32, Reg<u32, _MCSM>>

pub fn mcmps(&mut self) -> MCMPS_W<'_>

Bits 0:15 - Shadow Multi-Channel Pattern

impl W<u32, Reg<u32, _MCMS>>

pub fn mnps(&mut self) -> MNPS_W<'_>

Bit 0 - Multi-Channel Pattern Update Enable Set

pub fn sthr(&mut self) -> STHR_W<'_>

Bit 1 - Hall Pattern Shadow Transfer Request

pub fn stmr(&mut self) -> STMR_W<'_>

Bit 2 - Multi-Channel Shadow Transfer Request

impl W<u32, Reg<u32, _MCMC>>

pub fn mnpc(&mut self) -> MNPC_W<'_>

Bit 0 - Multi-Channel Pattern Update Enable Clear

pub fn mpc(&mut self) -> MPC_W<'_>

Bit 1 - Multi-Channel Pattern clear

impl W<u32, Reg<u32, _QDC>>

pub fn pals(&mut self) -> PALS_W<'_>

Bit 0 - Phase A Level selector

pub fn pbls(&mut self) -> PBLS_W<'_>

Bit 1 - Phase B Level selector

pub fn phs(&mut self) -> PHS_W<'_>

Bit 2 - Phase signals swap

pub fn icm(&mut self) -> ICM_W<'_>

Bits 4:5 - Index Marker generations control

impl W<u32, Reg<u32, _PFLGE>>

pub fn eche(&mut self) -> ECHE_W<'_>

Bit 0 - Correct Hall Event Enable

pub fn ewhe(&mut self) -> EWHE_W<'_>

Bit 1 - Wrong Hall Event Enable

pub fn ehie(&mut self) -> EHIE_W<'_>

Bit 2 - Hall Input Update Enable

pub fn emst(&mut self) -> EMST_W<'_>

Bit 4 - Multi-Channel pattern shadow transfer enable

pub fn eindx(&mut self) -> EINDX_W<'_>

Bit 8 - Quadrature Index Event Enable

pub fn eerr(&mut self) -> EERR_W<'_>

Bit 9 - Quadrature Phase Error Enable

pub fn ecnt(&mut self) -> ECNT_W<'_>

Bit 10 - Quadrature CLK interrupt Enable

pub fn edir(&mut self) -> EDIR_W<'_>

Bit 11 - Quadrature direction change interrupt Enable

pub fn epclk(&mut self) -> EPCLK_W<'_>

Bit 12 - Quadrature Period CLK interrupt Enable

pub fn chesel(&mut self) -> CHESEL_W<'_>

Bit 16 - Correct Hall Event Service Request Selector

pub fn whesel(&mut self) -> WHESEL_W<'_>

Bit 17 - Wrong Hall Event Service Request Selector

pub fn hiesel(&mut self) -> HIESEL_W<'_>

Bit 18 - Hall Inputs Update Event Service Request Selector

pub fn mstsel(&mut self) -> MSTSEL_W<'_>

Bit 20 - Multi-Channel pattern Update Event Service Request Selector

pub fn indsel(&mut self) -> INDSEL_W<'_>

Bit 24 - Quadrature Index Event Service Request Selector

pub fn errsel(&mut self) -> ERRSEL_W<'_>

Bit 25 - Quadrature Phase Error Event Service Request Selector

pub fn cntsel(&mut self) -> CNTSEL_W<'_>

Bit 26 - Quadrature Clock Event Service Request Selector

pub fn dirsel(&mut self) -> DIRSEL_W<'_>

Bit 27 - Quadrature Direction Update Event Service Request Selector

pub fn pclsel(&mut self) -> PCLSEL_W<'_>

Bit 28 - Quadrature Period clock Event Service Request Selector

impl W<u32, Reg<u32, _SPFLG>>

pub fn sche(&mut self) -> SCHE_W<'_>

Bit 0 - Correct Hall Event flag set

pub fn swhe(&mut self) -> SWHE_W<'_>

Bit 1 - Wrong Hall Event flag set

pub fn shie(&mut self) -> SHIE_W<'_>

Bit 2 - Hall Inputs Update Event flag set

pub fn smst(&mut self) -> SMST_W<'_>

Bit 4 - Multi-Channel Pattern shadow transfer flag set

pub fn sindx(&mut self) -> SINDX_W<'_>

Bit 8 - Quadrature Index flag set

pub fn serr(&mut self) -> SERR_W<'_>

Bit 9 - Quadrature Phase Error flag set

pub fn scnt(&mut self) -> SCNT_W<'_>

Bit 10 - Quadrature CLK flag set

pub fn sdir(&mut self) -> SDIR_W<'_>

Bit 11 - Quadrature Direction flag set

pub fn spclk(&mut self) -> SPCLK_W<'_>

Bit 12 - Quadrature period clock flag set

impl W<u32, Reg<u32, _RPFLG>>

pub fn rche(&mut self) -> RCHE_W<'_>

Bit 0 - Correct Hall Event flag clear

pub fn rwhe(&mut self) -> RWHE_W<'_>

Bit 1 - Wrong Hall Event flag clear

pub fn rhie(&mut self) -> RHIE_W<'_>

Bit 2 - Hall Inputs Update Event flag clear

pub fn rmst(&mut self) -> RMST_W<'_>

Bit 4 - Multi-Channel Pattern shadow transfer flag clear

pub fn rindx(&mut self) -> RINDX_W<'_>

Bit 8 - Quadrature Index flag clear

pub fn rerr(&mut self) -> RERR_W<'_>

Bit 9 - Quadrature Phase Error flag clear

pub fn rcnt(&mut self) -> RCNT_W<'_>

Bit 10 - Quadrature CLK flag clear

pub fn rdir(&mut self) -> RDIR_W<'_>

Bit 11 - Quadrature Direction flag clear

pub fn rpclk(&mut self) -> RPCLK_W<'_>

Bit 12 - Quadrature period clock flag clear

impl W<u32, Reg<u32, _OUT>>

pub fn p0(&mut self) -> P0_W<'_>

Bit 0 - Port n Output Bit 0

pub fn p1(&mut self) -> P1_W<'_>

Bit 1 - Port n Output Bit 1

pub fn p2(&mut self) -> P2_W<'_>

Bit 2 - Port n Output Bit 2

pub fn p3(&mut self) -> P3_W<'_>

Bit 3 - Port n Output Bit 3

pub fn p4(&mut self) -> P4_W<'_>

Bit 4 - Port n Output Bit 4

pub fn p5(&mut self) -> P5_W<'_>

Bit 5 - Port n Output Bit 5

pub fn p6(&mut self) -> P6_W<'_>

Bit 6 - Port n Output Bit 6

pub fn p7(&mut self) -> P7_W<'_>

Bit 7 - Port n Output Bit 7

pub fn p8(&mut self) -> P8_W<'_>

Bit 8 - Port n Output Bit 8

pub fn p9(&mut self) -> P9_W<'_>

Bit 9 - Port n Output Bit 9

pub fn p10(&mut self) -> P10_W<'_>

Bit 10 - Port n Output Bit 10

pub fn p11(&mut self) -> P11_W<'_>

Bit 11 - Port n Output Bit 11

pub fn p12(&mut self) -> P12_W<'_>

Bit 12 - Port n Output Bit 12

pub fn p13(&mut self) -> P13_W<'_>

Bit 13 - Port n Output Bit 13

pub fn p14(&mut self) -> P14_W<'_>

Bit 14 - Port n Output Bit 14

pub fn p15(&mut self) -> P15_W<'_>

Bit 15 - Port n Output Bit 15

impl W<u32, Reg<u32, _OMR>>

pub fn ps0(&mut self) -> PS0_W<'_>

Bit 0 - Port n Set Bit 0

pub fn ps1(&mut self) -> PS1_W<'_>

Bit 1 - Port n Set Bit 1

pub fn ps2(&mut self) -> PS2_W<'_>

Bit 2 - Port n Set Bit 2

pub fn ps3(&mut self) -> PS3_W<'_>

Bit 3 - Port n Set Bit 3

pub fn ps4(&mut self) -> PS4_W<'_>

Bit 4 - Port n Set Bit 4

pub fn ps5(&mut self) -> PS5_W<'_>

Bit 5 - Port n Set Bit 5

pub fn ps6(&mut self) -> PS6_W<'_>

Bit 6 - Port n Set Bit 6

pub fn ps7(&mut self) -> PS7_W<'_>

Bit 7 - Port n Set Bit 7

pub fn ps8(&mut self) -> PS8_W<'_>

Bit 8 - Port n Set Bit 8

pub fn ps9(&mut self) -> PS9_W<'_>

Bit 9 - Port n Set Bit 9

pub fn ps10(&mut self) -> PS10_W<'_>

Bit 10 - Port n Set Bit 10

pub fn ps11(&mut self) -> PS11_W<'_>

Bit 11 - Port n Set Bit 11

pub fn ps12(&mut self) -> PS12_W<'_>

Bit 12 - Port n Set Bit 12

pub fn ps13(&mut self) -> PS13_W<'_>

Bit 13 - Port n Set Bit 13

pub fn ps14(&mut self) -> PS14_W<'_>

Bit 14 - Port n Set Bit 14

pub fn ps15(&mut self) -> PS15_W<'_>

Bit 15 - Port n Set Bit 15

pub fn pr0(&mut self) -> PR0_W<'_>

Bit 16 - Port n Reset Bit 0

pub fn pr1(&mut self) -> PR1_W<'_>

Bit 17 - Port n Reset Bit 1

pub fn pr2(&mut self) -> PR2_W<'_>

Bit 18 - Port n Reset Bit 2

pub fn pr3(&mut self) -> PR3_W<'_>

Bit 19 - Port n Reset Bit 3

pub fn pr4(&mut self) -> PR4_W<'_>

Bit 20 - Port n Reset Bit 4

pub fn pr5(&mut self) -> PR5_W<'_>

Bit 21 - Port n Reset Bit 5

pub fn pr6(&mut self) -> PR6_W<'_>

Bit 22 - Port n Reset Bit 6

pub fn pr7(&mut self) -> PR7_W<'_>

Bit 23 - Port n Reset Bit 7

pub fn pr8(&mut self) -> PR8_W<'_>

Bit 24 - Port n Reset Bit 8

pub fn pr9(&mut self) -> PR9_W<'_>

Bit 25 - Port n Reset Bit 9

pub fn pr10(&mut self) -> PR10_W<'_>

Bit 26 - Port n Reset Bit 10

pub fn pr11(&mut self) -> PR11_W<'_>

Bit 27 - Port n Reset Bit 11

pub fn pr12(&mut self) -> PR12_W<'_>

Bit 28 - Port n Reset Bit 12

pub fn pr13(&mut self) -> PR13_W<'_>

Bit 29 - Port n Reset Bit 13

pub fn pr14(&mut self) -> PR14_W<'_>

Bit 30 - Port n Reset Bit 14

pub fn pr15(&mut self) -> PR15_W<'_>

Bit 31 - Port n Reset Bit 15

impl W<u32, Reg<u32, _IOCR0>>

pub fn pc0(&mut self) -> PC0_W<'_>

Bits 3:7 - Port Control for Port n Pin 0 to 3

pub fn pc1(&mut self) -> PC1_W<'_>

Bits 11:15 - Port Control for Port n Pin 0 to 3

pub fn pc2(&mut self) -> PC2_W<'_>

Bits 19:23 - Port Control for Port n Pin 0 to 3

pub fn pc3(&mut self) -> PC3_W<'_>

Bits 27:31 - Port Control for Port n Pin 0 to 3

impl W<u32, Reg<u32, _IOCR4>>

pub fn pc4(&mut self) -> PC4_W<'_>

Bits 3:7 - Port Control for Port n Pin 4 to 7

pub fn pc5(&mut self) -> PC5_W<'_>

Bits 11:15 - Port Control for Port n Pin 4 to 7

pub fn pc6(&mut self) -> PC6_W<'_>

Bits 19:23 - Port Control for Port n Pin 4 to 7

pub fn pc7(&mut self) -> PC7_W<'_>

Bits 27:31 - Port Control for Port n Pin 4 to 7

impl W<u32, Reg<u32, _IOCR8>>

pub fn pc8(&mut self) -> PC8_W<'_>

Bits 3:7 - Port Control for Port n Pin 8 to 11

pub fn pc9(&mut self) -> PC9_W<'_>

Bits 11:15 - Port Control for Port n Pin 8 to 11

pub fn pc10(&mut self) -> PC10_W<'_>

Bits 19:23 - Port Control for Port n Pin 8 to 11

pub fn pc11(&mut self) -> PC11_W<'_>

Bits 27:31 - Port Control for Port n Pin 8 to 11

impl W<u32, Reg<u32, _PDR0>>

pub fn pd0(&mut self) -> PD0_W<'_>

Bits 0:2 - Pad Driver Mode for Pn.0

pub fn pd1(&mut self) -> PD1_W<'_>

Bits 4:6 - Pad Driver Mode for Pn.1

pub fn pd2(&mut self) -> PD2_W<'_>

Bits 8:10 - Pad Driver Mode for Pn.2

pub fn pd3(&mut self) -> PD3_W<'_>

Bits 12:14 - Pad Driver Mode for Pn.3

pub fn pd4(&mut self) -> PD4_W<'_>

Bits 16:18 - Pad Driver Mode for Pn.4

pub fn pd5(&mut self) -> PD5_W<'_>

Bits 20:22 - Pad Driver Mode for Pn.5

pub fn pd6(&mut self) -> PD6_W<'_>

Bits 24:26 - Pad Driver Mode for Pn.6

pub fn pd7(&mut self) -> PD7_W<'_>

Bits 28:30 - Pad Driver Mode for Pn.7

impl W<u32, Reg<u32, _PDR1>>

pub fn pd8(&mut self) -> PD8_W<'_>

Bits 0:2 - Pad Driver Mode for Pn.8

pub fn pd9(&mut self) -> PD9_W<'_>

Bits 4:6 - Pad Driver Mode for Pn.9

pub fn pd10(&mut self) -> PD10_W<'_>

Bits 8:10 - Pad Driver Mode for Pn.10

pub fn pd11(&mut self) -> PD11_W<'_>

Bits 12:14 - Pad Driver Mode for Pn.11

pub fn pd12(&mut self) -> PD12_W<'_>

Bits 16:18 - Pad Driver Mode for Pn.12

pub fn pd13(&mut self) -> PD13_W<'_>

Bits 20:22 - Pad Driver Mode for Pn.13

pub fn pd14(&mut self) -> PD14_W<'_>

Bits 24:26 - Pad Driver Mode for Pn.14

pub fn pd15(&mut self) -> PD15_W<'_>

Bits 28:30 - Pad Driver Mode for Pn.15

impl W<u32, Reg<u32, _PPS>>

pub fn pps0(&mut self) -> PPS0_W<'_>

Bit 0 - Port n Pin Power Save Bit 0

pub fn pps1(&mut self) -> PPS1_W<'_>

Bit 1 - Port n Pin Power Save Bit 1

pub fn pps2(&mut self) -> PPS2_W<'_>

Bit 2 - Port n Pin Power Save Bit 2

pub fn pps3(&mut self) -> PPS3_W<'_>

Bit 3 - Port n Pin Power Save Bit 3

pub fn pps4(&mut self) -> PPS4_W<'_>

Bit 4 - Port n Pin Power Save Bit 4

pub fn pps5(&mut self) -> PPS5_W<'_>

Bit 5 - Port n Pin Power Save Bit 5

pub fn pps6(&mut self) -> PPS6_W<'_>

Bit 6 - Port n Pin Power Save Bit 6

pub fn pps7(&mut self) -> PPS7_W<'_>

Bit 7 - Port n Pin Power Save Bit 7

pub fn pps8(&mut self) -> PPS8_W<'_>

Bit 8 - Port n Pin Power Save Bit 8

pub fn pps9(&mut self) -> PPS9_W<'_>

Bit 9 - Port n Pin Power Save Bit 9

pub fn pps10(&mut self) -> PPS10_W<'_>

Bit 10 - Port n Pin Power Save Bit 10

pub fn pps11(&mut self) -> PPS11_W<'_>

Bit 11 - Port n Pin Power Save Bit 11

pub fn pps12(&mut self) -> PPS12_W<'_>

Bit 12 - Port n Pin Power Save Bit 12

pub fn pps13(&mut self) -> PPS13_W<'_>

Bit 13 - Port n Pin Power Save Bit 13

pub fn pps14(&mut self) -> PPS14_W<'_>

Bit 14 - Port n Pin Power Save Bit 14

pub fn pps15(&mut self) -> PPS15_W<'_>

Bit 15 - Port n Pin Power Save Bit 15

impl W<u32, Reg<u32, _HWSEL>>

pub fn hw0(&mut self) -> HW0_W<'_>

Bits 0:1 - Port n Pin Hardware Select Bit 0

pub fn hw1(&mut self) -> HW1_W<'_>

Bits 2:3 - Port n Pin Hardware Select Bit 1

pub fn hw2(&mut self) -> HW2_W<'_>

Bits 4:5 - Port n Pin Hardware Select Bit 2

pub fn hw3(&mut self) -> HW3_W<'_>

Bits 6:7 - Port n Pin Hardware Select Bit 3

pub fn hw4(&mut self) -> HW4_W<'_>

Bits 8:9 - Port n Pin Hardware Select Bit 4

pub fn hw5(&mut self) -> HW5_W<'_>

Bits 10:11 - Port n Pin Hardware Select Bit 5

pub fn hw6(&mut self) -> HW6_W<'_>

Bits 12:13 - Port n Pin Hardware Select Bit 6

pub fn hw7(&mut self) -> HW7_W<'_>

Bits 14:15 - Port n Pin Hardware Select Bit 7

pub fn hw8(&mut self) -> HW8_W<'_>

Bits 16:17 - Port n Pin Hardware Select Bit 8

pub fn hw9(&mut self) -> HW9_W<'_>

Bits 18:19 - Port n Pin Hardware Select Bit 9

pub fn hw10(&mut self) -> HW10_W<'_>

Bits 20:21 - Port n Pin Hardware Select Bit 10

pub fn hw11(&mut self) -> HW11_W<'_>

Bits 22:23 - Port n Pin Hardware Select Bit 11

pub fn hw12(&mut self) -> HW12_W<'_>

Bits 24:25 - Port n Pin Hardware Select Bit 12

pub fn hw13(&mut self) -> HW13_W<'_>

Bits 26:27 - Port n Pin Hardware Select Bit 13

pub fn hw14(&mut self) -> HW14_W<'_>

Bits 28:29 - Port n Pin Hardware Select Bit 14

pub fn hw15(&mut self) -> HW15_W<'_>

Bits 30:31 - Port n Pin Hardware Select Bit 15

impl W<u32, Reg<u32, _OUT>>

pub fn p0(&mut self) -> P0_W<'_>

Bit 0 - Port n Output Bit 0

pub fn p1(&mut self) -> P1_W<'_>

Bit 1 - Port n Output Bit 1

pub fn p2(&mut self) -> P2_W<'_>

Bit 2 - Port n Output Bit 2

pub fn p3(&mut self) -> P3_W<'_>

Bit 3 - Port n Output Bit 3

pub fn p4(&mut self) -> P4_W<'_>

Bit 4 - Port n Output Bit 4

pub fn p5(&mut self) -> P5_W<'_>

Bit 5 - Port n Output Bit 5

pub fn p6(&mut self) -> P6_W<'_>

Bit 6 - Port n Output Bit 6

pub fn p7(&mut self) -> P7_W<'_>

Bit 7 - Port n Output Bit 7

pub fn p8(&mut self) -> P8_W<'_>

Bit 8 - Port n Output Bit 8

pub fn p9(&mut self) -> P9_W<'_>

Bit 9 - Port n Output Bit 9

pub fn p10(&mut self) -> P10_W<'_>

Bit 10 - Port n Output Bit 10

pub fn p11(&mut self) -> P11_W<'_>

Bit 11 - Port n Output Bit 11

pub fn p12(&mut self) -> P12_W<'_>

Bit 12 - Port n Output Bit 12

pub fn p13(&mut self) -> P13_W<'_>

Bit 13 - Port n Output Bit 13

pub fn p14(&mut self) -> P14_W<'_>

Bit 14 - Port n Output Bit 14

pub fn p15(&mut self) -> P15_W<'_>

Bit 15 - Port n Output Bit 15

impl W<u32, Reg<u32, _OMR>>

pub fn ps0(&mut self) -> PS0_W<'_>

Bit 0 - Port n Set Bit 0

pub fn ps1(&mut self) -> PS1_W<'_>

Bit 1 - Port n Set Bit 1

pub fn ps2(&mut self) -> PS2_W<'_>

Bit 2 - Port n Set Bit 2

pub fn ps3(&mut self) -> PS3_W<'_>

Bit 3 - Port n Set Bit 3

pub fn ps4(&mut self) -> PS4_W<'_>

Bit 4 - Port n Set Bit 4

pub fn ps5(&mut self) -> PS5_W<'_>

Bit 5 - Port n Set Bit 5

pub fn ps6(&mut self) -> PS6_W<'_>

Bit 6 - Port n Set Bit 6

pub fn ps7(&mut self) -> PS7_W<'_>

Bit 7 - Port n Set Bit 7

pub fn ps8(&mut self) -> PS8_W<'_>

Bit 8 - Port n Set Bit 8

pub fn ps9(&mut self) -> PS9_W<'_>

Bit 9 - Port n Set Bit 9

pub fn ps10(&mut self) -> PS10_W<'_>

Bit 10 - Port n Set Bit 10

pub fn ps11(&mut self) -> PS11_W<'_>

Bit 11 - Port n Set Bit 11

pub fn ps12(&mut self) -> PS12_W<'_>

Bit 12 - Port n Set Bit 12

pub fn ps13(&mut self) -> PS13_W<'_>

Bit 13 - Port n Set Bit 13

pub fn ps14(&mut self) -> PS14_W<'_>

Bit 14 - Port n Set Bit 14

pub fn ps15(&mut self) -> PS15_W<'_>

Bit 15 - Port n Set Bit 15

pub fn pr0(&mut self) -> PR0_W<'_>

Bit 16 - Port n Reset Bit 0

pub fn pr1(&mut self) -> PR1_W<'_>

Bit 17 - Port n Reset Bit 1

pub fn pr2(&mut self) -> PR2_W<'_>

Bit 18 - Port n Reset Bit 2

pub fn pr3(&mut self) -> PR3_W<'_>

Bit 19 - Port n Reset Bit 3

pub fn pr4(&mut self) -> PR4_W<'_>

Bit 20 - Port n Reset Bit 4

pub fn pr5(&mut self) -> PR5_W<'_>

Bit 21 - Port n Reset Bit 5

pub fn pr6(&mut self) -> PR6_W<'_>

Bit 22 - Port n Reset Bit 6

pub fn pr7(&mut self) -> PR7_W<'_>

Bit 23 - Port n Reset Bit 7

pub fn pr8(&mut self) -> PR8_W<'_>

Bit 24 - Port n Reset Bit 8

pub fn pr9(&mut self) -> PR9_W<'_>

Bit 25 - Port n Reset Bit 9

pub fn pr10(&mut self) -> PR10_W<'_>

Bit 26 - Port n Reset Bit 10

pub fn pr11(&mut self) -> PR11_W<'_>

Bit 27 - Port n Reset Bit 11

pub fn pr12(&mut self) -> PR12_W<'_>

Bit 28 - Port n Reset Bit 12

pub fn pr13(&mut self) -> PR13_W<'_>

Bit 29 - Port n Reset Bit 13

pub fn pr14(&mut self) -> PR14_W<'_>

Bit 30 - Port n Reset Bit 14

pub fn pr15(&mut self) -> PR15_W<'_>

Bit 31 - Port n Reset Bit 15

impl W<u32, Reg<u32, _IOCR0>>

pub fn pc0(&mut self) -> PC0_W<'_>

Bits 3:7 - Port Control for Port n Pin 0 to 3

pub fn pc1(&mut self) -> PC1_W<'_>

Bits 11:15 - Port Control for Port n Pin 0 to 3

pub fn pc2(&mut self) -> PC2_W<'_>

Bits 19:23 - Port Control for Port n Pin 0 to 3

pub fn pc3(&mut self) -> PC3_W<'_>

Bits 27:31 - Port Control for Port n Pin 0 to 3

impl W<u32, Reg<u32, _IOCR4>>

pub fn pc4(&mut self) -> PC4_W<'_>

Bits 3:7 - Port Control for Port n Pin 4 to 7

pub fn pc5(&mut self) -> PC5_W<'_>

Bits 11:15 - Port Control for Port n Pin 4 to 7

pub fn pc6(&mut self) -> PC6_W<'_>

Bits 19:23 - Port Control for Port n Pin 4 to 7

pub fn pc7(&mut self) -> PC7_W<'_>

Bits 27:31 - Port Control for Port n Pin 4 to 7

impl W<u32, Reg<u32, _IOCR8>>

pub fn pc8(&mut self) -> PC8_W<'_>

Bits 3:7 - Port Control for Port n Pin 8 to 11

pub fn pc9(&mut self) -> PC9_W<'_>

Bits 11:15 - Port Control for Port n Pin 8 to 11

pub fn pc10(&mut self) -> PC10_W<'_>

Bits 19:23 - Port Control for Port n Pin 8 to 11

pub fn pc11(&mut self) -> PC11_W<'_>

Bits 27:31 - Port Control for Port n Pin 8 to 11

impl W<u32, Reg<u32, _IOCR12>>

pub fn pc12(&mut self) -> PC12_W<'_>

Bits 3:7 - Port Control for Port n Pin 12 to 15

pub fn pc13(&mut self) -> PC13_W<'_>

Bits 11:15 - Port Control for Port n Pin 12 to 15

pub fn pc14(&mut self) -> PC14_W<'_>

Bits 19:23 - Port Control for Port n Pin 12 to 15

pub fn pc15(&mut self) -> PC15_W<'_>

Bits 27:31 - Port Control for Port n Pin 12 to 15

impl W<u32, Reg<u32, _PDR0>>

pub fn pd0(&mut self) -> PD0_W<'_>

Bits 0:2 - Pad Driver Mode for Pn.0

pub fn pd1(&mut self) -> PD1_W<'_>

Bits 4:6 - Pad Driver Mode for Pn.1

pub fn pd2(&mut self) -> PD2_W<'_>

Bits 8:10 - Pad Driver Mode for Pn.2

pub fn pd3(&mut self) -> PD3_W<'_>

Bits 12:14 - Pad Driver Mode for Pn.3

pub fn pd4(&mut self) -> PD4_W<'_>

Bits 16:18 - Pad Driver Mode for Pn.4

pub fn pd5(&mut self) -> PD5_W<'_>

Bits 20:22 - Pad Driver Mode for Pn.5

pub fn pd6(&mut self) -> PD6_W<'_>

Bits 24:26 - Pad Driver Mode for Pn.6

pub fn pd7(&mut self) -> PD7_W<'_>

Bits 28:30 - Pad Driver Mode for Pn.7

impl W<u32, Reg<u32, _PDR1>>

pub fn pd8(&mut self) -> PD8_W<'_>

Bits 0:2 - Pad Driver Mode for Pn.8

pub fn pd9(&mut self) -> PD9_W<'_>

Bits 4:6 - Pad Driver Mode for Pn.9

pub fn pd10(&mut self) -> PD10_W<'_>

Bits 8:10 - Pad Driver Mode for Pn.10

pub fn pd11(&mut self) -> PD11_W<'_>

Bits 12:14 - Pad Driver Mode for Pn.11

pub fn pd12(&mut self) -> PD12_W<'_>

Bits 16:18 - Pad Driver Mode for Pn.12

pub fn pd13(&mut self) -> PD13_W<'_>

Bits 20:22 - Pad Driver Mode for Pn.13

pub fn pd14(&mut self) -> PD14_W<'_>

Bits 24:26 - Pad Driver Mode for Pn.14

pub fn pd15(&mut self) -> PD15_W<'_>

Bits 28:30 - Pad Driver Mode for Pn.15

impl W<u32, Reg<u32, _PPS>>

pub fn pps0(&mut self) -> PPS0_W<'_>

Bit 0 - Port n Pin Power Save Bit 0

pub fn pps1(&mut self) -> PPS1_W<'_>

Bit 1 - Port n Pin Power Save Bit 1

pub fn pps2(&mut self) -> PPS2_W<'_>

Bit 2 - Port n Pin Power Save Bit 2

pub fn pps3(&mut self) -> PPS3_W<'_>

Bit 3 - Port n Pin Power Save Bit 3

pub fn pps4(&mut self) -> PPS4_W<'_>

Bit 4 - Port n Pin Power Save Bit 4

pub fn pps5(&mut self) -> PPS5_W<'_>

Bit 5 - Port n Pin Power Save Bit 5

pub fn pps6(&mut self) -> PPS6_W<'_>

Bit 6 - Port n Pin Power Save Bit 6

pub fn pps7(&mut self) -> PPS7_W<'_>

Bit 7 - Port n Pin Power Save Bit 7

pub fn pps8(&mut self) -> PPS8_W<'_>

Bit 8 - Port n Pin Power Save Bit 8

pub fn pps9(&mut self) -> PPS9_W<'_>

Bit 9 - Port n Pin Power Save Bit 9

pub fn pps10(&mut self) -> PPS10_W<'_>

Bit 10 - Port n Pin Power Save Bit 10

pub fn pps11(&mut self) -> PPS11_W<'_>

Bit 11 - Port n Pin Power Save Bit 11

pub fn pps12(&mut self) -> PPS12_W<'_>

Bit 12 - Port n Pin Power Save Bit 12

pub fn pps13(&mut self) -> PPS13_W<'_>

Bit 13 - Port n Pin Power Save Bit 13

pub fn pps14(&mut self) -> PPS14_W<'_>

Bit 14 - Port n Pin Power Save Bit 14

pub fn pps15(&mut self) -> PPS15_W<'_>

Bit 15 - Port n Pin Power Save Bit 15

impl W<u32, Reg<u32, _HWSEL>>

pub fn hw0(&mut self) -> HW0_W<'_>

Bits 0:1 - Port n Pin Hardware Select Bit 0

pub fn hw1(&mut self) -> HW1_W<'_>

Bits 2:3 - Port n Pin Hardware Select Bit 1

pub fn hw2(&mut self) -> HW2_W<'_>

Bits 4:5 - Port n Pin Hardware Select Bit 2

pub fn hw3(&mut self) -> HW3_W<'_>

Bits 6:7 - Port n Pin Hardware Select Bit 3

pub fn hw4(&mut self) -> HW4_W<'_>

Bits 8:9 - Port n Pin Hardware Select Bit 4

pub fn hw5(&mut self) -> HW5_W<'_>

Bits 10:11 - Port n Pin Hardware Select Bit 5

pub fn hw6(&mut self) -> HW6_W<'_>

Bits 12:13 - Port n Pin Hardware Select Bit 6

pub fn hw7(&mut self) -> HW7_W<'_>

Bits 14:15 - Port n Pin Hardware Select Bit 7

pub fn hw8(&mut self) -> HW8_W<'_>

Bits 16:17 - Port n Pin Hardware Select Bit 8

pub fn hw9(&mut self) -> HW9_W<'_>

Bits 18:19 - Port n Pin Hardware Select Bit 9

pub fn hw10(&mut self) -> HW10_W<'_>

Bits 20:21 - Port n Pin Hardware Select Bit 10

pub fn hw11(&mut self) -> HW11_W<'_>

Bits 22:23 - Port n Pin Hardware Select Bit 11

pub fn hw12(&mut self) -> HW12_W<'_>

Bits 24:25 - Port n Pin Hardware Select Bit 12

pub fn hw13(&mut self) -> HW13_W<'_>

Bits 26:27 - Port n Pin Hardware Select Bit 13

pub fn hw14(&mut self) -> HW14_W<'_>

Bits 28:29 - Port n Pin Hardware Select Bit 14

pub fn hw15(&mut self) -> HW15_W<'_>

Bits 30:31 - Port n Pin Hardware Select Bit 15

impl W<u32, Reg<u32, _OUT>>

pub fn p0(&mut self) -> P0_W<'_>

Bit 0 - Port n Output Bit 0

pub fn p1(&mut self) -> P1_W<'_>

Bit 1 - Port n Output Bit 1

pub fn p2(&mut self) -> P2_W<'_>

Bit 2 - Port n Output Bit 2

pub fn p3(&mut self) -> P3_W<'_>

Bit 3 - Port n Output Bit 3

pub fn p4(&mut self) -> P4_W<'_>

Bit 4 - Port n Output Bit 4

pub fn p5(&mut self) -> P5_W<'_>

Bit 5 - Port n Output Bit 5

pub fn p6(&mut self) -> P6_W<'_>

Bit 6 - Port n Output Bit 6

pub fn p7(&mut self) -> P7_W<'_>

Bit 7 - Port n Output Bit 7

pub fn p8(&mut self) -> P8_W<'_>

Bit 8 - Port n Output Bit 8

pub fn p9(&mut self) -> P9_W<'_>

Bit 9 - Port n Output Bit 9

pub fn p10(&mut self) -> P10_W<'_>

Bit 10 - Port n Output Bit 10

pub fn p11(&mut self) -> P11_W<'_>

Bit 11 - Port n Output Bit 11

pub fn p12(&mut self) -> P12_W<'_>

Bit 12 - Port n Output Bit 12

pub fn p13(&mut self) -> P13_W<'_>

Bit 13 - Port n Output Bit 13

pub fn p14(&mut self) -> P14_W<'_>

Bit 14 - Port n Output Bit 14

pub fn p15(&mut self) -> P15_W<'_>

Bit 15 - Port n Output Bit 15

impl W<u32, Reg<u32, _OMR>>

pub fn ps0(&mut self) -> PS0_W<'_>

Bit 0 - Port n Set Bit 0

pub fn ps1(&mut self) -> PS1_W<'_>

Bit 1 - Port n Set Bit 1

pub fn ps2(&mut self) -> PS2_W<'_>

Bit 2 - Port n Set Bit 2

pub fn ps3(&mut self) -> PS3_W<'_>

Bit 3 - Port n Set Bit 3

pub fn ps4(&mut self) -> PS4_W<'_>

Bit 4 - Port n Set Bit 4

pub fn ps5(&mut self) -> PS5_W<'_>

Bit 5 - Port n Set Bit 5

pub fn ps6(&mut self) -> PS6_W<'_>

Bit 6 - Port n Set Bit 6

pub fn ps7(&mut self) -> PS7_W<'_>

Bit 7 - Port n Set Bit 7

pub fn ps8(&mut self) -> PS8_W<'_>

Bit 8 - Port n Set Bit 8

pub fn ps9(&mut self) -> PS9_W<'_>

Bit 9 - Port n Set Bit 9

pub fn ps10(&mut self) -> PS10_W<'_>

Bit 10 - Port n Set Bit 10

pub fn ps11(&mut self) -> PS11_W<'_>

Bit 11 - Port n Set Bit 11

pub fn ps12(&mut self) -> PS12_W<'_>

Bit 12 - Port n Set Bit 12

pub fn ps13(&mut self) -> PS13_W<'_>

Bit 13 - Port n Set Bit 13

pub fn ps14(&mut self) -> PS14_W<'_>

Bit 14 - Port n Set Bit 14

pub fn ps15(&mut self) -> PS15_W<'_>

Bit 15 - Port n Set Bit 15

pub fn pr0(&mut self) -> PR0_W<'_>

Bit 16 - Port n Reset Bit 0

pub fn pr1(&mut self) -> PR1_W<'_>

Bit 17 - Port n Reset Bit 1

pub fn pr2(&mut self) -> PR2_W<'_>

Bit 18 - Port n Reset Bit 2

pub fn pr3(&mut self) -> PR3_W<'_>

Bit 19 - Port n Reset Bit 3

pub fn pr4(&mut self) -> PR4_W<'_>

Bit 20 - Port n Reset Bit 4

pub fn pr5(&mut self) -> PR5_W<'_>

Bit 21 - Port n Reset Bit 5

pub fn pr6(&mut self) -> PR6_W<'_>

Bit 22 - Port n Reset Bit 6

pub fn pr7(&mut self) -> PR7_W<'_>

Bit 23 - Port n Reset Bit 7

pub fn pr8(&mut self) -> PR8_W<'_>

Bit 24 - Port n Reset Bit 8

pub fn pr9(&mut self) -> PR9_W<'_>

Bit 25 - Port n Reset Bit 9

pub fn pr10(&mut self) -> PR10_W<'_>

Bit 26 - Port n Reset Bit 10

pub fn pr11(&mut self) -> PR11_W<'_>

Bit 27 - Port n Reset Bit 11

pub fn pr12(&mut self) -> PR12_W<'_>

Bit 28 - Port n Reset Bit 12

pub fn pr13(&mut self) -> PR13_W<'_>

Bit 29 - Port n Reset Bit 13

pub fn pr14(&mut self) -> PR14_W<'_>

Bit 30 - Port n Reset Bit 14

pub fn pr15(&mut self) -> PR15_W<'_>

Bit 31 - Port n Reset Bit 15

impl W<u32, Reg<u32, _IOCR0>>

pub fn pc0(&mut self) -> PC0_W<'_>

Bits 3:7 - Port Control for Port n Pin 0 to 3

pub fn pc1(&mut self) -> PC1_W<'_>

Bits 11:15 - Port Control for Port n Pin 0 to 3

pub fn pc2(&mut self) -> PC2_W<'_>

Bits 19:23 - Port Control for Port n Pin 0 to 3

pub fn pc3(&mut self) -> PC3_W<'_>

Bits 27:31 - Port Control for Port n Pin 0 to 3

impl W<u32, Reg<u32, _IOCR4>>

pub fn pc4(&mut self) -> PC4_W<'_>

Bits 3:7 - Port Control for Port n Pin 4 to 7

pub fn pc5(&mut self) -> PC5_W<'_>

Bits 11:15 - Port Control for Port n Pin 4 to 7

pub fn pc6(&mut self) -> PC6_W<'_>

Bits 19:23 - Port Control for Port n Pin 4 to 7

pub fn pc7(&mut self) -> PC7_W<'_>

Bits 27:31 - Port Control for Port n Pin 4 to 7

impl W<u32, Reg<u32, _IOCR8>>

pub fn pc8(&mut self) -> PC8_W<'_>

Bits 3:7 - Port Control for Port n Pin 8 to 11

pub fn pc9(&mut self) -> PC9_W<'_>

Bits 11:15 - Port Control for Port n Pin 8 to 11

pub fn pc10(&mut self) -> PC10_W<'_>

Bits 19:23 - Port Control for Port n Pin 8 to 11

pub fn pc11(&mut self) -> PC11_W<'_>

Bits 27:31 - Port Control for Port n Pin 8 to 11

impl W<u32, Reg<u32, _IOCR12>>

pub fn pc12(&mut self) -> PC12_W<'_>

Bits 3:7 - Port Control for Port n Pin 12 to 15

pub fn pc13(&mut self) -> PC13_W<'_>

Bits 11:15 - Port Control for Port n Pin 12 to 15

pub fn pc14(&mut self) -> PC14_W<'_>

Bits 19:23 - Port Control for Port n Pin 12 to 15

pub fn pc15(&mut self) -> PC15_W<'_>

Bits 27:31 - Port Control for Port n Pin 12 to 15

impl W<u32, Reg<u32, _PDR0>>

pub fn pd0(&mut self) -> PD0_W<'_>

Bits 0:2 - Pad Driver Mode for Pn.0

pub fn pd1(&mut self) -> PD1_W<'_>

Bits 4:6 - Pad Driver Mode for Pn.1

pub fn pd2(&mut self) -> PD2_W<'_>

Bits 8:10 - Pad Driver Mode for Pn.2

pub fn pd3(&mut self) -> PD3_W<'_>

Bits 12:14 - Pad Driver Mode for Pn.3

pub fn pd4(&mut self) -> PD4_W<'_>

Bits 16:18 - Pad Driver Mode for Pn.4

pub fn pd5(&mut self) -> PD5_W<'_>

Bits 20:22 - Pad Driver Mode for Pn.5

pub fn pd6(&mut self) -> PD6_W<'_>

Bits 24:26 - Pad Driver Mode for Pn.6

pub fn pd7(&mut self) -> PD7_W<'_>

Bits 28:30 - Pad Driver Mode for Pn.7

impl W<u32, Reg<u32, _PDR1>>

pub fn pd8(&mut self) -> PD8_W<'_>

Bits 0:2 - Pad Driver Mode for Pn.8

pub fn pd9(&mut self) -> PD9_W<'_>

Bits 4:6 - Pad Driver Mode for Pn.9

pub fn pd10(&mut self) -> PD10_W<'_>

Bits 8:10 - Pad Driver Mode for Pn.10

pub fn pd11(&mut self) -> PD11_W<'_>

Bits 12:14 - Pad Driver Mode for Pn.11

pub fn pd12(&mut self) -> PD12_W<'_>

Bits 16:18 - Pad Driver Mode for Pn.12

pub fn pd13(&mut self) -> PD13_W<'_>

Bits 20:22 - Pad Driver Mode for Pn.13

pub fn pd14(&mut self) -> PD14_W<'_>

Bits 24:26 - Pad Driver Mode for Pn.14

pub fn pd15(&mut self) -> PD15_W<'_>

Bits 28:30 - Pad Driver Mode for Pn.15

impl W<u32, Reg<u32, _PPS>>

pub fn pps0(&mut self) -> PPS0_W<'_>

Bit 0 - Port n Pin Power Save Bit 0

pub fn pps1(&mut self) -> PPS1_W<'_>

Bit 1 - Port n Pin Power Save Bit 1

pub fn pps2(&mut self) -> PPS2_W<'_>

Bit 2 - Port n Pin Power Save Bit 2

pub fn pps3(&mut self) -> PPS3_W<'_>

Bit 3 - Port n Pin Power Save Bit 3

pub fn pps4(&mut self) -> PPS4_W<'_>

Bit 4 - Port n Pin Power Save Bit 4

pub fn pps5(&mut self) -> PPS5_W<'_>

Bit 5 - Port n Pin Power Save Bit 5

pub fn pps6(&mut self) -> PPS6_W<'_>

Bit 6 - Port n Pin Power Save Bit 6

pub fn pps7(&mut self) -> PPS7_W<'_>

Bit 7 - Port n Pin Power Save Bit 7

pub fn pps8(&mut self) -> PPS8_W<'_>

Bit 8 - Port n Pin Power Save Bit 8

pub fn pps9(&mut self) -> PPS9_W<'_>

Bit 9 - Port n Pin Power Save Bit 9

pub fn pps10(&mut self) -> PPS10_W<'_>

Bit 10 - Port n Pin Power Save Bit 10

pub fn pps11(&mut self) -> PPS11_W<'_>

Bit 11 - Port n Pin Power Save Bit 11

pub fn pps12(&mut self) -> PPS12_W<'_>

Bit 12 - Port n Pin Power Save Bit 12

pub fn pps13(&mut self) -> PPS13_W<'_>

Bit 13 - Port n Pin Power Save Bit 13

pub fn pps14(&mut self) -> PPS14_W<'_>

Bit 14 - Port n Pin Power Save Bit 14

pub fn pps15(&mut self) -> PPS15_W<'_>

Bit 15 - Port n Pin Power Save Bit 15

impl W<u32, Reg<u32, _HWSEL>>

pub fn hw0(&mut self) -> HW0_W<'_>

Bits 0:1 - Port n Pin Hardware Select Bit 0

pub fn hw1(&mut self) -> HW1_W<'_>

Bits 2:3 - Port n Pin Hardware Select Bit 1

pub fn hw2(&mut self) -> HW2_W<'_>

Bits 4:5 - Port n Pin Hardware Select Bit 2

pub fn hw3(&mut self) -> HW3_W<'_>

Bits 6:7 - Port n Pin Hardware Select Bit 3

pub fn hw4(&mut self) -> HW4_W<'_>

Bits 8:9 - Port n Pin Hardware Select Bit 4

pub fn hw5(&mut self) -> HW5_W<'_>

Bits 10:11 - Port n Pin Hardware Select Bit 5

pub fn hw6(&mut self) -> HW6_W<'_>

Bits 12:13 - Port n Pin Hardware Select Bit 6

pub fn hw7(&mut self) -> HW7_W<'_>

Bits 14:15 - Port n Pin Hardware Select Bit 7

pub fn hw8(&mut self) -> HW8_W<'_>

Bits 16:17 - Port n Pin Hardware Select Bit 8

pub fn hw9(&mut self) -> HW9_W<'_>

Bits 18:19 - Port n Pin Hardware Select Bit 9

pub fn hw10(&mut self) -> HW10_W<'_>

Bits 20:21 - Port n Pin Hardware Select Bit 10

pub fn hw11(&mut self) -> HW11_W<'_>

Bits 22:23 - Port n Pin Hardware Select Bit 11

pub fn hw12(&mut self) -> HW12_W<'_>

Bits 24:25 - Port n Pin Hardware Select Bit 12

pub fn hw13(&mut self) -> HW13_W<'_>

Bits 26:27 - Port n Pin Hardware Select Bit 13

pub fn hw14(&mut self) -> HW14_W<'_>

Bits 28:29 - Port n Pin Hardware Select Bit 14

pub fn hw15(&mut self) -> HW15_W<'_>

Bits 30:31 - Port n Pin Hardware Select Bit 15

impl W<u32, Reg<u32, _OUT>>

pub fn p0(&mut self) -> P0_W<'_>

Bit 0 - Port n Output Bit 0

pub fn p1(&mut self) -> P1_W<'_>

Bit 1 - Port n Output Bit 1

pub fn p2(&mut self) -> P2_W<'_>

Bit 2 - Port n Output Bit 2

pub fn p3(&mut self) -> P3_W<'_>

Bit 3 - Port n Output Bit 3

pub fn p4(&mut self) -> P4_W<'_>

Bit 4 - Port n Output Bit 4

pub fn p5(&mut self) -> P5_W<'_>

Bit 5 - Port n Output Bit 5

pub fn p6(&mut self) -> P6_W<'_>

Bit 6 - Port n Output Bit 6

pub fn p7(&mut self) -> P7_W<'_>

Bit 7 - Port n Output Bit 7

pub fn p8(&mut self) -> P8_W<'_>

Bit 8 - Port n Output Bit 8

pub fn p9(&mut self) -> P9_W<'_>

Bit 9 - Port n Output Bit 9

pub fn p10(&mut self) -> P10_W<'_>

Bit 10 - Port n Output Bit 10

pub fn p11(&mut self) -> P11_W<'_>

Bit 11 - Port n Output Bit 11

pub fn p12(&mut self) -> P12_W<'_>

Bit 12 - Port n Output Bit 12

pub fn p13(&mut self) -> P13_W<'_>

Bit 13 - Port n Output Bit 13

pub fn p14(&mut self) -> P14_W<'_>

Bit 14 - Port n Output Bit 14

pub fn p15(&mut self) -> P15_W<'_>

Bit 15 - Port n Output Bit 15

impl W<u32, Reg<u32, _OMR>>

pub fn ps0(&mut self) -> PS0_W<'_>

Bit 0 - Port n Set Bit 0

pub fn ps1(&mut self) -> PS1_W<'_>

Bit 1 - Port n Set Bit 1

pub fn ps2(&mut self) -> PS2_W<'_>

Bit 2 - Port n Set Bit 2

pub fn ps3(&mut self) -> PS3_W<'_>

Bit 3 - Port n Set Bit 3

pub fn ps4(&mut self) -> PS4_W<'_>

Bit 4 - Port n Set Bit 4

pub fn ps5(&mut self) -> PS5_W<'_>

Bit 5 - Port n Set Bit 5

pub fn ps6(&mut self) -> PS6_W<'_>

Bit 6 - Port n Set Bit 6

pub fn ps7(&mut self) -> PS7_W<'_>

Bit 7 - Port n Set Bit 7

pub fn ps8(&mut self) -> PS8_W<'_>

Bit 8 - Port n Set Bit 8

pub fn ps9(&mut self) -> PS9_W<'_>

Bit 9 - Port n Set Bit 9

pub fn ps10(&mut self) -> PS10_W<'_>

Bit 10 - Port n Set Bit 10

pub fn ps11(&mut self) -> PS11_W<'_>

Bit 11 - Port n Set Bit 11

pub fn ps12(&mut self) -> PS12_W<'_>

Bit 12 - Port n Set Bit 12

pub fn ps13(&mut self) -> PS13_W<'_>

Bit 13 - Port n Set Bit 13

pub fn ps14(&mut self) -> PS14_W<'_>

Bit 14 - Port n Set Bit 14

pub fn ps15(&mut self) -> PS15_W<'_>

Bit 15 - Port n Set Bit 15

pub fn pr0(&mut self) -> PR0_W<'_>

Bit 16 - Port n Reset Bit 0

pub fn pr1(&mut self) -> PR1_W<'_>

Bit 17 - Port n Reset Bit 1

pub fn pr2(&mut self) -> PR2_W<'_>

Bit 18 - Port n Reset Bit 2

pub fn pr3(&mut self) -> PR3_W<'_>

Bit 19 - Port n Reset Bit 3

pub fn pr4(&mut self) -> PR4_W<'_>

Bit 20 - Port n Reset Bit 4

pub fn pr5(&mut self) -> PR5_W<'_>

Bit 21 - Port n Reset Bit 5

pub fn pr6(&mut self) -> PR6_W<'_>

Bit 22 - Port n Reset Bit 6

pub fn pr7(&mut self) -> PR7_W<'_>

Bit 23 - Port n Reset Bit 7

pub fn pr8(&mut self) -> PR8_W<'_>

Bit 24 - Port n Reset Bit 8

pub fn pr9(&mut self) -> PR9_W<'_>

Bit 25 - Port n Reset Bit 9

pub fn pr10(&mut self) -> PR10_W<'_>

Bit 26 - Port n Reset Bit 10

pub fn pr11(&mut self) -> PR11_W<'_>

Bit 27 - Port n Reset Bit 11

pub fn pr12(&mut self) -> PR12_W<'_>

Bit 28 - Port n Reset Bit 12

pub fn pr13(&mut self) -> PR13_W<'_>

Bit 29 - Port n Reset Bit 13

pub fn pr14(&mut self) -> PR14_W<'_>

Bit 30 - Port n Reset Bit 14

pub fn pr15(&mut self) -> PR15_W<'_>

Bit 31 - Port n Reset Bit 15

impl W<u32, Reg<u32, _IOCR0>>

pub fn pc0(&mut self) -> PC0_W<'_>

Bits 3:7 - Port Control for Port n Pin 0 to 3

pub fn pc1(&mut self) -> PC1_W<'_>

Bits 11:15 - Port Control for Port n Pin 0 to 3

pub fn pc2(&mut self) -> PC2_W<'_>

Bits 19:23 - Port Control for Port n Pin 0 to 3

pub fn pc3(&mut self) -> PC3_W<'_>

Bits 27:31 - Port Control for Port n Pin 0 to 3

impl W<u32, Reg<u32, _PDR0>>

pub fn pd0(&mut self) -> PD0_W<'_>

Bits 0:2 - Pad Driver Mode for Pn.0

pub fn pd1(&mut self) -> PD1_W<'_>

Bits 4:6 - Pad Driver Mode for Pn.1

pub fn pd2(&mut self) -> PD2_W<'_>

Bits 8:10 - Pad Driver Mode for Pn.2

pub fn pd3(&mut self) -> PD3_W<'_>

Bits 12:14 - Pad Driver Mode for Pn.3

pub fn pd4(&mut self) -> PD4_W<'_>

Bits 16:18 - Pad Driver Mode for Pn.4

pub fn pd5(&mut self) -> PD5_W<'_>

Bits 20:22 - Pad Driver Mode for Pn.5

pub fn pd6(&mut self) -> PD6_W<'_>

Bits 24:26 - Pad Driver Mode for Pn.6

pub fn pd7(&mut self) -> PD7_W<'_>

Bits 28:30 - Pad Driver Mode for Pn.7

impl W<u32, Reg<u32, _PPS>>

pub fn pps0(&mut self) -> PPS0_W<'_>

Bit 0 - Port n Pin Power Save Bit 0

pub fn pps1(&mut self) -> PPS1_W<'_>

Bit 1 - Port n Pin Power Save Bit 1

pub fn pps2(&mut self) -> PPS2_W<'_>

Bit 2 - Port n Pin Power Save Bit 2

pub fn pps3(&mut self) -> PPS3_W<'_>

Bit 3 - Port n Pin Power Save Bit 3

pub fn pps4(&mut self) -> PPS4_W<'_>

Bit 4 - Port n Pin Power Save Bit 4

pub fn pps5(&mut self) -> PPS5_W<'_>

Bit 5 - Port n Pin Power Save Bit 5

pub fn pps6(&mut self) -> PPS6_W<'_>

Bit 6 - Port n Pin Power Save Bit 6

pub fn pps7(&mut self) -> PPS7_W<'_>

Bit 7 - Port n Pin Power Save Bit 7

pub fn pps8(&mut self) -> PPS8_W<'_>

Bit 8 - Port n Pin Power Save Bit 8

pub fn pps9(&mut self) -> PPS9_W<'_>

Bit 9 - Port n Pin Power Save Bit 9

pub fn pps10(&mut self) -> PPS10_W<'_>

Bit 10 - Port n Pin Power Save Bit 10

pub fn pps11(&mut self) -> PPS11_W<'_>

Bit 11 - Port n Pin Power Save Bit 11

pub fn pps12(&mut self) -> PPS12_W<'_>

Bit 12 - Port n Pin Power Save Bit 12

pub fn pps13(&mut self) -> PPS13_W<'_>

Bit 13 - Port n Pin Power Save Bit 13

pub fn pps14(&mut self) -> PPS14_W<'_>

Bit 14 - Port n Pin Power Save Bit 14

pub fn pps15(&mut self) -> PPS15_W<'_>

Bit 15 - Port n Pin Power Save Bit 15

impl W<u32, Reg<u32, _HWSEL>>

pub fn hw0(&mut self) -> HW0_W<'_>

Bits 0:1 - Port n Pin Hardware Select Bit 0

pub fn hw1(&mut self) -> HW1_W<'_>

Bits 2:3 - Port n Pin Hardware Select Bit 1

pub fn hw2(&mut self) -> HW2_W<'_>

Bits 4:5 - Port n Pin Hardware Select Bit 2

pub fn hw3(&mut self) -> HW3_W<'_>

Bits 6:7 - Port n Pin Hardware Select Bit 3

pub fn hw4(&mut self) -> HW4_W<'_>

Bits 8:9 - Port n Pin Hardware Select Bit 4

pub fn hw5(&mut self) -> HW5_W<'_>

Bits 10:11 - Port n Pin Hardware Select Bit 5

pub fn hw6(&mut self) -> HW6_W<'_>

Bits 12:13 - Port n Pin Hardware Select Bit 6

pub fn hw7(&mut self) -> HW7_W<'_>

Bits 14:15 - Port n Pin Hardware Select Bit 7

pub fn hw8(&mut self) -> HW8_W<'_>

Bits 16:17 - Port n Pin Hardware Select Bit 8

pub fn hw9(&mut self) -> HW9_W<'_>

Bits 18:19 - Port n Pin Hardware Select Bit 9

pub fn hw10(&mut self) -> HW10_W<'_>

Bits 20:21 - Port n Pin Hardware Select Bit 10

pub fn hw11(&mut self) -> HW11_W<'_>

Bits 22:23 - Port n Pin Hardware Select Bit 11

pub fn hw12(&mut self) -> HW12_W<'_>

Bits 24:25 - Port n Pin Hardware Select Bit 12

pub fn hw13(&mut self) -> HW13_W<'_>

Bits 26:27 - Port n Pin Hardware Select Bit 13

pub fn hw14(&mut self) -> HW14_W<'_>

Bits 28:29 - Port n Pin Hardware Select Bit 14

pub fn hw15(&mut self) -> HW15_W<'_>

Bits 30:31 - Port n Pin Hardware Select Bit 15

impl W<u32, Reg<u32, _OUT>>

pub fn p0(&mut self) -> P0_W<'_>

Bit 0 - Port n Output Bit 0

pub fn p1(&mut self) -> P1_W<'_>

Bit 1 - Port n Output Bit 1

pub fn p2(&mut self) -> P2_W<'_>

Bit 2 - Port n Output Bit 2

pub fn p3(&mut self) -> P3_W<'_>

Bit 3 - Port n Output Bit 3

pub fn p4(&mut self) -> P4_W<'_>

Bit 4 - Port n Output Bit 4

pub fn p5(&mut self) -> P5_W<'_>

Bit 5 - Port n Output Bit 5

pub fn p6(&mut self) -> P6_W<'_>

Bit 6 - Port n Output Bit 6

pub fn p7(&mut self) -> P7_W<'_>

Bit 7 - Port n Output Bit 7

pub fn p8(&mut self) -> P8_W<'_>

Bit 8 - Port n Output Bit 8

pub fn p9(&mut self) -> P9_W<'_>

Bit 9 - Port n Output Bit 9

pub fn p10(&mut self) -> P10_W<'_>

Bit 10 - Port n Output Bit 10

pub fn p11(&mut self) -> P11_W<'_>

Bit 11 - Port n Output Bit 11

pub fn p12(&mut self) -> P12_W<'_>

Bit 12 - Port n Output Bit 12

pub fn p13(&mut self) -> P13_W<'_>

Bit 13 - Port n Output Bit 13

pub fn p14(&mut self) -> P14_W<'_>

Bit 14 - Port n Output Bit 14

pub fn p15(&mut self) -> P15_W<'_>

Bit 15 - Port n Output Bit 15

impl W<u32, Reg<u32, _OMR>>

pub fn ps0(&mut self) -> PS0_W<'_>

Bit 0 - Port n Set Bit 0

pub fn ps1(&mut self) -> PS1_W<'_>

Bit 1 - Port n Set Bit 1

pub fn ps2(&mut self) -> PS2_W<'_>

Bit 2 - Port n Set Bit 2

pub fn ps3(&mut self) -> PS3_W<'_>

Bit 3 - Port n Set Bit 3

pub fn ps4(&mut self) -> PS4_W<'_>

Bit 4 - Port n Set Bit 4

pub fn ps5(&mut self) -> PS5_W<'_>

Bit 5 - Port n Set Bit 5

pub fn ps6(&mut self) -> PS6_W<'_>

Bit 6 - Port n Set Bit 6

pub fn ps7(&mut self) -> PS7_W<'_>

Bit 7 - Port n Set Bit 7

pub fn ps8(&mut self) -> PS8_W<'_>

Bit 8 - Port n Set Bit 8

pub fn ps9(&mut self) -> PS9_W<'_>

Bit 9 - Port n Set Bit 9

pub fn ps10(&mut self) -> PS10_W<'_>

Bit 10 - Port n Set Bit 10

pub fn ps11(&mut self) -> PS11_W<'_>

Bit 11 - Port n Set Bit 11

pub fn ps12(&mut self) -> PS12_W<'_>

Bit 12 - Port n Set Bit 12

pub fn ps13(&mut self) -> PS13_W<'_>

Bit 13 - Port n Set Bit 13

pub fn ps14(&mut self) -> PS14_W<'_>

Bit 14 - Port n Set Bit 14

pub fn ps15(&mut self) -> PS15_W<'_>

Bit 15 - Port n Set Bit 15

pub fn pr0(&mut self) -> PR0_W<'_>

Bit 16 - Port n Reset Bit 0

pub fn pr1(&mut self) -> PR1_W<'_>

Bit 17 - Port n Reset Bit 1

pub fn pr2(&mut self) -> PR2_W<'_>

Bit 18 - Port n Reset Bit 2

pub fn pr3(&mut self) -> PR3_W<'_>

Bit 19 - Port n Reset Bit 3

pub fn pr4(&mut self) -> PR4_W<'_>

Bit 20 - Port n Reset Bit 4

pub fn pr5(&mut self) -> PR5_W<'_>

Bit 21 - Port n Reset Bit 5

pub fn pr6(&mut self) -> PR6_W<'_>

Bit 22 - Port n Reset Bit 6

pub fn pr7(&mut self) -> PR7_W<'_>

Bit 23 - Port n Reset Bit 7

pub fn pr8(&mut self) -> PR8_W<'_>

Bit 24 - Port n Reset Bit 8

pub fn pr9(&mut self) -> PR9_W<'_>

Bit 25 - Port n Reset Bit 9

pub fn pr10(&mut self) -> PR10_W<'_>

Bit 26 - Port n Reset Bit 10

pub fn pr11(&mut self) -> PR11_W<'_>

Bit 27 - Port n Reset Bit 11

pub fn pr12(&mut self) -> PR12_W<'_>

Bit 28 - Port n Reset Bit 12

pub fn pr13(&mut self) -> PR13_W<'_>

Bit 29 - Port n Reset Bit 13

pub fn pr14(&mut self) -> PR14_W<'_>

Bit 30 - Port n Reset Bit 14

pub fn pr15(&mut self) -> PR15_W<'_>

Bit 31 - Port n Reset Bit 15

impl W<u32, Reg<u32, _IOCR0>>

pub fn pc0(&mut self) -> PC0_W<'_>

Bits 3:7 - Port Control for Port n Pin 0 to 3

pub fn pc1(&mut self) -> PC1_W<'_>

Bits 11:15 - Port Control for Port n Pin 0 to 3

pub fn pc2(&mut self) -> PC2_W<'_>

Bits 19:23 - Port Control for Port n Pin 0 to 3

pub fn pc3(&mut self) -> PC3_W<'_>

Bits 27:31 - Port Control for Port n Pin 0 to 3

impl W<u32, Reg<u32, _IOCR4>>

pub fn pc4(&mut self) -> PC4_W<'_>

Bits 3:7 - Port Control for Port n Pin 4 to 7

pub fn pc5(&mut self) -> PC5_W<'_>

Bits 11:15 - Port Control for Port n Pin 4 to 7

pub fn pc6(&mut self) -> PC6_W<'_>

Bits 19:23 - Port Control for Port n Pin 4 to 7

pub fn pc7(&mut self) -> PC7_W<'_>

Bits 27:31 - Port Control for Port n Pin 4 to 7

impl W<u32, Reg<u32, _IOCR8>>

pub fn pc8(&mut self) -> PC8_W<'_>

Bits 3:7 - Port Control for Port n Pin 8 to 11

pub fn pc9(&mut self) -> PC9_W<'_>

Bits 11:15 - Port Control for Port n Pin 8 to 11

pub fn pc10(&mut self) -> PC10_W<'_>

Bits 19:23 - Port Control for Port n Pin 8 to 11

pub fn pc11(&mut self) -> PC11_W<'_>

Bits 27:31 - Port Control for Port n Pin 8 to 11

impl W<u32, Reg<u32, _IOCR12>>

pub fn pc12(&mut self) -> PC12_W<'_>

Bits 3:7 - Port Control for Port n Pin 12 to 15

pub fn pc13(&mut self) -> PC13_W<'_>

Bits 11:15 - Port Control for Port n Pin 12 to 15

pub fn pc14(&mut self) -> PC14_W<'_>

Bits 19:23 - Port Control for Port n Pin 12 to 15

pub fn pc15(&mut self) -> PC15_W<'_>

Bits 27:31 - Port Control for Port n Pin 12 to 15

impl W<u32, Reg<u32, _PDISC>>

pub fn pdis0(&mut self) -> PDIS0_W<'_>

Bit 0 - Pad Disable for Port n Pin 0

pub fn pdis1(&mut self) -> PDIS1_W<'_>

Bit 1 - Pad Disable for Port n Pin 1

pub fn pdis2(&mut self) -> PDIS2_W<'_>

Bit 2 - Pad Disable for Port n Pin 2

pub fn pdis3(&mut self) -> PDIS3_W<'_>

Bit 3 - Pad Disable for Port n Pin 3

pub fn pdis4(&mut self) -> PDIS4_W<'_>

Bit 4 - Pad Disable for Port n Pin 4

pub fn pdis5(&mut self) -> PDIS5_W<'_>

Bit 5 - Pad Disable for Port n Pin 5

pub fn pdis6(&mut self) -> PDIS6_W<'_>

Bit 6 - Pad Disable for Port n Pin 6

pub fn pdis7(&mut self) -> PDIS7_W<'_>

Bit 7 - Pad Disable for Port n Pin 7

pub fn pdis8(&mut self) -> PDIS8_W<'_>

Bit 8 - Pad Disable for Port n Pin 8

pub fn pdis9(&mut self) -> PDIS9_W<'_>

Bit 9 - Pad Disable for Port n Pin 9

pub fn pdis10(&mut self) -> PDIS10_W<'_>

Bit 10 - Pad Disable for Port n Pin 10

pub fn pdis11(&mut self) -> PDIS11_W<'_>

Bit 11 - Pad Disable for Port n Pin 11

pub fn pdis12(&mut self) -> PDIS12_W<'_>

Bit 12 - Pad Disable for Port n Pin 12

pub fn pdis13(&mut self) -> PDIS13_W<'_>

Bit 13 - Pad Disable for Port n Pin 13

pub fn pdis14(&mut self) -> PDIS14_W<'_>

Bit 14 - Pad Disable for Port n Pin 14

pub fn pdis15(&mut self) -> PDIS15_W<'_>

Bit 15 - Pad Disable for Port n Pin 15

impl W<u32, Reg<u32, _PPS>>

pub fn pps0(&mut self) -> PPS0_W<'_>

Bit 0 - Port n Pin Power Save Bit 0

pub fn pps1(&mut self) -> PPS1_W<'_>

Bit 1 - Port n Pin Power Save Bit 1

pub fn pps2(&mut self) -> PPS2_W<'_>

Bit 2 - Port n Pin Power Save Bit 2

pub fn pps3(&mut self) -> PPS3_W<'_>

Bit 3 - Port n Pin Power Save Bit 3

pub fn pps4(&mut self) -> PPS4_W<'_>

Bit 4 - Port n Pin Power Save Bit 4

pub fn pps5(&mut self) -> PPS5_W<'_>

Bit 5 - Port n Pin Power Save Bit 5

pub fn pps6(&mut self) -> PPS6_W<'_>

Bit 6 - Port n Pin Power Save Bit 6

pub fn pps7(&mut self) -> PPS7_W<'_>

Bit 7 - Port n Pin Power Save Bit 7

pub fn pps8(&mut self) -> PPS8_W<'_>

Bit 8 - Port n Pin Power Save Bit 8

pub fn pps9(&mut self) -> PPS9_W<'_>

Bit 9 - Port n Pin Power Save Bit 9

pub fn pps10(&mut self) -> PPS10_W<'_>

Bit 10 - Port n Pin Power Save Bit 10

pub fn pps11(&mut self) -> PPS11_W<'_>

Bit 11 - Port n Pin Power Save Bit 11

pub fn pps12(&mut self) -> PPS12_W<'_>

Bit 12 - Port n Pin Power Save Bit 12

pub fn pps13(&mut self) -> PPS13_W<'_>

Bit 13 - Port n Pin Power Save Bit 13

pub fn pps14(&mut self) -> PPS14_W<'_>

Bit 14 - Port n Pin Power Save Bit 14

pub fn pps15(&mut self) -> PPS15_W<'_>

Bit 15 - Port n Pin Power Save Bit 15

impl W<u32, Reg<u32, _HWSEL>>

pub fn hw0(&mut self) -> HW0_W<'_>

Bits 0:1 - Port n Pin Hardware Select Bit 0

pub fn hw1(&mut self) -> HW1_W<'_>

Bits 2:3 - Port n Pin Hardware Select Bit 1

pub fn hw2(&mut self) -> HW2_W<'_>

Bits 4:5 - Port n Pin Hardware Select Bit 2

pub fn hw3(&mut self) -> HW3_W<'_>

Bits 6:7 - Port n Pin Hardware Select Bit 3

pub fn hw4(&mut self) -> HW4_W<'_>

Bits 8:9 - Port n Pin Hardware Select Bit 4

pub fn hw5(&mut self) -> HW5_W<'_>

Bits 10:11 - Port n Pin Hardware Select Bit 5

pub fn hw6(&mut self) -> HW6_W<'_>

Bits 12:13 - Port n Pin Hardware Select Bit 6

pub fn hw7(&mut self) -> HW7_W<'_>

Bits 14:15 - Port n Pin Hardware Select Bit 7

pub fn hw8(&mut self) -> HW8_W<'_>

Bits 16:17 - Port n Pin Hardware Select Bit 8

pub fn hw9(&mut self) -> HW9_W<'_>

Bits 18:19 - Port n Pin Hardware Select Bit 9

pub fn hw10(&mut self) -> HW10_W<'_>

Bits 20:21 - Port n Pin Hardware Select Bit 10

pub fn hw11(&mut self) -> HW11_W<'_>

Bits 22:23 - Port n Pin Hardware Select Bit 11

pub fn hw12(&mut self) -> HW12_W<'_>

Bits 24:25 - Port n Pin Hardware Select Bit 12

pub fn hw13(&mut self) -> HW13_W<'_>

Bits 26:27 - Port n Pin Hardware Select Bit 13

pub fn hw14(&mut self) -> HW14_W<'_>

Bits 28:29 - Port n Pin Hardware Select Bit 14

pub fn hw15(&mut self) -> HW15_W<'_>

Bits 30:31 - Port n Pin Hardware Select Bit 15