Expand description
Description of the data-structures for IA-32e paging mode.
Structs
A type wrapping a huge page with a 1 GiB buffer.
A wrapper for an IO address (IOVA / DMA Address for devices)
A type wrapping a large page with a 2 MiB buffer.
A wrapper for a physical address.
A PD Entry consists of an address and a bunch of flags.
PD configuration bits description.
A PDPT Entry consists of an address and a bunch of flags.
PDPT configuration bit description.
A PML4 Entry consists of an address and a bunch of flags.
PML4 configuration bit description.
A PML5 Entry consists of an address and a bunch of flags.
PML5 configuration bit description.
A PT Entry consists of an address and a bunch of flags.
PT Entry bits description.
A type wrapping a base page with a 4 KiB buffer.
A wrapper for a virtual address.
Constants
Log2 of base page size (12 bits).
Size of a base page (4 KiB)
Size of a cache-line
Size of a huge page (1 GiB)
Size of a large page (2 MiB)
MAXPHYADDR, which is at most 52; (use CPUID for finding system value).
Maximum virtual address.
Maximum supported bits for virtual addresses (with 5-level paging)
Page tables have 512 = 4096 / 64 entries.
Functions
Given virtual address calculate corresponding entry in PD.
Given virtual address calculate corresponding entry in PDPT.
Given virtual address calculate corresponding entry in PT.