[−][src]Constant x86::xapic::XAPIC_TIMER_DIV_CONF
pub const XAPIC_TIMER_DIV_CONF: u32
Divide Configuration Register (DCR; for Timer). Read/write. See Figure 10-10 for reserved bits.
pub const XAPIC_TIMER_DIV_CONF: u32
Divide Configuration Register (DCR; for Timer). Read/write. See Figure 10-10 for reserved bits.