LRM 6.6 Alias declarations
LRM 3.3 Architecture bodies
LRM 10.3 Assertion statement
LRM 6.5.7 Association Lists
LRM 6.7 Attribute declarations
LRM 8.6 Attribute names
LRM 7.2 Attribute specification
LRM 7.3.2 Binding indication
LRM 15.8 Bit string literals
LRM 3.4 Configuration declarations
LRM 11.2 Block statement
LRM 11.2 Block statement
LRM 9.3.4 Function calls
LRM 10.9 Case statement
LRM 3.4 Configuration declarations
LRM 6.8 Component declarations
LRM 7.3 Configuration specification
LRM 11.5 Concurrent assertion statements
LRM 11.4 Concurrent procedure call statements
11.6 Concurrent signal assignment statements
LRM 3.4 Configuration declarations
LRM 7.3 Configuration specification
LRM 13.4 Context clauses
LRM 13.4 Context clauses
LRM: record_element_constraint
LRM 5.3.3 Record types
LRM 3.2 Entity declarations
LRM 7.2 Attribute specification
LRM 10.12 Exit statement
LRM 8.7 External names
11.8 Generate statements
LRM 4.2 Subprogram declaration
11.8 Generate statements
11.8 Generate statements
LRM 10.8 If statement
11.7 Component instantiation statements
LRM 6.5.2 Interface object declarations
LRM 6.5.5 Interface package declaration
LRM 11. Concurrent statements
LRM 10. Sequential statements
LRM 13. Design units and their analysis
LRM 10.10 Loop statement
LRM 6.5.2 Interface Object Declarations - Mode view declarations
LRM 10.11 Next statement
LRM 4.8 Package bodies
LRM 4.7 Package declarations
LRM 4.9 Package instantiation declaration
LRM 5.4.2 Physical type declaration
LRM 4.2 Subprogram declaration
LRM 11.3 Process statement
LRM 5.6.3 Protected type bodies
LRM 5.6.2 Protected type declarations
LRM 9.3.5 Qualified expressions
LRM 6.3 Subtype declarations
LRM 10.4 Report statement
LRM 10.13 Return statement
Represents a token-separated list of some generic type T
LRM 10.5 Signal assignment statement
LRM 4.3 Subprogram bodies
LRM 4.2 Subprogram declarations
LRM 4.2.1 Subprogram Header
Note that, as opposed to the standard, the header is not optional.
Instead, the element that contains the header (e.g., procedure specifications)
mark this element as optional.
LRM 4.4 Subprogram Instantiation Statement
LRM 6.3 Subtype declarations
LRM 6.2 Type declarations
LRM 12.4. Use clauses
LRM 7.3.4 Verification unit binding indication
LRM 10.6 Variable assignment statement
LRM 10.2 Wait statement
LRM 10.5 Signal assignment statement
An item which declares a named entity
An item which has a reference to a declaration
LRM 15.5 Abstract literals
LRM 6.5.7 Association Lists
LRM 9.3.7 Allocators
LRM 13.1 Design units
LRM 13.1 Design units
LRM 13.1 Design units
LRM 5.3 Array Types
LRM 10.5 Signal assignment statement
LRM 10.6 Variable assignment statement
LRM 7.2 Attribute specification
LRM 15.8 Bit string literals
LRM 9.3.3 Aggregates
LRM 11. Concurrent statements
LRM 3.4 Configuration declarations
LRM 3.4 Configuration declarations
LRM 13.4 Context clauses
LRM 10.5 Signal assignment statement
LRM discrete_range
discrete_range ::= discrete_subtype_indication | range
range ::=
range_attribute_name
| simple_expression direction simple_expression
LRM 9.3.3 Aggregates
LRM 7.3.2 Binding indication
LRM 7.2 Attribute specification
LRM 7.2 Attribute specification
LRM 5.2.2 Enumeration types
LRM 9. Expressions
LRM 8.7 External names
LRM 8.7 External names
11.7 Component instantiation statements
LRM 7.3 Configuration specification
LRM 6.5.5 Interface package declaration
LRM 10.10 Loop statement
LRM 9.3.2 Literals
LRM 8. Names
LRM 6.4.2 Object Declarations
LRM 5.6.2 Protected type declarations
LRM 6.3 Subtype declarations
LRM 10. Sequential statements
LRM 4.5.3 Signatures
LRM 10.5 Signal assignment statement
LRM 5 Types
LRM 10.5 Signal assignment statement