vexriscv 0.0.3

Low level access to the VexRiscv processor
Documentation
language: rust

env:
  - TARGET=x86_64-unknown-linux-gnu
  - TARGET=riscv32imac-unknown-none-elf

rust:
  - nightly
  - stable
  - 1.30.0 # MSRV

if: (branch = staging OR branch = trying OR branch = master) OR (type = pull_request AND branch = master)

matrix:
  include:
    - env: TARGET=riscv64imac-unknown-none-elf
      rust: nightly
      if: (branch = staging OR branch = trying OR branch = master) OR (type = pull_request AND branch = master)

    - env: TARGET=riscv64gc-unknown-none-elf
      rust: nightly
      if: (branch = staging OR branch = trying OR branch = master) OR (type = pull_request AND branch = master)

    - env: CHECK_BLOBS=1
      rust:
      language: bash
      if: (branch = staging OR branch = trying OR branch = master) OR (type = pull_request AND branch = master)


install:
  - ci/install.sh

script:
  - ci/script.sh


cache:
  cargo: true
  directories:
    - gcc
before_cache:
  # Travis can't cache files that are not readable by "others"
  - chmod -R a+r $HOME/.cargo

branches:
  only:
    - master
    - staging
    - trying

notifications:
  email:
    on_success: never