Veryl

Veryl is a modern hardware description language.

This project is under the exploration phase of language design. If you have any idea, please open Issue.

Documentation quick links

• Features
• Installation
• Usage
• Reference
• License
• Contribution

Features

• Symplified syntax
  • Based on SystemVerilog / Rust
• Transpiler to SystemVerilog
  • Human readable output
  • Interoperability with SystemVerilog
• Integrated Tools
  • Semantic checker
  • Source code formatter
  • Language server

Installation

Download binary

Download from release page, and extract to the directory in PATH.

Cargo

You can install with cargo.

cargo install veryl veryl-ls

Usage

• Create a new package

veryl new [package name]

• Create a new package in an existing directory

veryl init [path]

• Format the current package

veryl fmt

• Analyze the current package

veryl check

• Build target codes corresponding to the current package

veryl build

Package Configuration Example

[package]
name = "name"      # package name
version = "0.1.0"  # package version (semver is recommended)

[build]
clock_type = "posedge"    # default clock type [posedge|negedge]
reset_type = "async_low"  # default reset type [async_low|async_high|sync_low|sync_high]

# output target files in the same location as source
target     = {type = "source"}

# output target files in the specified directory
#target     = {type = "directory", path = "testcases/sv"}

[format]
indent_width = 4  # indent width

Reference

License

Licensed under either of

• Apache License, Version 2.0, (LICENSE-APACHE or http://www.apache.org/licenses/LICENSE-2.0)
• MIT license (LICENSE-MIT or http://opensource.org/licenses/MIT)

at your option.

Contribution

Unless you explicitly state otherwise, any contribution intentionally submitted for inclusion in the work by you, as defined in the Apache-2.0 license, shall be dual licensed as above, without any additional terms or conditions.