Crate unarm
Source - AddrLdrStrPost
- A post-indexed memory address for LDR(B)(T)/STR(B)(T)
- AifFlags
- In a CPS instruction, specifies which interrupt bits to enable or disable
- BranchTarget
- The direct destination address of a branch instruction
- DisplayIns
- DregIndex
- A double-precision floating-point register and index (0 or 1) to move to/from
- DregList
- List of general-purpose double-precision floation-point registers, used by VLDM/VSTM
- Extensions
- Formatter
- Fpscr
- Floating-Point Status and Control Register
- Options
- Parser
- RegList
- List of general-purpose registers, used by LDM/STM
- ShiftImm
- Register shifted by an immediate
- ShiftReg
- Register shifted by another register
- SregList
- List of general-purpose single-precision floation-point registers, used by VLDM/VSTM
- StatusFields
- Status register with field masks
- StringFormatter
- Versions
- AddrLdcStc
- The memory address of an LDC/STC instruction
- AddrLdrStr
- The memory address of an LDR(B)/STR(B)/PLD instruction
- AddrMiscLoad
- The memory address of a miscellaneous load/store instruction
- BlxTarget
- The destination of a BLX instruction, which can be direct (immediate) or indirect (register)
- CoReg
- Coprocessor register
- Cond
- Mnemonic suffix, specifies the condition for whether to execute the instruction
- Coproc
- Coprocessor
- CpsEffect
- Mnemonic suffix for CPS, specifies whether to enable/disable interrupt bits or just set the processor mode
- Dreg
- General-purpose register for double-precision floating-point numbers
- Endianness
- Used by SETEND, specifies the endianness for data accesses
- Extension
- Ins
- LdmStmMode
- Mnemonic suffix for LDM/STM, specifies how to step the base address
- LdrStrOffset
- The offset value in the memory address of a LDR(B)/STR(B) instruction, can be an immediate or a register
- MiscLoadOffset
- The offset value in the memory address of a miscellaneous load/store instruction, can be an immediate or a register
- MsrOp2
- Second operand of the MSR instruction, can be an immediate or a register
- Op2
- Second operand of a data-processing operation, can be an immediate, an immediate-shifted register or a register-shifted register.
- Op2Shift
- Second operand of a shift instruction, can be an immediate or a register
- ParseEndian
- ParseMode
- R9Use
- Reg
- General-purpose register
- RegSide
- Mnemonic suffix, specifies which half of a register to use as an operand
- ShiftOp
- Shift operation
- Sreg
- General-purpose register for single-precision floating-point numbers
- SrsRfeMode
- Mnemonic suffix for SRS/RFE, specifies how to step the stack pointer
- StatusReg
- Status register
- VcmpF32Op2
- Second operand of a VCMP.F32 instruction, can be zero or a register
- VcmpF64Op2
- Second operand of a VCMP.F64 instruction, can be zero or a register
- Version
- VldmVstmMode
- Mnemonic suffix for VLDM/VSTM, specifies how to step the base address
- FormatIns
- FormatValue
- parse_arm
- parse_arm_with_discriminant
- parse_thumb
- parse_thumb_with_discriminant