Enum tydi::generator::common::Type

pub enum Type {
    Bit,
    BitVec {
        width: NonNegative,
    },
    Array(Array),
    Record(Record),
}

Hardware types.

Variants

Bit

A single bit.

BitVec

A vector of bits.

Fields of BitVec

width: NonNegative

The width of the vector.

Array(Array)

A statically-sized array.

Record(Record)

A record.

Methods

impl Type

pub fn bitvec(width: NonNegative) -> Type

Construct a bit vector type.

pub fn record(name: impl Into<String>, fields: Vec<Field>) -> Type

Construct a record type.

pub fn flatten(&self, prefix: Vec<String>, reversed: bool) -> TypeBundle

Flatten a type to a non-nested type bundle.

pub fn has_reversed(&self) -> bool

Trait Implementations

impl Analyze for Type

fn list_record_types(&self) -> Vec<Type>

List all record types used.

impl Clone for Type

fn clone(&self) -> Type

Returns a copy of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for Type

fn fmt(&self, f: &mut Formatter) -> Result

Formats the value using the given formatter.

impl Declare for Type

fn declare(&self) -> Result<String>

Generate a VHDL declaration from self.

impl From<Width> for Type

fn from(width: Width) -> Self

Performs the conversion.

impl PartialEq<Type> for Type

fn eq(&self, other: &Type) -> bool

This method tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Type) -> bool

This method tests for !=.

impl StructuralPartialEq for Type

impl VHDLIdentifier for Type

fn vhdl_identifier(&self) -> Result<String>

Generate a VHDL identifier from self.