Crate topstitch 

Re-exports

pub use lefdef::LefDefOptions;

Modules

lefdef

Macros

for_each_edge_direction

Structs

BoundingBox

CalculatedPlacement

Public placement info for block instances.

Coordinate

Funnel

Mat3

ModDef

Represents a module definition, like module <mod_def_name> ... endmodule in Verilog.

ModInst

Package

Parameter

ParserConfig

PhysicalPin

PipelineConfig

Placement

Polygon

PortSlice

Represents a slice of a port, which may be on a module definition or on a module instance.

Range

Represents an optionally bounded inclusive interval along an edge or track.

SpreadPinsOptions

Options controlling pin spreading behavior.

TrackDefinition

Definition of a routing track family on a named layer.

TrackDefinitions

Collection of track definitions keyed by layer name.

Enums

EdgeOrientation

Enumerates the axis-aligned orientation of an edge.

IO

Represents the direction (Input or Output) and bit width of a port.

Intf

Represents an interface on a module definition or module instance. Interfaces are used to connect modules together by function name.

Orientation

ParameterType

Port

Represents a port on a module definition or a module instance.

TrackOrientation

Orientation of routing tracks.

Usage

Represents how a module definition should be used when validating and/or emitting Verilog.

Constants

BOTTOM_EDGE_INDEX

EAST_EDGE_INDEX

LEFT_EDGE_INDEX

NORTH_EDGE_INDEX

RIGHT_EDGE_INDEX

SOUTH_EDGE_INDEX

TOP_EDGE_INDEX

WEST_EDGE_INDEX

Traits

ConvertibleToModDef

Indicates that a type can be converted to a ModDef. ModDef and ModInst both implement this trait, which makes it easier to perform the same operations on both.

ConvertibleToPortSlice

Indicates that a type can be converted to a PortSlice. Port and PortSlice both implement this trait, which makes it easier to perform the same operations on both.

Functions

extract_packages_from_verilog

extract_packages_from_verilog_file

extract_packages_from_verilog_files

extract_packages_with_config