Struct tm4c129x::pwm0::RegisterBlock

source ·

#[repr(C)]
pub struct RegisterBlock {Show 89 fields
    pub ctl: CTL,
    pub sync: SYNC,
    pub enable: ENABLE,
    pub invert: INVERT,
    pub fault: FAULT,
    pub inten: INTEN,
    pub ris: RIS,
    pub isc: ISC,
    pub status: STATUS,
    pub faultval: FAULTVAL,
    pub enupd: ENUPD,
    pub _0_ctl: _0_CTL,
    pub _0_inten: _0_INTEN,
    pub _0_ris: _0_RIS,
    pub _0_isc: _0_ISC,
    pub _0_load: _0_LOAD,
    pub _0_count: _0_COUNT,
    pub _0_cmpa: _0_CMPA,
    pub _0_cmpb: _0_CMPB,
    pub _0_gena: _0_GENA,
    pub _0_genb: _0_GENB,
    pub _0_dbctl: _0_DBCTL,
    pub _0_dbrise: _0_DBRISE,
    pub _0_dbfall: _0_DBFALL,
    pub _0_fltsrc0: _0_FLTSRC0,
    pub _0_fltsrc1: _0_FLTSRC1,
    pub _0_minfltper: _0_MINFLTPER,
    pub _1_ctl: _1_CTL,
    pub _1_inten: _1_INTEN,
    pub _1_ris: _1_RIS,
    pub _1_isc: _1_ISC,
    pub _1_load: _1_LOAD,
    pub _1_count: _1_COUNT,
    pub _1_cmpa: _1_CMPA,
    pub _1_cmpb: _1_CMPB,
    pub _1_gena: _1_GENA,
    pub _1_genb: _1_GENB,
    pub _1_dbctl: _1_DBCTL,
    pub _1_dbrise: _1_DBRISE,
    pub _1_dbfall: _1_DBFALL,
    pub _1_fltsrc0: _1_FLTSRC0,
    pub _1_fltsrc1: _1_FLTSRC1,
    pub _1_minfltper: _1_MINFLTPER,
    pub _2_ctl: _2_CTL,
    pub _2_inten: _2_INTEN,
    pub _2_ris: _2_RIS,
    pub _2_isc: _2_ISC,
    pub _2_load: _2_LOAD,
    pub _2_count: _2_COUNT,
    pub _2_cmpa: _2_CMPA,
    pub _2_cmpb: _2_CMPB,
    pub _2_gena: _2_GENA,
    pub _2_genb: _2_GENB,
    pub _2_dbctl: _2_DBCTL,
    pub _2_dbrise: _2_DBRISE,
    pub _2_dbfall: _2_DBFALL,
    pub _2_fltsrc0: _2_FLTSRC0,
    pub _2_fltsrc1: _2_FLTSRC1,
    pub _2_minfltper: _2_MINFLTPER,
    pub _3_ctl: _3_CTL,
    pub _3_inten: _3_INTEN,
    pub _3_ris: _3_RIS,
    pub _3_isc: _3_ISC,
    pub _3_load: _3_LOAD,
    pub _3_count: _3_COUNT,
    pub _3_cmpa: _3_CMPA,
    pub _3_cmpb: _3_CMPB,
    pub _3_gena: _3_GENA,
    pub _3_genb: _3_GENB,
    pub _3_dbctl: _3_DBCTL,
    pub _3_dbrise: _3_DBRISE,
    pub _3_dbfall: _3_DBFALL,
    pub _3_fltsrc0: _3_FLTSRC0,
    pub _3_fltsrc1: _3_FLTSRC1,
    pub _3_minfltper: _3_MINFLTPER,
    pub _0_fltsen: _0_FLTSEN,
    pub _0_fltstat0: _0_FLTSTAT0,
    pub _0_fltstat1: _0_FLTSTAT1,
    pub _1_fltsen: _1_FLTSEN,
    pub _1_fltstat0: _1_FLTSTAT0,
    pub _1_fltstat1: _1_FLTSTAT1,
    pub _2_fltsen: _2_FLTSEN,
    pub _2_fltstat0: _2_FLTSTAT0,
    pub _2_fltstat1: _2_FLTSTAT1,
    pub _3_fltsen: _3_FLTSEN,
    pub _3_fltstat0: _3_FLTSTAT0,
    pub _3_fltstat1: _3_FLTSTAT1,
    pub pp: PP,
    pub cc: CC,
    /* private fields */
}

Expand description

Register block

Fields§

§ctl: CTL

0x00 - PWM Master Control

§sync: SYNC

0x04 - PWM Time Base Sync

§enable: ENABLE

0x08 - PWM Output Enable

§invert: INVERT

0x0c - PWM Output Inversion

§fault: FAULT

0x10 - PWM Output Fault

§inten: INTEN

0x14 - PWM Interrupt Enable

§ris: RIS

0x18 - PWM Raw Interrupt Status

§isc: ISC

0x1c - PWM Interrupt Status and Clear

§status: STATUS

0x20 - PWM Status

§faultval: FAULTVAL

0x24 - PWM Fault Condition Value

§enupd: ENUPD

0x28 - PWM Enable Update

§_0_ctl: _0_CTL

0x40 - PWM0 Control

§_0_inten: _0_INTEN

0x44 - PWM0 Interrupt and Trigger Enable

§_0_ris: _0_RIS

0x48 - PWM0 Raw Interrupt Status

§_0_isc: _0_ISC

0x4c - PWM0 Interrupt Status and Clear

§_0_load: _0_LOAD

0x50 - PWM0 Load

§_0_count: _0_COUNT

0x54 - PWM0 Counter

§_0_cmpa: _0_CMPA

0x58 - PWM0 Compare A

§_0_cmpb: _0_CMPB

0x5c - PWM0 Compare B

§_0_gena: _0_GENA

0x60 - PWM0 Generator A Control

§_0_genb: _0_GENB

0x64 - PWM0 Generator B Control

§_0_dbctl: _0_DBCTL

0x68 - PWM0 Dead-Band Control

§_0_dbrise: _0_DBRISE

0x6c - PWM0 Dead-Band Rising-Edge Delay

§_0_dbfall: _0_DBFALL

0x70 - PWM0 Dead-Band Falling-Edge-Delay

§_0_fltsrc0: _0_FLTSRC0

0x74 - PWM0 Fault Source 0

§_0_fltsrc1: _0_FLTSRC1

0x78 - PWM0 Fault Source 1

§_0_minfltper: _0_MINFLTPER

0x7c - PWM0 Minimum Fault Period

§_1_ctl: _1_CTL

0x80 - PWM1 Control

§_1_inten: _1_INTEN

0x84 - PWM1 Interrupt and Trigger Enable

§_1_ris: _1_RIS

0x88 - PWM1 Raw Interrupt Status

§_1_isc: _1_ISC

0x8c - PWM1 Interrupt Status and Clear

§_1_load: _1_LOAD

0x90 - PWM1 Load

§_1_count: _1_COUNT

0x94 - PWM1 Counter

§_1_cmpa: _1_CMPA

0x98 - PWM1 Compare A

§_1_cmpb: _1_CMPB

0x9c - PWM1 Compare B

§_1_gena: _1_GENA

0xa0 - PWM1 Generator A Control

§_1_genb: _1_GENB

0xa4 - PWM1 Generator B Control

§_1_dbctl: _1_DBCTL

0xa8 - PWM1 Dead-Band Control

§_1_dbrise: _1_DBRISE

0xac - PWM1 Dead-Band Rising-Edge Delay

§_1_dbfall: _1_DBFALL

0xb0 - PWM1 Dead-Band Falling-Edge-Delay

§_1_fltsrc0: _1_FLTSRC0

0xb4 - PWM1 Fault Source 0

§_1_fltsrc1: _1_FLTSRC1

0xb8 - PWM1 Fault Source 1

§_1_minfltper: _1_MINFLTPER

0xbc - PWM1 Minimum Fault Period

§_2_ctl: _2_CTL

0xc0 - PWM2 Control

§_2_inten: _2_INTEN

0xc4 - PWM2 Interrupt and Trigger Enable

§_2_ris: _2_RIS

0xc8 - PWM2 Raw Interrupt Status

§_2_isc: _2_ISC

0xcc - PWM2 Interrupt Status and Clear

§_2_load: _2_LOAD

0xd0 - PWM2 Load

§_2_count: _2_COUNT

0xd4 - PWM2 Counter

§_2_cmpa: _2_CMPA

0xd8 - PWM2 Compare A

§_2_cmpb: _2_CMPB

0xdc - PWM2 Compare B

§_2_gena: _2_GENA

0xe0 - PWM2 Generator A Control

§_2_genb: _2_GENB

0xe4 - PWM2 Generator B Control

§_2_dbctl: _2_DBCTL

0xe8 - PWM2 Dead-Band Control

§_2_dbrise: _2_DBRISE

0xec - PWM2 Dead-Band Rising-Edge Delay

§_2_dbfall: _2_DBFALL

0xf0 - PWM2 Dead-Band Falling-Edge-Delay

§_2_fltsrc0: _2_FLTSRC0

0xf4 - PWM2 Fault Source 0

§_2_fltsrc1: _2_FLTSRC1

0xf8 - PWM2 Fault Source 1

§_2_minfltper: _2_MINFLTPER

0xfc - PWM2 Minimum Fault Period

§_3_ctl: _3_CTL

0x100 - PWM3 Control

§_3_inten: _3_INTEN

0x104 - PWM3 Interrupt and Trigger Enable

§_3_ris: _3_RIS

0x108 - PWM3 Raw Interrupt Status

§_3_isc: _3_ISC

0x10c - PWM3 Interrupt Status and Clear

§_3_load: _3_LOAD

0x110 - PWM3 Load

§_3_count: _3_COUNT

0x114 - PWM3 Counter

§_3_cmpa: _3_CMPA

0x118 - PWM3 Compare A

§_3_cmpb: _3_CMPB

0x11c - PWM3 Compare B

§_3_gena: _3_GENA

0x120 - PWM3 Generator A Control

§_3_genb: _3_GENB

0x124 - PWM3 Generator B Control

§_3_dbctl: _3_DBCTL

0x128 - PWM3 Dead-Band Control

§_3_dbrise: _3_DBRISE

0x12c - PWM3 Dead-Band Rising-Edge Delay

§_3_dbfall: _3_DBFALL

0x130 - PWM3 Dead-Band Falling-Edge-Delay

§_3_fltsrc0: _3_FLTSRC0

0x134 - PWM3 Fault Source 0

§_3_fltsrc1: _3_FLTSRC1

0x138 - PWM3 Fault Source 1

§_3_minfltper: _3_MINFLTPER

0x13c - PWM3 Minimum Fault Period

§_0_fltsen: _0_FLTSEN

0x800 - PWM0 Fault Pin Logic Sense

§_0_fltstat0: _0_FLTSTAT0

0x804 - PWM0 Fault Status 0

§_0_fltstat1: _0_FLTSTAT1

0x808 - PWM0 Fault Status 1

§_1_fltsen: _1_FLTSEN

0x880 - PWM1 Fault Pin Logic Sense

§_1_fltstat0: _1_FLTSTAT0

0x884 - PWM1 Fault Status 0

§_1_fltstat1: _1_FLTSTAT1

0x888 - PWM1 Fault Status 1

§_2_fltsen: _2_FLTSEN

0x900 - PWM2 Fault Pin Logic Sense

§_2_fltstat0: _2_FLTSTAT0

0x904 - PWM2 Fault Status 0

§_2_fltstat1: _2_FLTSTAT1

0x908 - PWM2 Fault Status 1

§_3_fltsen: _3_FLTSEN

0x980 - PWM3 Fault Pin Logic Sense

§_3_fltstat0: _3_FLTSTAT0

0x984 - PWM3 Fault Status 0

§_3_fltstat1: _3_FLTSTAT1

0x988 - PWM3 Fault Status 1

§pp: PP

0xfc0 - PWM Peripheral Properties

§cc: CC

0xfc8 - PWM Clock Configuration

Auto Trait Implementations§

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impl UnwindSafe for RegisterBlock

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fn try_into(self) -> Result<U, >::Error>

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Struct tm4c129x::pwm0::RegisterBlock

Fields§

Auto Trait Implementations§

impl !RefUnwindSafe for RegisterBlock

impl Send for RegisterBlock

impl !Sync for RegisterBlock

impl Unpin for RegisterBlock

impl UnwindSafe for RegisterBlock

Blanket Implementations§

impl<T> Any for Twhere T: 'static + ?Sized,

fn type_id(&self) -> TypeId

impl<T> Borrow<T> for Twhere T: ?Sized,

fn borrow(&self) -> &T

impl<T> BorrowMut<T> for Twhere T: ?Sized,

fn borrow_mut(&mut self) -> &mut T

impl<T> From<T> for T

fn from(t: T) -> T

impl<T, U> Into<U> for Twhere U: From<T>,

fn into(self) -> U

impl<T, U> TryFrom<U> for Twhere U: Into<T>,

type Error = Infallible

fn try_from(value: U) -> Result<T, <T as TryFrom<U>>::Error>

impl<T, U> TryInto<U> for Twhere U: TryFrom<T>,

type Error = <U as TryFrom<T>>::Error

fn try_into(self) -> Result<U, <U as TryFrom<T>>::Error>