tm4c129x/adc0/
cc.rs

1#[doc = "Reader of register CC"]
2pub type R = crate::R<u32, super::CC>;
3#[doc = "Writer for register CC"]
4pub type W = crate::W<u32, super::CC>;
5#[doc = "Register CC `reset()`'s with value 0"]
6impl crate::ResetValue for super::CC {
7    type Type = u32;
8    #[inline(always)]
9    fn reset_value() -> Self::Type {
10        0
11    }
12}
13#[doc = "ADC Clock Source\n\nValue on reset: 0"]
14#[derive(Clone, Copy, Debug, PartialEq)]
15#[repr(u8)]
16pub enum CS_A {
17    #[doc = "0: PLL VCO divided by CLKDIV"]
18    SYSPLL = 0,
19    #[doc = "1: PIOSC"]
20    PIOSC = 1,
21    #[doc = "2: MOSC"]
22    MOSC = 2,
23}
24impl From<CS_A> for u8 {
25    #[inline(always)]
26    fn from(variant: CS_A) -> Self {
27        variant as _
28    }
29}
30#[doc = "Reader of field `CS`"]
31pub type CS_R = crate::R<u8, CS_A>;
32impl CS_R {
33    #[doc = r"Get enumerated values variant"]
34    #[inline(always)]
35    pub fn variant(&self) -> crate::Variant<u8, CS_A> {
36        use crate::Variant::*;
37        match self.bits {
38            0 => Val(CS_A::SYSPLL),
39            1 => Val(CS_A::PIOSC),
40            2 => Val(CS_A::MOSC),
41            i => Res(i),
42        }
43    }
44    #[doc = "Checks if the value of the field is `SYSPLL`"]
45    #[inline(always)]
46    pub fn is_syspll(&self) -> bool {
47        *self == CS_A::SYSPLL
48    }
49    #[doc = "Checks if the value of the field is `PIOSC`"]
50    #[inline(always)]
51    pub fn is_piosc(&self) -> bool {
52        *self == CS_A::PIOSC
53    }
54    #[doc = "Checks if the value of the field is `MOSC`"]
55    #[inline(always)]
56    pub fn is_mosc(&self) -> bool {
57        *self == CS_A::MOSC
58    }
59}
60#[doc = "Write proxy for field `CS`"]
61pub struct CS_W<'a> {
62    w: &'a mut W,
63}
64impl<'a> CS_W<'a> {
65    #[doc = r"Writes `variant` to the field"]
66    #[inline(always)]
67    pub fn variant(self, variant: CS_A) -> &'a mut W {
68        unsafe { self.bits(variant.into()) }
69    }
70    #[doc = "PLL VCO divided by CLKDIV"]
71    #[inline(always)]
72    pub fn syspll(self) -> &'a mut W {
73        self.variant(CS_A::SYSPLL)
74    }
75    #[doc = "PIOSC"]
76    #[inline(always)]
77    pub fn piosc(self) -> &'a mut W {
78        self.variant(CS_A::PIOSC)
79    }
80    #[doc = "MOSC"]
81    #[inline(always)]
82    pub fn mosc(self) -> &'a mut W {
83        self.variant(CS_A::MOSC)
84    }
85    #[doc = r"Writes raw bits to the field"]
86    #[inline(always)]
87    pub unsafe fn bits(self, value: u8) -> &'a mut W {
88        self.w.bits = (self.w.bits & !0x0f) | ((value as u32) & 0x0f);
89        self.w
90    }
91}
92#[doc = "Reader of field `CLKDIV`"]
93pub type CLKDIV_R = crate::R<u8, u8>;
94#[doc = "Write proxy for field `CLKDIV`"]
95pub struct CLKDIV_W<'a> {
96    w: &'a mut W,
97}
98impl<'a> CLKDIV_W<'a> {
99    #[doc = r"Writes raw bits to the field"]
100    #[inline(always)]
101    pub fn bits(self, value: u8) -> &'a mut W {
102        self.w.bits = (self.w.bits & !(0x3f << 4)) | (((value as u32) & 0x3f) << 4);
103        self.w
104    }
105}
106impl R {
107    #[doc = "Bits 0:3 - ADC Clock Source"]
108    #[inline(always)]
109    pub fn cs(&self) -> CS_R {
110        CS_R::new((self.bits & 0x0f) as u8)
111    }
112    #[doc = "Bits 4:9 - PLL VCO Clock Divisor"]
113    #[inline(always)]
114    pub fn clkdiv(&self) -> CLKDIV_R {
115        CLKDIV_R::new(((self.bits >> 4) & 0x3f) as u8)
116    }
117}
118impl W {
119    #[doc = "Bits 0:3 - ADC Clock Source"]
120    #[inline(always)]
121    pub fn cs(&mut self) -> CS_W {
122        CS_W { w: self }
123    }
124    #[doc = "Bits 4:9 - PLL VCO Clock Divisor"]
125    #[inline(always)]
126    pub fn clkdiv(&mut self) -> CLKDIV_W {
127        CLKDIV_W { w: self }
128    }
129}
tm4c129x/adc0/cc.rs

tm4c129x/adc0/
cc.rs
