Module tm4c123x::udma
[−]
[src]
Micro Direct Memory Access register addresses
Modules
altbase |
DMA Alternate Channel Control Base Pointer |
altclr |
DMA Channel Primary Alternate Clear |
altset |
DMA Channel Primary Alternate Set |
cfg |
DMA Configuration |
chasgn |
DMA Channel Assignment |
chis |
DMA Channel Interrupt Status |
chmap0 |
DMA Channel Map Select 0 |
chmap1 |
DMA Channel Map Select 1 |
chmap2 |
DMA Channel Map Select 2 |
chmap3 |
DMA Channel Map Select 3 |
ctlbase |
DMA Channel Control Base Pointer |
enaclr |
DMA Channel Enable Clear |
enaset |
DMA Channel Enable Set |
errclr |
DMA Bus Error Clear |
prioclr |
DMA Channel Priority Clear |
prioset |
DMA Channel Priority Set |
reqmaskclr |
DMA Channel Request Mask Clear |
reqmaskset |
DMA Channel Request Mask Set |
stat |
DMA Status |
swreq |
DMA Channel Software Request |
useburstclr |
DMA Channel Useburst Clear |
useburstset |
DMA Channel Useburst Set |
waitstat |
DMA Channel Wait-on-Request Status |
Structs
ALTBASE |
DMA Alternate Channel Control Base Pointer |
ALTCLR |
DMA Channel Primary Alternate Clear |
ALTSET |
DMA Channel Primary Alternate Set |
CFG |
DMA Configuration |
CHASGN |
DMA Channel Assignment |
CHIS |
DMA Channel Interrupt Status |
CHMAP0 |
DMA Channel Map Select 0 |
CHMAP1 |
DMA Channel Map Select 1 |
CHMAP2 |
DMA Channel Map Select 2 |
CHMAP3 |
DMA Channel Map Select 3 |
CTLBASE |
DMA Channel Control Base Pointer |
ENACLR |
DMA Channel Enable Clear |
ENASET |
DMA Channel Enable Set |
ERRCLR |
DMA Bus Error Clear |
PRIOCLR |
DMA Channel Priority Clear |
PRIOSET |
DMA Channel Priority Set |
REQMASKCLR |
DMA Channel Request Mask Clear |
REQMASKSET |
DMA Channel Request Mask Set |
RegisterBlock |
Register block |
STAT |
DMA Status |
SWREQ |
DMA Channel Software Request |
USEBURSTCLR |
DMA Channel Useburst Clear |
USEBURSTSET |
DMA Channel Useburst Set |
WAITSTAT |
DMA Channel Wait-on-Request Status |