1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809 810 811 812 813 814 815 816 817 818 819 820 821 822 823 824 825 826 827 828 829 830 831 832 833 834 835 836 837 838 839 840 841 842 843 844 845 846 847 848 849 850 851 852 853 854 855 856 857 858 859 860 861 862 863 864 865 866 867 868 869 870 871 872 873 874 875 876 877 878 879 880 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895 896 897 898 899 900 901 902 903 904 905 906 907 908 909 910 911 912 913 914 915 916 917 918 919 920 921 922 923 924 925 926 927 928 929 930 931 932 933 934 935 936 937 938 939 940 941 942 943 944 945 946 947 948 949 950 951 952 953 954 955 956 957 958 959 960 961 962 963 964 965 966 967 968 969 970 971 972 973 974 975 976 977 978 979 980 981 982 983 984 985 986 987 988 989 990 991 992 993 994 995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170 1171 1172 1173 1174 1175 1176 1177 1178 1179 1180 1181 1182 1183 1184 1185 1186 1187 1188 1189 1190 1191 1192 1193 1194 1195 1196 1197 1198 1199 1200 1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 1222 1223 1224 1225 1226 1227 1228 1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 1239 1240 1241 1242 1243 1244 1245 1246 1247 1248 1249 1250 1251 1252 1253 1254 1255 1256 1257 1258 1259 1260 1261 1262 1263 1264 1265 1266 1267 1268 1269 1270 1271 1272 1273 1274 1275 1276 1277 1278 1279 1280 1281 1282 1283 1284 1285 1286 1287 1288 1289 1290 1291 1292 1293 1294 1295 1296 1297 1298 1299 1300 1301 1302 1303 1304 1305 1306 1307 1308 1309 1310 1311 1312 1313 1314 1315 1316 1317 1318 1319 1320 1321 1322 1323 1324 1325 1326 1327 1328 1329 1330 1331 1332 1333 1334 1335 1336 1337 1338 1339 1340 1341 1342 1343 1344 1345 1346 1347 1348 1349 1350 1351 1352 1353 1354 1355 1356 1357 1358 1359 1360 1361 1362 1363 1364 1365 1366 1367 1368 1369 1370 1371 1372 1373 1374 1375 1376 1377 1378 1379 1380 1381 1382 1383 1384 1385 1386 1387 1388 1389 1390 1391 1392 1393 1394 1395 1396 1397 1398 1399 1400 1401 1402 1403 1404 1405 1406 1407 1408 1409 1410 1411 1412 1413 1414 1415 1416 1417 1418 1419 1420 1421 1422 1423 1424 1425 1426 1427 1428 1429 1430 1431 1432 1433 1434 1435
use super::{Cpu, StatusRegs::*, IRQ_ADDR, NMI_ADDR, SP_BASE}; use crate::{ common::{Addr, Byte}, memory::{MemRead, MemWrite}, serialization::Savable, NesResult, }; use std::{ fmt, io::{Read, Write}, }; // 16x16 grid of 6502 opcodes. Matches datasheet matrix for easy lookup #[rustfmt::skip] pub const INSTRUCTIONS: [Instr; 256] = [ Instr(0x00, IMM, BRK, 7), Instr(0x01, IDX, ORA, 6), Instr(0x02, IMP, XXX, 2), Instr(0x03, IDX, SLO, 8), Instr(0x04, ZP0, NOP, 3), Instr(0x05, ZP0, ORA, 3), Instr(0x06, ZP0, ASL, 5), Instr(0x07, ZP0, SLO, 5), Instr(0x08, IMP, PHP, 3), Instr(0x09, IMM, ORA, 2), Instr(0x0A, ACC, ASL, 2), Instr(0x0B, IMM, ANC, 2), Instr(0x0C, ABS, NOP, 4), Instr(0x0D, ABS, ORA, 4), Instr(0x0E, ABS, ASL, 6), Instr(0x0F, ABS, SLO, 6), Instr(0x10, REL, BPL, 2), Instr(0x11, IDY, ORA, 5), Instr(0x12, IMP, XXX, 2), Instr(0x13, IDY, SLO, 8), Instr(0x14, ZPX, NOP, 4), Instr(0x15, ZPX, ORA, 4), Instr(0x16, ZPX, ASL, 6), Instr(0x17, ZPX, SLO, 6), Instr(0x18, IMP, CLC, 2), Instr(0x19, ABY, ORA, 4), Instr(0x1A, IMP, NOP, 2), Instr(0x1B, ABY, SLO, 7), Instr(0x1C, ABX, IGN, 4), Instr(0x1D, ABX, ORA, 4), Instr(0x1E, ABX, ASL, 7), Instr(0x1F, ABX, SLO, 7), Instr(0x20, ABS, JSR, 6), Instr(0x21, IDX, AND, 6), Instr(0x22, IMP, XXX, 2), Instr(0x23, IDX, RLA, 8), Instr(0x24, ZP0, BIT, 3), Instr(0x25, ZP0, AND, 3), Instr(0x26, ZP0, ROL, 5), Instr(0x27, ZP0, RLA, 5), Instr(0x28, IMP, PLP, 4), Instr(0x29, IMM, AND, 2), Instr(0x2A, ACC, ROL, 2), Instr(0x2B, IMM, ANC, 2), Instr(0x2C, ABS, BIT, 4), Instr(0x2D, ABS, AND, 4), Instr(0x2E, ABS, ROL, 6), Instr(0x2F, ABS, RLA, 6), Instr(0x30, REL, BMI, 2), Instr(0x31, IDY, AND, 5), Instr(0x32, IMP, XXX, 2), Instr(0x33, IDY, RLA, 8), Instr(0x34, ZPX, NOP, 4), Instr(0x35, ZPX, AND, 4), Instr(0x36, ZPX, ROL, 6), Instr(0x37, ZPX, RLA, 6), Instr(0x38, IMP, SEC, 2), Instr(0x39, ABY, AND, 4), Instr(0x3A, IMP, NOP, 2), Instr(0x3B, ABY, RLA, 7), Instr(0x3C, ABX, IGN, 4), Instr(0x3D, ABX, AND, 4), Instr(0x3E, ABX, ROL, 7), Instr(0x3F, ABX, RLA, 7), Instr(0x40, IMP, RTI, 6), Instr(0x41, IDX, EOR, 6), Instr(0x42, IMP, XXX, 2), Instr(0x43, IDX, SRE, 8), Instr(0x44, ZP0, NOP, 3), Instr(0x45, ZP0, EOR, 3), Instr(0x46, ZP0, LSR, 5), Instr(0x47, ZP0, SRE, 5), Instr(0x48, IMP, PHA, 3), Instr(0x49, IMM, EOR, 2), Instr(0x4A, ACC, LSR, 2), Instr(0x4B, IMM, ALR, 2), Instr(0x4C, ABS, JMP, 3), Instr(0x4D, ABS, EOR, 4), Instr(0x4E, ABS, LSR, 6), Instr(0x4F, ABS, SRE, 6), Instr(0x50, REL, BVC, 2), Instr(0x51, IDY, EOR, 5), Instr(0x52, IMP, XXX, 2), Instr(0x53, IDY, SRE, 8), Instr(0x54, ZPX, NOP, 4), Instr(0x55, ZPX, EOR, 4), Instr(0x56, ZPX, LSR, 6), Instr(0x57, ZPX, SRE, 6), Instr(0x58, IMP, CLI, 2), Instr(0x59, ABY, EOR, 4), Instr(0x5A, IMP, NOP, 2), Instr(0x5B, ABY, SRE, 7), Instr(0x5C, ABX, IGN, 4), Instr(0x5D, ABX, EOR, 4), Instr(0x5E, ABX, LSR, 7), Instr(0x5F, ABX, SRE, 7), Instr(0x60, IMP, RTS, 6), Instr(0x61, IDX, ADC, 6), Instr(0x62, IMP, XXX, 2), Instr(0x63, IDX, RRA, 8), Instr(0x64, ZP0, NOP, 3), Instr(0x65, ZP0, ADC, 3), Instr(0x66, ZP0, ROR, 5), Instr(0x67, ZP0, RRA, 5), Instr(0x68, IMP, PLA, 4), Instr(0x69, IMM, ADC, 2), Instr(0x6A, ACC, ROR, 2), Instr(0x6B, IMM, ARR, 2), Instr(0x6C, IND, JMP, 5), Instr(0x6D, ABS, ADC, 4), Instr(0x6E, ABS, ROR, 6), Instr(0x6F, ABS, RRA, 6), Instr(0x70, REL, BVS, 2), Instr(0x71, IDY, ADC, 5), Instr(0x72, IMP, XXX, 2), Instr(0x73, IDY, RRA, 8), Instr(0x74, ZPX, NOP, 4), Instr(0x75, ZPX, ADC, 4), Instr(0x76, ZPX, ROR, 6), Instr(0x77, ZPX, RRA, 6), Instr(0x78, IMP, SEI, 2), Instr(0x79, ABY, ADC, 4), Instr(0x7A, IMP, NOP, 2), Instr(0x7B, ABY, RRA, 7), Instr(0x7C, ABX, IGN, 4), Instr(0x7D, ABX, ADC, 4), Instr(0x7E, ABX, ROR, 7), Instr(0x7F, ABX, RRA, 7), Instr(0x80, IMM, SKB, 2), Instr(0x81, IDX, STA, 6), Instr(0x82, IMM, SKB, 2), Instr(0x83, IDX, SAX, 6), Instr(0x84, ZP0, STY, 3), Instr(0x85, ZP0, STA, 3), Instr(0x86, ZP0, STX, 3), Instr(0x87, ZP0, SAX, 3), Instr(0x88, IMP, DEY, 2), Instr(0x89, IMM, SKB, 2), Instr(0x8A, IMP, TXA, 2), Instr(0x8B, IMM, XAA, 2), Instr(0x8C, ABS, STY, 4), Instr(0x8D, ABS, STA, 4), Instr(0x8E, ABS, STX, 4), Instr(0x8F, ABS, SAX, 4), Instr(0x90, REL, BCC, 2), Instr(0x91, IDY, STA, 6), Instr(0x92, IMP, XXX, 2), Instr(0x93, IDY, AHX, 6), Instr(0x94, ZPX, STY, 4), Instr(0x95, ZPX, STA, 4), Instr(0x96, ZPY, STX, 4), Instr(0x97, ZPY, SAX, 4), Instr(0x98, IMP, TYA, 2), Instr(0x99, ABY, STA, 5), Instr(0x9A, IMP, TXS, 2), Instr(0x9B, ABY, TAS, 5), Instr(0x9C, ABX, SYA, 5), Instr(0x9D, ABX, STA, 5), Instr(0x9E, ABY, SXA, 5), Instr(0x9F, ABY, AHX, 5), Instr(0xA0, IMM, LDY, 2), Instr(0xA1, IDX, LDA, 6), Instr(0xA2, IMM, LDX, 2), Instr(0xA3, IDX, LAX, 6), Instr(0xA4, ZP0, LDY, 3), Instr(0xA5, ZP0, LDA, 3), Instr(0xA6, ZP0, LDX, 3), Instr(0xA7, ZP0, LAX, 3), Instr(0xA8, IMP, TAY, 2), Instr(0xA9, IMM, LDA, 2), Instr(0xAA, IMP, TAX, 2), Instr(0xAB, IMM, LAX, 2), Instr(0xAC, ABS, LDY, 4), Instr(0xAD, ABS, LDA, 4), Instr(0xAE, ABS, LDX, 4), Instr(0xAF, ABS, LAX, 4), Instr(0xB0, REL, BCS, 2), Instr(0xB1, IDY, LDA, 5), Instr(0xB2, IMP, XXX, 2), Instr(0xB3, IDY, LAX, 5), Instr(0xB4, ZPX, LDY, 4), Instr(0xB5, ZPX, LDA, 4), Instr(0xB6, ZPY, LDX, 4), Instr(0xB7, ZPY, LAX, 4), Instr(0xB8, IMP, CLV, 2), Instr(0xB9, ABY, LDA, 4), Instr(0xBA, IMP, TSX, 2), Instr(0xBB, ABY, LAS, 4), Instr(0xBC, ABX, LDY, 4), Instr(0xBD, ABX, LDA, 4), Instr(0xBE, ABY, LDX, 4), Instr(0xBF, ABY, LAX, 4), Instr(0xC0, IMM, CPY, 2), Instr(0xC1, IDX, CMP, 6), Instr(0xC2, IMM, SKB, 2), Instr(0xC3, IDX, DCP, 8), Instr(0xC4, ZP0, CPY, 3), Instr(0xC5, ZP0, CMP, 3), Instr(0xC6, ZP0, DEC, 5), Instr(0xC7, ZP0, DCP, 5), Instr(0xC8, IMP, INY, 2), Instr(0xC9, IMM, CMP, 2), Instr(0xCA, IMP, DEX, 2), Instr(0xCB, IMM, AXS, 2), Instr(0xCC, ABS, CPY, 4), Instr(0xCD, ABS, CMP, 4), Instr(0xCE, ABS, DEC, 6), Instr(0xCF, ABS, DCP, 6), Instr(0xD0, REL, BNE, 2), Instr(0xD1, IDY, CMP, 5), Instr(0xD2, IMP, XXX, 2), Instr(0xD3, IDY, DCP, 8), Instr(0xD4, ZPX, NOP, 4), Instr(0xD5, ZPX, CMP, 4), Instr(0xD6, ZPX, DEC, 6), Instr(0xD7, ZPX, DCP, 6), Instr(0xD8, IMP, CLD, 2), Instr(0xD9, ABY, CMP, 4), Instr(0xDA, IMP, NOP, 2), Instr(0xDB, ABY, DCP, 7), Instr(0xDC, ABX, IGN, 4), Instr(0xDD, ABX, CMP, 4), Instr(0xDE, ABX, DEC, 7), Instr(0xDF, ABX, DCP, 7), Instr(0xE0, IMM, CPX, 2), Instr(0xE1, IDX, SBC, 6), Instr(0xE2, IMM, SKB, 2), Instr(0xE3, IDX, ISB, 8), Instr(0xE4, ZP0, CPX, 3), Instr(0xE5, ZP0, SBC, 3), Instr(0xE6, ZP0, INC, 5), Instr(0xE7, ZP0, ISB, 5), Instr(0xE8, IMP, INX, 2), Instr(0xE9, IMM, SBC, 2), Instr(0xEA, IMP, NOP, 2), Instr(0xEB, IMM, SBC, 2), Instr(0xEC, ABS, CPX, 4), Instr(0xED, ABS, SBC, 4), Instr(0xEE, ABS, INC, 6), Instr(0xEF, ABS, ISB, 6), Instr(0xF0, REL, BEQ, 2), Instr(0xF1, IDY, SBC, 5), Instr(0xF2, IMP, XXX, 2), Instr(0xF3, IDY, ISB, 8), Instr(0xF4, ZPX, NOP, 4), Instr(0xF5, ZPX, SBC, 4), Instr(0xF6, ZPX, INC, 6), Instr(0xF7, ZPX, ISB, 6), Instr(0xF8, IMP, SED, 2), Instr(0xF9, ABY, SBC, 4), Instr(0xFA, IMP, NOP, 2), Instr(0xFB, ABY, ISB, 7), Instr(0xFC, ABX, IGN, 4), Instr(0xFD, ABX, SBC, 4), Instr(0xFE, ABX, INC, 7), Instr(0xFF, ABX, ISB, 7), ]; #[rustfmt::skip] #[derive(Copy, Clone, Debug, PartialEq, Eq)] // List of all CPU official and unofficial operations // http://wiki.nesdev.com/w/index.php/6502_instructions // http://archive.6502.org/datasheets/rockwell_r650x_r651x.pdf pub enum Operation { ADC, AND, ASL, BCC, BCS, BEQ, BIT, BMI, BNE, BPL, BRK, BVC, BVS, CLC, CLD, CLI, CLV, CMP, CPX, CPY, DEC, DEX, DEY, EOR, INC, INX, INY, JMP, JSR, LDA, LDX, LDY, LSR, NOP, ORA, PHA, PHP, PLA, PLP, ROL, ROR, RTI, RTS, SBC, SEC, SED, SEI, STA, STX, STY, TAX, TAY, TSX, TXA, TXS, TYA, // "Unofficial" opcodes SKB, IGN, ISB, DCP, AXS, LAS, LAX, AHX, SAX, XAA, SXA, RRA, TAS, SYA, ARR, SRE, ALR, RLA, ANC, SLO, XXX } #[derive(Copy, Clone, Debug, PartialEq, Eq)] #[rustfmt::skip] pub enum AddrMode { IMM, ZP0, ZPX, ZPY, ABS, ABX, ABY, IND, IDX, IDY, REL, ACC, IMP, } use AddrMode::*; use Operation::*; // (opcode, Addressing Mode, Operation, cycles taken) #[derive(Copy, Clone, PartialEq, Eq)] pub struct Instr(Byte, AddrMode, Operation, usize); impl Instr { pub fn opcode(&self) -> Byte { self.0 } pub fn addr_mode(&self) -> AddrMode { self.1 } pub fn op(&self) -> Operation { self.2 } pub fn cycles(&self) -> usize { self.3 } } /// CPU Addressing Modes /// /// The 6502 can address 64KB from 0x0000 - 0xFFFF. The high byte is usually the page and the /// low byte the offset into the page. There are 256 total pages of 256 bytes. impl Cpu { /// Accumulator /// No additional data is required, but the default target will be the accumulator. // ASL, ROL, LSR, ROR // # address R/W description // --- ------- --- ----------------------------------------------- // 1 PC R fetch opcode, increment PC // 2 PC R read next instruction byte (and throw it away) pub(super) fn acc(&mut self) { let _ = self.read(self.pc); // Cycle 2, Read and throw away } /// Implied /// No additional data is required, but the default target will be the accumulator. // # address R/W description // --- ------- --- ----------------------------------------------- // 1 PC R fetch opcode, increment PC // 2 PC R read next instruction byte (and throw it away) pub(super) fn imp(&mut self) { let _ = self.read(self.pc); // Cycle 2, Read and throw away } /// Immediate /// Uses the next byte as the value, so we'll update the abs_addr to the next byte. // # address R/W description // --- ------- --- ------------------------------------------ // 1 PC R fetch opcode, increment PC // 2 PC R fetch value, increment PC pub(super) fn imm(&mut self) { self.abs_addr = self.pc; self.pc = self.pc.wrapping_add(1); } /// Zero Page /// Accesses the first 0xFF bytes of the address range, so this only requires one extra byte /// instead of the usual two. // Read instructions (LDA, LDX, LDY, EOR, AND, ORA, ADC, SBC, CMP, BIT, // LAX, NOP) // # address R/W description // --- ------- --- ------------------------------------------ // 1 PC R fetch opcode, increment PC // 2 PC R fetch address, increment PC // 3 address R read from effective address // Read-Modify-Write instructions (ASL, LSR, ROL, ROR, INC, DEC, // SLO, SRE, RLA, RRA, ISB, DCP) // # address R/W description // --- ------- --- ------------------------------------------ // 1 PC R fetch opcode, increment PC // 2 PC R fetch address, increment PC // 3 address R read from effective address // 4 address W write the value back to effective address, // and do the operation on it // 5 address W write the new value to effective address // Write instructions (STA, STX, STY, SAX) // # address R/W description // --- ------- --- ------------------------------------------ // 1 PC R fetch opcode, increment PC // 2 PC R fetch address, increment PC // 3 address W write register to effective address pub(super) fn zp0(&mut self) { self.abs_addr = Addr::from(self.read(self.pc)) & 0x00FF; // Cycle 2 self.pc = self.pc.wrapping_add(1); } /// Zero Page w/ X offset /// Same as Zero Page, but is offset by adding the x register. // Read instructions (LDA, LDX, LDY, EOR, AND, ORA, ADC, SBC, CMP, BIT, // LAX, NOP) // # address R/W description // --- --------- --- ------------------------------------------ // 1 PC R fetch opcode, increment PC // 2 PC R fetch address, increment PC // 3 address R read from address, add index register to it // 4 address+X* R read from effective address // * The high byte of the effective address is always zero, // i.e. page boundary crossings are not handled. // Read-Modify-Write instructions (ASL, LSR, ROL, ROR, INC, DEC, // SLO, SRE, RLA, RRA, ISB, DCP) // # address R/W description // --- --------- --- --------------------------------------------- // 1 PC R fetch opcode, increment PC // 2 PC R fetch address, increment PC // 3 address R read from address, add index register X to it // 4 address+X* R read from effective address // 5 address+X* W write the value back to effective address, // and do the operation on it // 6 address+X* W write the new value to effective address // Note: * The high byte of the effective address is always zero, // i.e. page boundary crossings are not handled. // Write instructions (STA, STX, STY, SAX) // # address R/W description // --- --------- --- ------------------------------------------- // 1 PC R fetch opcode, increment PC // 2 PC R fetch address, increment PC // 3 address R read from address, add index register to it // 4 address+X* W write to effective address // * The high byte of the effective address is always zero, // i.e. page boundary crossings are not handled. pub(super) fn zpx(&mut self) { let addr = self.read(self.pc); // Cycle 2 self.abs_addr = Addr::from(addr.wrapping_add(self.x)) & 0x00FF; let _ = self.read(Addr::from(addr)); // Cycle 3 self.pc = self.pc.wrapping_add(1); } /// Zero Page w/ Y offset /// Same as Zero Page, but is offset by adding the y register. // Read instructions (LDX, LAX) // # address R/W description // --- --------- --- ------------------------------------------ // 1 PC R fetch opcode, increment PC // 2 PC R fetch address, increment PC // 3 address R read from address, add index register to it // 4 address+Y* R read from effective address // * The high byte of the effective address is always zero, // i.e. page boundary crossings are not handled. // Write instructions (STX, SAX) // # address R/W description // --- --------- --- ------------------------------------------- // 1 PC R fetch opcode, increment PC // 2 PC R fetch address, increment PC // 3 address R read from address, add index register to it // 4 address+Y* W write to effective address // * The high byte of the effective address is always zero, // i.e. page boundary crossings are not handled. pub(super) fn zpy(&mut self) { let addr = self.read(self.pc); // Cycle 2 self.abs_addr = Addr::from(addr.wrapping_add(self.y)) & 0x00FF; let _ = self.read(Addr::from(addr)); // Cycle 3 self.pc = self.pc.wrapping_add(1); } /// Relative /// This mode is only used by branching instructions. The address must be between -128 and +127, /// allowing the branching instruction to move backward or forward relative to the current /// program counter. // # address R/W description // --- --------- --- --------------------------------------------- // 1 PC R fetch opcode, increment PC // 2 PC R fetch operand, increment PC // 3 PC R Fetch opcode of next instruction, // If branch is taken, add operand to PCL. // Otherwise increment PC. // 4+ PC* R Fetch opcode of next instruction. // Fix PCH. If it did not change, increment PC. // 5! PC R Fetch opcode of next instruction, // increment PC. // Notes: The opcode fetch of the next instruction is included to // this diagram for illustration purposes. When determining // real execution times, remember to subtract the last // cycle. // * The high byte of Program Counter (PCH) may be invalid // at this time, i.e. it may be smaller or bigger by $100. // + If branch is taken, this cycle will be executed. // ! If branch occurs to different page, this cycle will be // executed. pub(super) fn rel(&mut self) { self.rel_addr = self.read(self.pc).into(); // Cycle 2 self.pc = self.pc.wrapping_add(1); } /// Absolute /// Uses a full 16-bit address as the next value. // Read instructions (LDA, LDX, LDY, EOR, AND, ORA, ADC, SBC, CMP, BIT, // LAX, NOP) // // # address R/W description // --- ------- --- ------------------------------------------ // 1 PC R fetch opcode, increment PC // 2 PC R fetch low byte of address, increment PC // 3 PC R fetch high byte of address, increment PC // 4 address R read from effective address // Read-Modify-Write instructions (ASL, LSR, ROL, ROR, INC, DEC, // SLO, SRE, RLA, RRA, ISB, DCP) // // # address R/W description // --- ------- --- ------------------------------------------ // 1 PC R fetch opcode, increment PC // 2 PC R fetch low byte of address, increment PC // 3 PC R fetch high byte of address, increment PC // 4 address R read from effective address // 5 address W write the value back to effective address, // and do the operation on it // 6 address W write the new value to effective address // Write instructions (STA, STX, STY, SAX) // // # address R/W description // --- ------- --- ------------------------------------------ // 1 PC R fetch opcode, increment PC // 2 PC R fetch low byte of address, increment PC // 3 PC R fetch high byte of address, increment PC // 4 address W write register to effective address pub(super) fn abs(&mut self) { self.abs_addr = self.readw(self.pc); // Cycle 2 & 3 self.pc = self.pc.wrapping_add(2); } /// Absolute w/ X offset /// Same as Absolute, but is offset by adding the x register. If a page boundary is crossed, an /// additional clock is required. // Read instructions (LDA, LDX, LDY, EOR, AND, ORA, ADC, SBC, CMP, BIT, // LAX, LAE, SHS, NOP) // # address R/W description // --- --------- --- ------------------------------------------ // 1 PC R fetch opcode, increment PC // 2 PC R fetch low byte of address, increment PC // 3 PC R fetch high byte of address, // add index register to low address byte, // increment PC // 4 address+X* R read from effective address, // fix the high byte of effective address // 5+ address+X R re-read from effective address // * The high byte of the effective address may be invalid // at this time, i.e. it may be smaller by $100. // + This cycle will be executed only if the effective address // was invalid during cycle #4, i.e. page boundary was crossed. // Read-Modify-Write instructions (ASL, LSR, ROL, ROR, INC, DEC, // SLO, SRE, RLA, RRA, ISB, DCP) // # address R/W description // --- --------- --- ------------------------------------------ // 1 PC R fetch opcode, increment PC // 2 PC R fetch low byte of address, increment PC // 3 PC R fetch high byte of address, // add index register X to low address byte, // increment PC // 4 address+X* R read from effective address, // fix the high byte of effective address // 5 address+X R re-read from effective address // 6 address+X W write the value back to effective address, // and do the operation on it // 7 address+X W write the new value to effective address // Notes: * The high byte of the effective address may be invalid // at this time, i.e. it may be smaller by $100. // Write instructions (STA, STX, STY, SHA, SHX, SHY) // # address R/W description // --- --------- --- ------------------------------------------ // 1 PC R fetch opcode, increment PC // 2 PC R fetch low byte of address, increment PC // 3 PC R fetch high byte of address, // add index register to low address byte, // increment PC // 4 address+X* R read from effective address, // fix the high byte of effective address // 5 address+X W write to effective address // * The high byte of the effective address may be invalid // at this time, i.e. it may be smaller by $100. Because // the processor cannot undo a write to an invalid // address, it always reads from the address first. pub(super) fn abx(&mut self) { let addr = self.readw(self.pc); // Cycle 2 & 3 self.pc = self.pc.wrapping_add(2); self.abs_addr = addr.wrapping_add(self.x.into()); // Cycle 4 Read with fixed high byte self.fetched_data = self.read((addr & 0xFF00) | (self.abs_addr & 0x00FF)); } /// Absolute w/ Y offset /// Same as Absolute, but is offset by adding the y register. If a page boundary is crossed, an /// additional clock is required. // Read instructions (LDA, LDX, LDY, EOR, AND, ORA, ADC, SBC, CMP, BIT, // LAX, LAE, SHS, NOP) // # address R/W description // --- --------- --- ------------------------------------------ // 1 PC R fetch opcode, increment PC // 2 PC R fetch low byte of address, increment PC // 3 PC R fetch high byte of address, // add index register to low address byte, // increment PC // 4 address+Y* R read from effective address, // fix the high byte of effective address // 5+ address+Y R re-read from effective address // * The high byte of the effective address may be invalid // at this time, i.e. it may be smaller by $100. // + This cycle will be executed only if the effective address // was invalid during cycle #4, i.e. page boundary was crossed. // Read-Modify-Write instructions (ASL, LSR, ROL, ROR, INC, DEC, // SLO, SRE, RLA, RRA, ISB, DCP) // # address R/W description // --- --------- --- ------------------------------------------ // 1 PC R fetch opcode, increment PC // 2 PC R fetch low byte of address, increment PC // 3 PC R fetch high byte of address, // add index register Y to low address byte, // increment PC // 4 address+Y* R read from effective address, // fix the high byte of effective address // 5 address+Y R re-read from effective address // 6 address+Y W write the value back to effective address, // and do the operation on it // 7 address+Y W write the new value to effective address // Notes: * The high byte of the effective address may be invalid // at this time, i.e. it may be smaller by $100. // Write instructions (STA, STX, STY, SHA, SHX, SHY) // # address R/W description // --- --------- --- ------------------------------------------ // 1 PC R fetch opcode, increment PC // 2 PC R fetch low byte of address, increment PC // 3 PC R fetch high byte of address, // add index register to low address byte, // increment PC // 4 address+Y* R read from effective address, // fix the high byte of effective address // 5 address+Y W write to effective address // * The high byte of the effective address may be invalid // at this time, i.e. it may be smaller by $100. Because // the processor cannot undo a write to an invalid // address, it always reads from the address first. pub(super) fn aby(&mut self) { let addr = self.readw(self.pc); // Cycles 2 & 3 self.pc = self.pc.wrapping_add(2); self.abs_addr = addr.wrapping_add(self.y.into()); // Cycle 4 Read with fixed high byte self.fetched_data = self.read((addr & 0xFF00) | (self.abs_addr & 0x00FF)); } /// Indirect (JMP) /// The next 16-bit address is used to get the actual 16-bit address. This instruction has /// a bug in the original hardware. If the lo byte is 0xFF, the hi byte would cross a page /// boundary. However, this doesn't work correctly on the original hardware and instead /// wraps back around to 0. // # address R/W description // --- --------- --- ------------------------------------------ // 1 PC R fetch opcode, increment PC // 2 PC R fetch pointer address low, increment PC // 3 PC R fetch pointer address high, increment PC // 4 pointer R fetch low address to latch // 5 pointer+1* R fetch PCH, copy latch to PCL // Note: * The PCH will always be fetched from the same page // than PCL, i.e. page boundary crossing is not handled. // How Real Programmers Acknowledge Interrupts pub(super) fn ind(&mut self) { let addr = self.readw(self.pc); self.pc = self.pc.wrapping_add(2); if addr & 0x00FF == 0x00FF { // Simulate bug self.abs_addr = (Addr::from(self.read(addr & 0xFF00)) << 8) | Addr::from(self.read(addr)); } else { // Normal behavior self.abs_addr = (Addr::from(self.read(addr + 1)) << 8) | Addr::from(self.read(addr)); } } /// Indirect X /// The next 8-bit address is offset by the X register to get the actual 16-bit address from /// page 0x00. // Read instructions (LDA, ORA, EOR, AND, ADC, CMP, SBC, LAX) // # address R/W description // --- ----------- --- ------------------------------------------ // 1 PC R fetch opcode, increment PC // 2 PC R fetch pointer address, increment PC // 3 pointer R read from the address, add X to it // 4 pointer+X R fetch effective address low // 5 pointer+X+1 R fetch effective address high // 6 address R read from effective address // Note: The effective address is always fetched from zero page, // i.e. the zero page boundary crossing is not handled. // Read-Modify-Write instructions (SLO, SRE, RLA, RRA, ISB, DCP) // # address R/W description // --- ----------- --- ------------------------------------------ // 1 PC R fetch opcode, increment PC // 2 PC R fetch pointer address, increment PC // 3 pointer R read from the address, add X to it // 4 pointer+X R fetch effective address low // 5 pointer+X+1 R fetch effective address high // 6 address R read from effective address // 7 address W write the value back to effective address, // and do the operation on it // 8 address W write the new value to effective address // Note: The effective address is always fetched from zero page, // i.e. the zero page boundary crossing is not handled. // Write instructions (STA, SAX) // # address R/W description // --- ----------- --- ------------------------------------------ // 1 PC R fetch opcode, increment PC // 2 PC R fetch pointer address, increment PC // 3 pointer R read from the address, add X to it // 4 pointer+X R fetch effective address low // 5 pointer+X+1 R fetch effective address high // 6 address W write to effective address // Note: The effective address is always fetched from zero page, // i.e. the zero page boundary crossing is not handled. pub(super) fn idx(&mut self) { let addr = self.read(self.pc); // Cycle 2 self.pc = self.pc.wrapping_add(1); let x_offset = addr.wrapping_add(self.x); let _ = self.read(Addr::from(addr)); // Cycle 3 self.abs_addr = self.readw_zp(x_offset); // Cycles 4 & 5 } /// Indirect Y /// The next 8-bit address is read to get a 16-bit address from page 0x00, which is then offset /// by the Y register. If a page boundary is crossed, add a clock cycle. // Read instructions (LDA, EOR, AND, ORA, ADC, SBC, CMP) // # address R/W description // --- ----------- --- ------------------------------------------ // 1 PC R fetch opcode, increment PC // 2 PC R fetch pointer address, increment PC // 3 pointer R fetch effective address low // 4 pointer+1 R fetch effective address high, // add Y to low byte of effective address // 5 address+Y* R read from effective address, // fix high byte of effective address // 6+ address+Y R read from effective address // Notes: The effective address is always fetched from zero page, // i.e. the zero page boundary crossing is not handled. // * The high byte of the effective address may be invalid // at this time, i.e. it may be smaller by $100. // + This cycle will be executed only if the effective address // was invalid during cycle #5, i.e. page boundary was crossed. // Read-Modify-Write instructions (SLO, SRE, RLA, RRA, ISB, DCP) // # address R/W description // --- ----------- --- ------------------------------------------ // 1 PC R fetch opcode, increment PC // 2 PC R fetch pointer address, increment PC // 3 pointer R fetch effective address low // 4 pointer+1 R fetch effective address high, // add Y to low byte of effective address // 5 address+Y* R read from effective address, // fix high byte of effective address // 6 address+Y R re-read from effective address // 7 address+Y W write the value back to effective address, // and do the operation on it // 8 address+Y W write the new value to effective address // Notes: The effective address is always fetched from zero page, // i.e. the zero page boundary crossing is not handled. // * The high byte of the effective address may be invalid // at this time, i.e. it may be smaller by $100. // Write instructions (STA, SHA) // # address R/W description // --- ----------- --- ------------------------------------------ // 1 PC R fetch opcode, increment PC // 2 PC R fetch pointer address, increment PC // 3 pointer R fetch effective address low // 4 pointer+1 R fetch effective address high, // add Y to low byte of effective address // 5 address+Y* R read from effective address, // fix high byte of effective address // 6 address+Y W write to effective address // Notes: The effective address is always fetched from zero page, // i.e. the zero page boundary crossing is not handled. // * The high byte of the effective address may be invalid // at this time, i.e. it may be smaller by $100. pub(super) fn idy(&mut self) { let addr = self.read(self.pc); // Cycle 2 self.pc = self.pc.wrapping_add(1); let addr = self.readw_zp(addr); // Cycles 3 & 4 self.abs_addr = addr.wrapping_add(self.y.into()); // Cycle 4 Read with fixed high byte self.fetched_data = self.read((addr & 0xFF00) | (self.abs_addr & 0x00FF)); } } /// CPU instructions impl Cpu { /// Storage opcodes /// LDA: Load A with M pub(super) fn lda(&mut self) { self.fetch_data(); self.acc = self.fetched_data; self.set_flags_zn(self.acc); } /// LDX: Load X with M pub(super) fn ldx(&mut self) { self.fetch_data(); self.x = self.fetched_data; self.set_flags_zn(self.x); } /// LDY: Load Y with M pub(super) fn ldy(&mut self) { self.fetch_data(); self.y = self.fetched_data; self.set_flags_zn(self.y); } /// STA: Store A into M pub(super) fn sta(&mut self) { self.write(self.abs_addr, self.acc); } /// STX: Store X into M pub(super) fn stx(&mut self) { self.write(self.abs_addr, self.x); } /// STY: Store Y into M pub(super) fn sty(&mut self) { self.write(self.abs_addr, self.y); } /// TAX: Transfer A to X pub(super) fn tax(&mut self) { self.x = self.acc; self.set_flags_zn(self.x); } /// TAY: Transfer A to Y pub(super) fn tay(&mut self) { self.y = self.acc; self.set_flags_zn(self.y); } /// TSX: Transfer Stack Pointer to X pub(super) fn tsx(&mut self) { self.x = self.sp; self.set_flags_zn(self.x); } /// TXA: Transfer X to A pub(super) fn txa(&mut self) { self.acc = self.x; self.set_flags_zn(self.acc); } /// TXS: Transfer X to Stack Pointer pub(super) fn txs(&mut self) { self.sp = self.x; } /// TYA: Transfer Y to A pub(super) fn tya(&mut self) { self.acc = self.y; self.set_flags_zn(self.acc); } /// Arithmetic opcodes /// ADC: Add M to A with Carry pub(super) fn adc(&mut self) { self.fetch_data(); let a = self.acc; let (x1, o1) = self.fetched_data.overflowing_add(a); let (x2, o2) = x1.overflowing_add(self.get_flag(C)); self.acc = x2; self.set_flag(C, o1 | o2); self.set_flag( V, (a ^ self.fetched_data) & 0x80 == 0 && (a ^ self.acc) & 0x80 != 0, ); self.set_flags_zn(self.acc); } /// SBC: Subtract M from A with Carry pub(super) fn sbc(&mut self) { self.fetch_data(); let a = self.acc; let (x1, o1) = a.overflowing_sub(self.fetched_data); let (x2, o2) = x1.overflowing_sub(1 - self.get_flag(C)); self.acc = x2; self.set_flag(C, !(o1 | o2)); self.set_flag( V, (a ^ self.fetched_data) & 0x80 != 0 && (a ^ self.acc) & 0x80 != 0, ); self.set_flags_zn(self.acc); } /// DEC: Decrement M by One pub(super) fn dec(&mut self) { self.fetch_data(); self.write_fetched(self.fetched_data); // dummy write let val = self.fetched_data.wrapping_sub(1); self.write_fetched(val); self.set_flags_zn(val); } /// DEX: Decrement X by One pub(super) fn dex(&mut self) { self.x = self.x.wrapping_sub(1); self.set_flags_zn(self.x); } /// DEY: Decrement Y by One pub(super) fn dey(&mut self) { self.y = self.y.wrapping_sub(1); self.set_flags_zn(self.y); } /// INC: Increment M by One pub(super) fn inc(&mut self) { self.fetch_data(); self.write_fetched(self.fetched_data); // dummy write let val = self.fetched_data.wrapping_add(1); self.set_flags_zn(val); self.write_fetched(val); } /// INX: Increment X by One pub(super) fn inx(&mut self) { self.x = self.x.wrapping_add(1); self.set_flags_zn(self.x); } /// INY: Increment Y by One pub(super) fn iny(&mut self) { self.y = self.y.wrapping_add(1); self.set_flags_zn(self.y); } /// Bitwise opcodes /// AND: "And" M with A pub(super) fn and(&mut self) { self.fetch_data(); self.acc &= self.fetched_data; self.set_flags_zn(self.acc); } /// ASL: Shift Left One Bit (M or A) pub(super) fn asl(&mut self) { self.fetch_data(); // Cycle 4 & 5 self.write_fetched(self.fetched_data); // Cycle 6 self.set_flag(C, (self.fetched_data >> 7) & 1 > 0); let val = self.fetched_data.wrapping_shl(1); self.set_flags_zn(val); self.write_fetched(val); // Cycle 7 } /// BIT: Test Bits in M with A (Affects N, V, and Z) pub(super) fn bit(&mut self) { self.fetch_data(); let val = self.acc & self.fetched_data; self.set_flag(Z, val == 0); self.set_flag(N, self.fetched_data & (1 << 7) > 0); self.set_flag(V, self.fetched_data & (1 << 6) > 0); } /// EOR: "Exclusive-Or" M with A pub(super) fn eor(&mut self) { self.fetch_data(); self.acc ^= self.fetched_data; self.set_flags_zn(self.acc); } /// LSR: Shift Right One Bit (M or A) pub(super) fn lsr(&mut self) { self.fetch_data(); // Cycle 4 & 5 self.write_fetched(self.fetched_data); // Cycle 6 self.set_flag(C, self.fetched_data & 1 > 0); let val = self.fetched_data.wrapping_shr(1); self.set_flags_zn(val); self.write_fetched(val); // Cycle 7 } /// ORA: "OR" M with A pub(super) fn ora(&mut self) { self.fetch_data(); self.acc |= self.fetched_data; self.set_flags_zn(self.acc); } /// ROL: Rotate One Bit Left (M or A) pub(super) fn rol(&mut self) { self.fetch_data(); self.write_fetched(self.fetched_data); // dummy write let old_c = self.get_flag(C); self.set_flag(C, (self.fetched_data >> 7) & 1 > 0); let val = (self.fetched_data << 1) | old_c; self.set_flags_zn(val); self.write_fetched(val); } /// ROR: Rotate One Bit Right (M or A) pub(super) fn ror(&mut self) { self.fetch_data(); self.write_fetched(self.fetched_data); // dummy write let mut ret = self.fetched_data.rotate_right(1); if self.get_flag(C) == 1 { ret |= 1 << 7; } else { ret &= !(1 << 7); } self.set_flag(C, self.fetched_data & 1 > 0); self.set_flags_zn(ret); self.write_fetched(ret); } /// Branch opcodes /// Utility function used by all branch instructions pub(super) fn branch(&mut self) { // If an interrupt occurs during the final cycle of a non-pagecrossing branch // then it will be ignored until the next instruction completes let skip_nmi = self.nmi_pending && !self.last_nmi; let skip_irq = self.irq_pending > 0 && !self.last_irq; self.run_cycle(); self.abs_addr = if self.rel_addr >= 128 { self.pc.wrapping_add(self.rel_addr | 0xFF00) } else { self.pc.wrapping_add(self.rel_addr) }; if self.pages_differ(self.abs_addr, self.pc) { self.run_cycle(); } else { if skip_nmi { self.last_nmi = false; } if skip_irq { self.last_irq = false; } } self.pc = self.abs_addr; } /// BCC: Branch on Carry Clear pub(super) fn bcc(&mut self) { if self.get_flag(C) == 0 { self.branch(); } } /// BCS: Branch on Carry Set pub(super) fn bcs(&mut self) { if self.get_flag(C) == 1 { self.branch(); } } /// BEQ: Branch on Result Zero pub(super) fn beq(&mut self) { if self.get_flag(Z) == 1 { self.branch(); } } /// BMI: Branch on Result Negative pub(super) fn bmi(&mut self) { if self.get_flag(N) == 1 { self.branch(); } } /// BNE: Branch on Result Not Zero pub(super) fn bne(&mut self) { if self.get_flag(Z) == 0 { self.branch(); } } /// BPL: Branch on Result Positive pub(super) fn bpl(&mut self) { if self.get_flag(N) == 0 { self.branch(); } } /// BVC: Branch on Overflow Clear pub(super) fn bvc(&mut self) { if self.get_flag(V) == 0 { self.branch(); } } /// BVS: Branch on Overflow Set pub(super) fn bvs(&mut self) { if self.get_flag(V) == 1 { self.branch(); } } /// Jump opcodes /// JMP: Jump to Location // # address R/W description // --- ------- --- ------------------------------------------------- // 1 PC R fetch opcode, increment PC // 2 PC R fetch low address byte, increment PC // 3 PC R copy low address byte to PCL, fetch high address // byte to PCH pub(super) fn jmp(&mut self) { self.pc = self.abs_addr; } /// JSR: Jump to Location Save Return addr // # address R/W description // --- ------- --- ------------------------------------------------- // 1 PC R fetch opcode, increment PC // 2 PC R fetch low address byte, increment PC // 3 $0100,S R internal operation (predecrement S?) // 4 $0100,S W push PCH on stack, decrement S // 5 $0100,S W push PCL on stack, decrement S // 6 PC R copy low address byte to PCL, fetch high address // byte to PCH pub(super) fn jsr(&mut self) { let _ = self.read(SP_BASE | Addr::from(self.sp)); // Cycle 3 self.push_stackw(self.pc.wrapping_sub(1)); self.pc = self.abs_addr; } /// RTI: Return from Interrupt // # address R/W description // --- ------- --- ----------------------------------------------- // 1 PC R fetch opcode, increment PC // 2 PC R read next instruction byte (and throw it away) // 3 $0100,S R increment S // 4 $0100,S R pull P from stack, increment S // 5 $0100,S R pull PCL from stack, increment S // 6 $0100,S R pull PCH from stack pub(super) fn rti(&mut self) { let _ = self.read(SP_BASE | Addr::from(self.sp)); // Cycle 3 self.status = self.pop_stackb(); // Cycle 4 self.status &= !(U as u8); self.status &= !(B as u8); self.pc = self.pop_stackw(); // Cycles 5 & 6 } /// RTS: Return from Subroutine // # address R/W description // --- ------- --- ----------------------------------------------- // 1 PC R fetch opcode, increment PC // 2 PC R read next instruction byte (and throw it away) // 3 $0100,S R increment S // 4 $0100,S R pull PCL from stack, increment S // 5 $0100,S R pull PCH from stack // 6 PC R increment PC pub(super) fn rts(&mut self) { let _ = self.read(SP_BASE | Addr::from(self.sp)); // Cycle 3 self.pc = self.pop_stackw().wrapping_add(1); // Cycles 4 & 5 let _ = self.read(self.pc); // Cycle 6 } /// Register opcodes /// CLC: Clear Carry Flag pub(super) fn clc(&mut self) { self.set_flag(C, false); } /// SEC: Set Carry Flag pub(super) fn sec(&mut self) { self.set_flag(C, true); } /// CLD: Clear Decimal Mode pub(super) fn cld(&mut self) { self.set_flag(D, false); } /// SED: Set Decimal Mode pub(super) fn sed(&mut self) { self.set_flag(D, true); } /// CLI: Clear Interrupt Disable Bit pub(super) fn cli(&mut self) { self.set_flag(I, false); } /// SEI: Set Interrupt Disable Status pub(super) fn sei(&mut self) { self.set_flag(I, true); } /// CLV: Clear Overflow Flag pub(super) fn clv(&mut self) { self.set_flag(V, false); } /// Compare opcodes /// Utility function used by all compare instructions pub(super) fn compare(&mut self, a: Byte, b: Byte) { let result = a.wrapping_sub(b); self.set_flags_zn(result); self.set_flag(C, a >= b); } /// CMP: Compare M and A pub(super) fn cmp(&mut self) { self.fetch_data(); self.compare(self.acc, self.fetched_data); } /// CPX: Compare M and X pub(super) fn cpx(&mut self) { self.fetch_data(); self.compare(self.x, self.fetched_data); } /// CPY: Compare M and Y pub(super) fn cpy(&mut self) { self.fetch_data(); self.compare(self.y, self.fetched_data); } /// Stack opcodes /// PHP: Push Processor Status on Stack // # address R/W description // --- ------- --- ----------------------------------------------- // 1 PC R fetch opcode, increment PC // 2 PC R read next instruction byte (and throw it away) // 3 $0100,S W push register on stack, decrement S pub(super) fn php(&mut self) { // Set U and B when pushing during PHP and BRK self.push_stackb(self.status | U as u8 | B as u8); } /// PLP: Pull Processor Status from Stack // # address R/W description // --- ------- --- ----------------------------------------------- // 1 PC R fetch opcode, increment PC // 2 PC R read next instruction byte (and throw it away) // 3 $0100,S R increment S // 4 $0100,S R pull register from stack pub(super) fn plp(&mut self) { let _ = self.read(SP_BASE | Addr::from(self.sp)); // Cycle 3 self.status = self.pop_stackb(); } /// PHA: Push A on Stack // # address R/W description // --- ------- --- ----------------------------------------------- // 1 PC R fetch opcode, increment PC // 2 PC R read next instruction byte (and throw it away) // 3 $0100,S W push register on stack, decrement S pub(super) fn pha(&mut self) { self.push_stackb(self.acc); } /// PLA: Pull A from Stack // # address R/W description // --- ------- --- ----------------------------------------------- // 1 PC R fetch opcode, increment PC // 2 PC R read next instruction byte (and throw it away) // 3 $0100,S R increment S // 4 $0100,S R pull register from stack pub(super) fn pla(&mut self) { let _ = self.read(SP_BASE | Addr::from(self.sp)); // Cycle 3 self.acc = self.pop_stackb(); self.set_flags_zn(self.acc); } /// System opcodes /// BRK: Force Break Interrupt // # address R/W description // --- ------- --- ----------------------------------------------- // 1 PC R fetch opcode, increment PC // 2 PC R read next instruction byte (and throw it away), // increment PC // 3 $0100,S W push PCH on stack (with B flag set), decrement S // 4 $0100,S W push PCL on stack, decrement S // 5 $0100,S W push P on stack, decrement S // 6 $FFFE R fetch PCL // 7 $FFFF R fetch PCH pub(super) fn brk(&mut self) { self.fetch_data(); // throw away self.push_stackw(self.pc); // Set U and B when pushing during PHP and BRK self.push_stackb(self.status | U as u8 | B as u8); self.set_flag(I, true); if self.last_nmi { self.nmi_pending = false; self.bus.ppu.nmi_pending = false; self.pc = self.readw(NMI_ADDR); } else { self.pc = self.readw(IRQ_ADDR); } // Prevent NMI from triggering immediately after BRK if self.last_nmi { self.last_nmi = false; } } /// NOP: No Operation pub(super) fn nop(&mut self) { self.fetch_data(); // throw away } /// Unofficial opcodes /// SKB: Like NOP pub(super) fn skb(&mut self) { self.fetch_data(); } /// IGN: Like NOP, but can cross page boundary pub(super) fn ign(&mut self) { self.fetch_data(); } /// XXX: Captures all unimplemented opcodes pub(super) fn xxx(&mut self) { panic!( "Invalid opcode ${:02X} {:?} #{:?} encountered!", self.instr.opcode(), self.instr.op(), self.instr.addr_mode(), ); } /// ISC/ISB: Shortcut for INC then SBC pub(super) fn isb(&mut self) { // INC self.fetch_data(); self.write_fetched(self.fetched_data); // dummy write let val = self.fetched_data.wrapping_add(1); // SBC let a = self.acc; let (x1, o1) = a.overflowing_sub(val); let (x2, o2) = x1.overflowing_sub(1 - self.get_flag(C)); self.acc = x2; self.set_flag(C, !(o1 | o2)); self.set_flag(V, (a ^ val) & 0x80 != 0 && (a ^ self.acc) & 0x80 != 0); self.set_flags_zn(self.acc); self.write_fetched(val); } /// DCP: Shortcut for DEC then CMP pub(super) fn dcp(&mut self) { // DEC self.fetch_data(); self.write_fetched(self.fetched_data); // dummy write let val = self.fetched_data.wrapping_sub(1); // CMP self.compare(self.acc, val); self.write_fetched(val); } /// AXS: A & X into X pub(super) fn axs(&mut self) { self.fetch_data(); let t = u32::from(self.acc & self.x).wrapping_sub(u32::from(self.fetched_data)); self.set_flags_zn((t & 0xFF) as u8); self.set_flag(C, (((t >> 8) & 0x01) ^ 0x01) == 0x01); self.x = (t & 0xFF) as Byte; } /// LAS: Shortcut for LDA then TSX pub(super) fn las(&mut self) { self.lda(); self.tsx(); } /// LAX: Shortcut for LDA then TAX pub(super) fn lax(&mut self) { self.lda(); self.tax(); } /// AHX/SHA/AXA: AND X with A then AND with 7, then store in memory pub(super) fn ahx(&mut self) { let val = self.acc & self.x & self .fetched_data .wrapping_sub(self.y) .wrapping_shr(8) .wrapping_add(1); self.write_fetched(val); } /// SAX: AND A with X pub(super) fn sax(&mut self) { if self.instr.addr_mode() == IDY { self.fetch_data(); } let val = self.acc & self.x; self.write_fetched(val); } /// XAA: Unknown pub(super) fn xaa(&mut self) { self.fetch_data(); self.acc |= 0xEE; self.acc &= self.x; // AND self.acc &= self.fetched_data; self.set_flags_zn(self.acc); } /// SXA/SHX/XAS: AND X with the high byte of the target address + 1 pub(super) fn sxa(&mut self) { let hi = (self.abs_addr >> 8) as Byte; let lo = (self.abs_addr & 0xFF) as Byte; let val = self.x & hi.wrapping_add(1); self.abs_addr = ((Addr::from(self.x) & Addr::from(hi.wrapping_add(1))) << 8) | Addr::from(lo); self.write_fetched(val); } /// SYA/SHY/SAY: AND Y with the high byte of the target address + 1 pub(super) fn sya(&mut self) { let hi = (self.abs_addr >> 8) as Byte; let lo = (self.abs_addr & 0xFF) as Byte; let val = self.y & hi.wrapping_add(1); self.abs_addr = ((Addr::from(self.y) & Addr::from(hi.wrapping_add(1))) << 8) | Addr::from(lo); self.write_fetched(val); } /// RRA: Shortcut for ROR then ADC pub(super) fn rra(&mut self) { self.fetch_data(); // ROR self.write_fetched(self.fetched_data); // dummy write let mut ret = self.fetched_data.rotate_right(1); if self.get_flag(C) == 1 { ret |= 1 << 7; } else { ret &= !(1 << 7); } self.set_flag(C, self.fetched_data & 1 > 0); // ADC let a = self.acc; let (x1, o1) = ret.overflowing_add(a); let (x2, o2) = x1.overflowing_add(self.get_flag(C)); self.acc = x2; self.set_flag(C, o1 | o2); self.set_flag(V, (a ^ ret) & 0x80 == 0 && (a ^ self.acc) & 0x80 != 0); self.set_flags_zn(self.acc); self.write_fetched(ret); } /// TAS: Shortcut for STA then TXS pub(super) fn tas(&mut self) { // STA self.write(self.abs_addr, self.acc); // TXS self.sp = self.x; } /// ARR: Shortcut for AND #imm then ROR, but sets flags differently /// C is bit 6 and V is bit 6 xor bit 5 pub(super) fn arr(&mut self) { // AND self.fetch_data(); self.acc &= self.fetched_data; // ROR self.set_flag(V, (self.acc ^ (self.acc >> 1)) & 0x40 == 0x40); let t = self.acc >> 7; self.acc >>= 1; self.acc |= self.get_flag(C) << 7; self.set_flag(C, t & 0x01 == 0x01); self.set_flags_zn(self.acc); } /// SRA: Shortcut for LSR then EOR pub(super) fn sre(&mut self) { self.fetch_data(); // LSR self.write_fetched(self.fetched_data); // dummy write self.set_flag(C, self.fetched_data & 1 > 0); let val = self.fetched_data.wrapping_shr(1); // EOR self.acc ^= val; self.set_flags_zn(self.acc); self.write_fetched(val); } /// ALR/ASR: Shortcut for AND #imm then LSR pub(super) fn alr(&mut self) { // AND self.fetch_data(); self.acc &= self.fetched_data; // LSR self.set_flag(C, self.acc & 0x01 == 0x01); self.acc >>= 1; self.set_flags_zn(self.acc); } /// RLA: Shortcut for ROL then AND pub(super) fn rla(&mut self) { self.fetch_data(); // ROL self.write_fetched(self.fetched_data); // dummy write let old_c = self.get_flag(C); self.set_flag(C, (self.fetched_data >> 7) & 1 > 0); let val = (self.fetched_data << 1) | old_c; // AND self.acc &= val; self.set_flags_zn(self.acc); self.write_fetched(val); } /// ANC/AAC: AND #imm but puts bit 7 into carry as if ASL was executed pub(super) fn anc(&mut self) { // AND self.fetch_data(); self.acc &= self.fetched_data; self.set_flags_zn(self.acc); // Put bit 7 into carry self.set_flag(C, (self.acc >> 7) & 1 > 0); } /// SLO: Shortcut for ASL then ORA pub(super) fn slo(&mut self) { self.fetch_data(); // ASL self.write_fetched(self.fetched_data); // dummy write self.set_flag(C, (self.fetched_data >> 7) & 1 > 0); let val = self.fetched_data.wrapping_shl(1); self.write_fetched(val); // ORA self.acc |= val; self.set_flags_zn(self.acc); } } impl Savable for Operation { fn save<F: Write>(&self, fh: &mut F) -> NesResult<()> { (*self as u8).save(fh) } fn load<F: Read>(&mut self, fh: &mut F) -> NesResult<()> { let mut val = 0u8; val.load(fh)?; *self = match val { 0 => Operation::ADC, 1 => Operation::AND, 2 => Operation::ASL, 3 => Operation::BCC, 4 => Operation::BCS, 5 => Operation::BEQ, 6 => Operation::BIT, 7 => Operation::BMI, 8 => Operation::BNE, 9 => Operation::BPL, 10 => Operation::BRK, 11 => Operation::BVC, 12 => Operation::BVS, 13 => Operation::CLC, 14 => Operation::CLD, 15 => Operation::CLI, 16 => Operation::CLV, 17 => Operation::CMP, 18 => Operation::CPX, 19 => Operation::CPY, 20 => Operation::DEC, 21 => Operation::DEX, 22 => Operation::DEY, 23 => Operation::EOR, 24 => Operation::INC, 25 => Operation::INX, 26 => Operation::INY, 27 => Operation::JMP, 28 => Operation::JSR, 29 => Operation::LDA, 30 => Operation::LDX, 31 => Operation::LDY, 32 => Operation::LSR, 33 => Operation::NOP, 34 => Operation::ORA, 35 => Operation::PHA, 36 => Operation::PHP, 37 => Operation::PLA, 38 => Operation::PLP, 39 => Operation::ROL, 40 => Operation::ROR, 41 => Operation::RTI, 42 => Operation::RTS, 43 => Operation::SBC, 44 => Operation::SEC, 45 => Operation::SED, 46 => Operation::SEI, 47 => Operation::STA, 48 => Operation::STX, 49 => Operation::STY, 50 => Operation::TAX, 51 => Operation::TAY, 52 => Operation::TSX, 53 => Operation::TXA, 54 => Operation::TXS, 55 => Operation::TYA, 56 => Operation::SKB, 57 => Operation::IGN, 58 => Operation::ISB, 59 => Operation::DCP, 60 => Operation::AXS, 61 => Operation::LAS, 62 => Operation::LAX, 63 => Operation::AHX, 64 => Operation::SAX, 65 => Operation::XAA, 66 => Operation::SXA, 67 => Operation::RRA, 68 => Operation::TAS, 69 => Operation::SYA, 70 => Operation::ARR, 71 => Operation::SRE, 72 => Operation::ALR, 73 => Operation::RLA, 74 => Operation::ANC, 75 => Operation::SLO, 76 => Operation::XXX, _ => panic!("invalid Operation value"), }; Ok(()) } } impl Savable for AddrMode { fn save<F: Write>(&self, fh: &mut F) -> NesResult<()> { (*self as u8).save(fh) } fn load<F: Read>(&mut self, fh: &mut F) -> NesResult<()> { let mut val = 0u8; val.load(fh)?; *self = match val { 0 => AddrMode::IMM, 1 => AddrMode::ZP0, 2 => AddrMode::ZPX, 3 => AddrMode::ZPY, 4 => AddrMode::ABS, 5 => AddrMode::ABX, 6 => AddrMode::ABY, 7 => AddrMode::IND, 8 => AddrMode::IDX, 9 => AddrMode::IDY, 10 => AddrMode::REL, 11 => AddrMode::ACC, 12 => AddrMode::IMP, _ => panic!("invalid AddrMode value"), }; Ok(()) } } impl Savable for Instr { fn save<F: Write>(&self, fh: &mut F) -> NesResult<()> { self.0.save(fh)?; self.1.save(fh)?; self.2.save(fh)?; self.3.save(fh) } fn load<F: Read>(&mut self, fh: &mut F) -> NesResult<()> { self.0.load(fh)?; self.1.load(fh)?; self.2.load(fh)?; self.3.load(fh) } } impl fmt::Debug for Instr { fn fmt(&self, f: &mut fmt::Formatter) -> std::result::Result<(), fmt::Error> { let mut op = self.op(); let unofficial = match self.op() { XXX | ISB | DCP | AXS | LAS | LAX | AHX | SAX | XAA | SXA | RRA | TAS | SYA | ARR | SRE | ALR | RLA | ANC | SLO => "*", NOP if self.opcode() != 0xEA => "*", // 0xEA is the only official NOP SKB | IGN => { op = NOP; "*" } SBC if self.opcode() == 0xEB => "*", _ => "", }; write!(f, "{:1}{:?}", unofficial, op) } }