Struct teensy4_bsp::t40::Pins[−][src]

pub struct Pins {
Show 40 fields
    pub p0: Pad<AD_B0, UInt<UInt<UTerm, B1>, B1>>,
    pub p1: Pad<AD_B0, UInt<UInt<UTerm, B1>, B0>>,
    pub p2: Pad<EMC, UInt<UInt<UInt<UTerm, B1>, B0>, B0>>,
    pub p3: Pad<EMC, UInt<UInt<UInt<UTerm, B1>, B0>, B1>>,
    pub p4: Pad<EMC, UInt<UInt<UInt<UTerm, B1>, B1>, B0>>,
    pub p5: Pad<EMC, UInt<UInt<UInt<UInt<UTerm, B1>, B0>, B0>, B0>>,
    pub p6: Pad<B0, UInt<UInt<UInt<UInt<UTerm, B1>, B0>, B1>, B0>>,
    pub p7: Pad<B1, UInt<UTerm, B1>>,
    pub p8: Pad<B1, UTerm>,
    pub p9: Pad<B0, UInt<UInt<UInt<UInt<UTerm, B1>, B0>, B1>, B1>>,
    pub p10: Pad<B0, UTerm>,
    pub p11: Pad<B0, UInt<UInt<UTerm, B1>, B0>>,
    pub p12: Pad<B0, UInt<UTerm, B1>>,
    pub p13: Pad<B0, UInt<UInt<UTerm, B1>, B1>>,
    pub p14: Pad<AD_B1, UInt<UInt<UTerm, B1>, B0>>,
    pub p15: Pad<AD_B1, UInt<UInt<UTerm, B1>, B1>>,
    pub p16: Pad<AD_B1, UInt<UInt<UInt<UTerm, B1>, B1>, B1>>,
    pub p17: Pad<AD_B1, UInt<UInt<UInt<UTerm, B1>, B1>, B0>>,
    pub p18: Pad<AD_B1, UInt<UTerm, B1>>,
    pub p19: Pad<AD_B1, UTerm>,
    pub p20: Pad<AD_B1, UInt<UInt<UInt<UInt<UTerm, B1>, B0>, B1>, B0>>,
    pub p21: Pad<AD_B1, UInt<UInt<UInt<UInt<UTerm, B1>, B0>, B1>, B1>>,
    pub p22: Pad<AD_B1, UInt<UInt<UInt<UInt<UTerm, B1>, B0>, B0>, B0>>,
    pub p23: Pad<AD_B1, UInt<UInt<UInt<UInt<UTerm, B1>, B0>, B0>, B1>>,
    pub p24: Pad<AD_B0, UInt<UInt<UInt<UInt<UTerm, B1>, B1>, B0>, B0>>,
    pub p25: Pad<AD_B0, UInt<UInt<UInt<UInt<UTerm, B1>, B1>, B0>, B1>>,
    pub p26: Pad<AD_B1, UInt<UInt<UInt<UInt<UTerm, B1>, B1>, B1>, B0>>,
    pub p27: Pad<AD_B1, UInt<UInt<UInt<UInt<UTerm, B1>, B1>, B1>, B1>>,
    pub p28: Pad<EMC, UInt<UInt<UInt<UInt<UInt<UInt<UTerm, B1>, B0>, B0>, B0>, B0>, B0>>,
    pub p29: Pad<EMC, UInt<UInt<UInt<UInt<UInt<UTerm, B1>, B1>, B1>, B1>, B1>>,
    pub p30: Pad<EMC, UInt<UInt<UInt<UInt<UInt<UInt<UTerm, B1>, B0>, B0>, B1>, B0>, B1>>,
    pub p31: Pad<EMC, UInt<UInt<UInt<UInt<UInt<UInt<UTerm, B1>, B0>, B0>, B1>, B0>, B0>>,
    pub p32: Pad<B0, UInt<UInt<UInt<UInt<UTerm, B1>, B1>, B0>, B0>>,
    pub p33: Pad<EMC, UInt<UInt<UInt<UTerm, B1>, B1>, B1>>,
    pub p34: Pad<SD_B0, UInt<UInt<UTerm, B1>, B1>>,
    pub p35: Pad<SD_B0, UInt<UInt<UTerm, B1>, B0>>,
    pub p36: Pad<SD_B0, UInt<UTerm, B1>>,
    pub p37: Pad<SD_B0, UTerm>,
    pub p38: Pad<SD_B0, UInt<UInt<UInt<UTerm, B1>, B0>, B1>>,
    pub p39: Pad<SD_B0, UInt<UInt<UInt<UTerm, B1>, B0>, B0>>,

}
Expand description

Teensy 4.0 pins

See from_pads to safely constrain the processor’s pads, and acquire Teensy 4.0 pins. Or, use new to unsafely create pins.

Fields

p0: Pad<AD_B0, UInt<UInt<UTerm, B1>, B1>>

Pin 0

p1: Pad<AD_B0, UInt<UInt<UTerm, B1>, B0>>

Pin 1

p2: Pad<EMC, UInt<UInt<UInt<UTerm, B1>, B0>, B0>>

Pin 2

p3: Pad<EMC, UInt<UInt<UInt<UTerm, B1>, B0>, B1>>

Pin 3

p4: Pad<EMC, UInt<UInt<UInt<UTerm, B1>, B1>, B0>>

Pin 4

p5: Pad<EMC, UInt<UInt<UInt<UInt<UTerm, B1>, B0>, B0>, B0>>

Pin 5

p6: Pad<B0, UInt<UInt<UInt<UInt<UTerm, B1>, B0>, B1>, B0>>

Pin 6

p7: Pad<B1, UInt<UTerm, B1>>

Pin 7

p8: Pad<B1, UTerm>

Pin 8

p9: Pad<B0, UInt<UInt<UInt<UInt<UTerm, B1>, B0>, B1>, B1>>

Pin 9

p10: Pad<B0, UTerm>

Pin 10

p11: Pad<B0, UInt<UInt<UTerm, B1>, B0>>

Pin 11

p12: Pad<B0, UInt<UTerm, B1>>

Pin 12

p13: Pad<B0, UInt<UInt<UTerm, B1>, B1>>

Pin 13

p14: Pad<AD_B1, UInt<UInt<UTerm, B1>, B0>>

Pin 14

p15: Pad<AD_B1, UInt<UInt<UTerm, B1>, B1>>

Pin 15

p16: Pad<AD_B1, UInt<UInt<UInt<UTerm, B1>, B1>, B1>>

Pin 16

p17: Pad<AD_B1, UInt<UInt<UInt<UTerm, B1>, B1>, B0>>

Pin 17

p18: Pad<AD_B1, UInt<UTerm, B1>>

Pin 18

p19: Pad<AD_B1, UTerm>

Pin 19

p20: Pad<AD_B1, UInt<UInt<UInt<UInt<UTerm, B1>, B0>, B1>, B0>>

Pin 20

p21: Pad<AD_B1, UInt<UInt<UInt<UInt<UTerm, B1>, B0>, B1>, B1>>

Pin 21

p22: Pad<AD_B1, UInt<UInt<UInt<UInt<UTerm, B1>, B0>, B0>, B0>>

Pin 22

p23: Pad<AD_B1, UInt<UInt<UInt<UInt<UTerm, B1>, B0>, B0>, B1>>

Pin 23

p24: Pad<AD_B0, UInt<UInt<UInt<UInt<UTerm, B1>, B1>, B0>, B0>>

Pin 24

p25: Pad<AD_B0, UInt<UInt<UInt<UInt<UTerm, B1>, B1>, B0>, B1>>

Pin 25

p26: Pad<AD_B1, UInt<UInt<UInt<UInt<UTerm, B1>, B1>, B1>, B0>>

Pin 26

p27: Pad<AD_B1, UInt<UInt<UInt<UInt<UTerm, B1>, B1>, B1>, B1>>

Pin 27

p28: Pad<EMC, UInt<UInt<UInt<UInt<UInt<UInt<UTerm, B1>, B0>, B0>, B0>, B0>, B0>>

Pin 28

p29: Pad<EMC, UInt<UInt<UInt<UInt<UInt<UTerm, B1>, B1>, B1>, B1>, B1>>

Pin 29

p30: Pad<EMC, UInt<UInt<UInt<UInt<UInt<UInt<UTerm, B1>, B0>, B0>, B1>, B0>, B1>>

Pin 30

p31: Pad<EMC, UInt<UInt<UInt<UInt<UInt<UInt<UTerm, B1>, B0>, B0>, B1>, B0>, B0>>

Pin 31

p32: Pad<B0, UInt<UInt<UInt<UInt<UTerm, B1>, B1>, B0>, B0>>

Pin 32

p33: Pad<EMC, UInt<UInt<UInt<UTerm, B1>, B1>, B1>>

Pin 33

p34: Pad<SD_B0, UInt<UInt<UTerm, B1>, B1>>

Pin 34

p35: Pad<SD_B0, UInt<UInt<UTerm, B1>, B0>>

Pin 35

p36: Pad<SD_B0, UInt<UTerm, B1>>

Pin 36

p37: Pad<SD_B0, UTerm>

Pin 37

p38: Pad<SD_B0, UInt<UInt<UInt<UTerm, B1>, B0>, B1>>

Pin 38

p39: Pad<SD_B0, UInt<UInt<UInt<UTerm, B1>, B0>, B0>>

Pin 39

Implementations

Create an instance of Pins when you do not have a handle to the processor pads

Safety

Caller must ensure that the pins are not aliased elsewhere in the program. This could include

  • an existing handle to the imxrt-iomuxc pads,
  • another instance of Pins that was safely acquired using from_pads.

Erase the types of all pins

Auto Trait Implementations

Blanket Implementations

Gets the TypeId of self. Read more

Immutably borrows from an owned value. Read more

Mutably borrows from an owned value. Read more

Performs the conversion.

Performs the conversion.

Should always be Self

The type returned in the event of a conversion error.

Performs the conversion.

The type returned in the event of a conversion error.

Performs the conversion.