pub type CEIS_W<'a, const O: u8> = BitWriter<'a, u32, SR_SPEC, CEIS_A, O>;
Field CEIS writer - Clock error interrupt status
CEIS
The RNG clock is correct (fRNGCLK> fHCLK/32)
The RNG clock before internal divider has been detected too slow (fRNGCLK< fHCLK/32)