Module stm32wl::stm32wl5x_cm4::rcc::c2apb1smenr2

CPU2 APB1 peripheral clocks enable in Sleep mode register 2 [dual core device only]

Re-exports

pub use LPUART1SMEN_A as LPTIM3SMEN_A;

pub use LPUART1SMEN_A as LPTIM2SMEN_A;

pub use LPUART1SMEN_R as LPTIM3SMEN_R;

pub use LPUART1SMEN_R as LPTIM2SMEN_R;

pub use LPUART1SMEN_W as LPTIM3SMEN_W;

pub use LPUART1SMEN_W as LPTIM2SMEN_W;

Structs

C2APB1SMENR2_SPEC

CPU2 APB1 peripheral clocks enable in Sleep mode register 2 [dual core device only]

R

Register C2APB1SMENR2 reader

W

Register C2APB1SMENR2 writer

Enums

LPUART1SMEN_A

Low power UART 1 clock enable during CPU2 CSleep and CStop mode

Type Definitions

LPUART1SMEN_R

Field LPUART1SMEN reader - Low power UART 1 clock enable during CPU2 CSleep and CStop mode

LPUART1SMEN_W

Field LPUART1SMEN writer - Low power UART 1 clock enable during CPU2 CSleep and CStop mode