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#[doc = "Register `CR1` reader"]
pub struct R(crate::R<CR1_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<CR1_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<CR1_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<CR1_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `CR1` writer"]
pub struct W(crate::W<CR1_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<CR1_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<CR1_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<CR1_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `PE` reader - Peripheral enable"]
pub type PE_R = crate::BitReader<bool>;
#[doc = "Field `PE` writer - Peripheral enable"]
pub type PE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR1_SPEC, bool, O>;
#[doc = "Field `TXIE` reader - TX Interrupt enable"]
pub type TXIE_R = crate::BitReader<bool>;
#[doc = "Field `TXIE` writer - TX Interrupt enable"]
pub type TXIE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR1_SPEC, bool, O>;
#[doc = "Field `RXIE` reader - RX Interrupt enable"]
pub type RXIE_R = crate::BitReader<bool>;
#[doc = "Field `RXIE` writer - RX Interrupt enable"]
pub type RXIE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR1_SPEC, bool, O>;
#[doc = "Field `ADDRIE` reader - Address match interrupt enable (slave only)"]
pub type ADDRIE_R = crate::BitReader<bool>;
#[doc = "Field `ADDRIE` writer - Address match interrupt enable (slave only)"]
pub type ADDRIE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR1_SPEC, bool, O>;
#[doc = "Field `NACKIE` reader - Not acknowledge received interrupt enable"]
pub type NACKIE_R = crate::BitReader<bool>;
#[doc = "Field `NACKIE` writer - Not acknowledge received interrupt enable"]
pub type NACKIE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR1_SPEC, bool, O>;
#[doc = "Field `STOPIE` reader - STOP detection Interrupt enable"]
pub type STOPIE_R = crate::BitReader<bool>;
#[doc = "Field `STOPIE` writer - STOP detection Interrupt enable"]
pub type STOPIE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR1_SPEC, bool, O>;
#[doc = "Field `TCIE` reader - Transfer Complete interrupt enable"]
pub type TCIE_R = crate::BitReader<bool>;
#[doc = "Field `TCIE` writer - Transfer Complete interrupt enable"]
pub type TCIE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR1_SPEC, bool, O>;
#[doc = "Field `ERRIE` reader - Error interrupts enable"]
pub type ERRIE_R = crate::BitReader<bool>;
#[doc = "Field `ERRIE` writer - Error interrupts enable"]
pub type ERRIE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR1_SPEC, bool, O>;
#[doc = "Field `DNF` reader - Digital noise filter"]
pub type DNF_R = crate::FieldReader<u8, u8>;
#[doc = "Field `DNF` writer - Digital noise filter"]
pub type DNF_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CR1_SPEC, u8, u8, 4, O>;
#[doc = "Field `ANFOFF` reader - Analog noise filter OFF"]
pub type ANFOFF_R = crate::BitReader<bool>;
#[doc = "Field `ANFOFF` writer - Analog noise filter OFF"]
pub type ANFOFF_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR1_SPEC, bool, O>;
#[doc = "Field `TXDMAEN` reader - DMA transmission requests enable"]
pub type TXDMAEN_R = crate::BitReader<bool>;
#[doc = "Field `TXDMAEN` writer - DMA transmission requests enable"]
pub type TXDMAEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR1_SPEC, bool, O>;
#[doc = "Field `RXDMAEN` reader - DMA reception requests enable"]
pub type RXDMAEN_R = crate::BitReader<bool>;
#[doc = "Field `RXDMAEN` writer - DMA reception requests enable"]
pub type RXDMAEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR1_SPEC, bool, O>;
#[doc = "Field `SBC` reader - Slave byte control"]
pub type SBC_R = crate::BitReader<bool>;
#[doc = "Field `SBC` writer - Slave byte control"]
pub type SBC_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR1_SPEC, bool, O>;
#[doc = "Field `NOSTRETCH` reader - Clock stretching disable"]
pub type NOSTRETCH_R = crate::BitReader<bool>;
#[doc = "Field `NOSTRETCH` writer - Clock stretching disable"]
pub type NOSTRETCH_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR1_SPEC, bool, O>;
#[doc = "Field `WUPEN` reader - Wakeup from STOP enable"]
pub type WUPEN_R = crate::BitReader<bool>;
#[doc = "Field `WUPEN` writer - Wakeup from STOP enable"]
pub type WUPEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR1_SPEC, bool, O>;
#[doc = "Field `GCEN` reader - General call enable"]
pub type GCEN_R = crate::BitReader<bool>;
#[doc = "Field `GCEN` writer - General call enable"]
pub type GCEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR1_SPEC, bool, O>;
#[doc = "Field `SMBHEN` reader - SMBus Host address enable"]
pub type SMBHEN_R = crate::BitReader<bool>;
#[doc = "Field `SMBHEN` writer - SMBus Host address enable"]
pub type SMBHEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR1_SPEC, bool, O>;
#[doc = "Field `SMBDEN` reader - SMBus Device Default address enable"]
pub type SMBDEN_R = crate::BitReader<bool>;
#[doc = "Field `SMBDEN` writer - SMBus Device Default address enable"]
pub type SMBDEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR1_SPEC, bool, O>;
#[doc = "Field `ALERTEN` reader - SMBUS alert enable"]
pub type ALERTEN_R = crate::BitReader<bool>;
#[doc = "Field `ALERTEN` writer - SMBUS alert enable"]
pub type ALERTEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR1_SPEC, bool, O>;
#[doc = "Field `PECEN` reader - PEC enable"]
pub type PECEN_R = crate::BitReader<bool>;
#[doc = "Field `PECEN` writer - PEC enable"]
pub type PECEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR1_SPEC, bool, O>;
impl R {
#[doc = "Bit 0 - Peripheral enable"]
#[inline(always)]
pub fn pe(&self) -> PE_R {
PE_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - TX Interrupt enable"]
#[inline(always)]
pub fn txie(&self) -> TXIE_R {
TXIE_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - RX Interrupt enable"]
#[inline(always)]
pub fn rxie(&self) -> RXIE_R {
RXIE_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Address match interrupt enable (slave only)"]
#[inline(always)]
pub fn addrie(&self) -> ADDRIE_R {
ADDRIE_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Not acknowledge received interrupt enable"]
#[inline(always)]
pub fn nackie(&self) -> NACKIE_R {
NACKIE_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - STOP detection Interrupt enable"]
#[inline(always)]
pub fn stopie(&self) -> STOPIE_R {
STOPIE_R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - Transfer Complete interrupt enable"]
#[inline(always)]
pub fn tcie(&self) -> TCIE_R {
TCIE_R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - Error interrupts enable"]
#[inline(always)]
pub fn errie(&self) -> ERRIE_R {
ERRIE_R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bits 8:11 - Digital noise filter"]
#[inline(always)]
pub fn dnf(&self) -> DNF_R {
DNF_R::new(((self.bits >> 8) & 0x0f) as u8)
}
#[doc = "Bit 12 - Analog noise filter OFF"]
#[inline(always)]
pub fn anfoff(&self) -> ANFOFF_R {
ANFOFF_R::new(((self.bits >> 12) & 1) != 0)
}
#[doc = "Bit 14 - DMA transmission requests enable"]
#[inline(always)]
pub fn txdmaen(&self) -> TXDMAEN_R {
TXDMAEN_R::new(((self.bits >> 14) & 1) != 0)
}
#[doc = "Bit 15 - DMA reception requests enable"]
#[inline(always)]
pub fn rxdmaen(&self) -> RXDMAEN_R {
RXDMAEN_R::new(((self.bits >> 15) & 1) != 0)
}
#[doc = "Bit 16 - Slave byte control"]
#[inline(always)]
pub fn sbc(&self) -> SBC_R {
SBC_R::new(((self.bits >> 16) & 1) != 0)
}
#[doc = "Bit 17 - Clock stretching disable"]
#[inline(always)]
pub fn nostretch(&self) -> NOSTRETCH_R {
NOSTRETCH_R::new(((self.bits >> 17) & 1) != 0)
}
#[doc = "Bit 18 - Wakeup from STOP enable"]
#[inline(always)]
pub fn wupen(&self) -> WUPEN_R {
WUPEN_R::new(((self.bits >> 18) & 1) != 0)
}
#[doc = "Bit 19 - General call enable"]
#[inline(always)]
pub fn gcen(&self) -> GCEN_R {
GCEN_R::new(((self.bits >> 19) & 1) != 0)
}
#[doc = "Bit 20 - SMBus Host address enable"]
#[inline(always)]
pub fn smbhen(&self) -> SMBHEN_R {
SMBHEN_R::new(((self.bits >> 20) & 1) != 0)
}
#[doc = "Bit 21 - SMBus Device Default address enable"]
#[inline(always)]
pub fn smbden(&self) -> SMBDEN_R {
SMBDEN_R::new(((self.bits >> 21) & 1) != 0)
}
#[doc = "Bit 22 - SMBUS alert enable"]
#[inline(always)]
pub fn alerten(&self) -> ALERTEN_R {
ALERTEN_R::new(((self.bits >> 22) & 1) != 0)
}
#[doc = "Bit 23 - PEC enable"]
#[inline(always)]
pub fn pecen(&self) -> PECEN_R {
PECEN_R::new(((self.bits >> 23) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - Peripheral enable"]
#[inline(always)]
pub fn pe(&mut self) -> PE_W<0> {
PE_W::new(self)
}
#[doc = "Bit 1 - TX Interrupt enable"]
#[inline(always)]
pub fn txie(&mut self) -> TXIE_W<1> {
TXIE_W::new(self)
}
#[doc = "Bit 2 - RX Interrupt enable"]
#[inline(always)]
pub fn rxie(&mut self) -> RXIE_W<2> {
RXIE_W::new(self)
}
#[doc = "Bit 3 - Address match interrupt enable (slave only)"]
#[inline(always)]
pub fn addrie(&mut self) -> ADDRIE_W<3> {
ADDRIE_W::new(self)
}
#[doc = "Bit 4 - Not acknowledge received interrupt enable"]
#[inline(always)]
pub fn nackie(&mut self) -> NACKIE_W<4> {
NACKIE_W::new(self)
}
#[doc = "Bit 5 - STOP detection Interrupt enable"]
#[inline(always)]
pub fn stopie(&mut self) -> STOPIE_W<5> {
STOPIE_W::new(self)
}
#[doc = "Bit 6 - Transfer Complete interrupt enable"]
#[inline(always)]
pub fn tcie(&mut self) -> TCIE_W<6> {
TCIE_W::new(self)
}
#[doc = "Bit 7 - Error interrupts enable"]
#[inline(always)]
pub fn errie(&mut self) -> ERRIE_W<7> {
ERRIE_W::new(self)
}
#[doc = "Bits 8:11 - Digital noise filter"]
#[inline(always)]
pub fn dnf(&mut self) -> DNF_W<8> {
DNF_W::new(self)
}
#[doc = "Bit 12 - Analog noise filter OFF"]
#[inline(always)]
pub fn anfoff(&mut self) -> ANFOFF_W<12> {
ANFOFF_W::new(self)
}
#[doc = "Bit 14 - DMA transmission requests enable"]
#[inline(always)]
pub fn txdmaen(&mut self) -> TXDMAEN_W<14> {
TXDMAEN_W::new(self)
}
#[doc = "Bit 15 - DMA reception requests enable"]
#[inline(always)]
pub fn rxdmaen(&mut self) -> RXDMAEN_W<15> {
RXDMAEN_W::new(self)
}
#[doc = "Bit 16 - Slave byte control"]
#[inline(always)]
pub fn sbc(&mut self) -> SBC_W<16> {
SBC_W::new(self)
}
#[doc = "Bit 17 - Clock stretching disable"]
#[inline(always)]
pub fn nostretch(&mut self) -> NOSTRETCH_W<17> {
NOSTRETCH_W::new(self)
}
#[doc = "Bit 18 - Wakeup from STOP enable"]
#[inline(always)]
pub fn wupen(&mut self) -> WUPEN_W<18> {
WUPEN_W::new(self)
}
#[doc = "Bit 19 - General call enable"]
#[inline(always)]
pub fn gcen(&mut self) -> GCEN_W<19> {
GCEN_W::new(self)
}
#[doc = "Bit 20 - SMBus Host address enable"]
#[inline(always)]
pub fn smbhen(&mut self) -> SMBHEN_W<20> {
SMBHEN_W::new(self)
}
#[doc = "Bit 21 - SMBus Device Default address enable"]
#[inline(always)]
pub fn smbden(&mut self) -> SMBDEN_W<21> {
SMBDEN_W::new(self)
}
#[doc = "Bit 22 - SMBUS alert enable"]
#[inline(always)]
pub fn alerten(&mut self) -> ALERTEN_W<22> {
ALERTEN_W::new(self)
}
#[doc = "Bit 23 - PEC enable"]
#[inline(always)]
pub fn pecen(&mut self) -> PECEN_W<23> {
PECEN_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Control register 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cr1](index.html) module"]
pub struct CR1_SPEC;
impl crate::RegisterSpec for CR1_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [cr1::R](R) reader structure"]
impl crate::Readable for CR1_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [cr1::W](W) writer structure"]
impl crate::Writable for CR1_SPEC {
type Writer = W;
}
#[doc = "`reset()` method sets CR1 to value 0"]
impl crate::Resettable for CR1_SPEC {
#[inline(always)]
fn reset_value() -> Self::Ux {
0
}
}
