Struct stm32wb::W

pub struct W<U, REG> { /* fields omitted */ }

Register writer

Used as an argument to the closures in the write and modify methods of the register

Implementations

impl<U, REG> W<U, REG>

pub unsafe fn bits(&mut self, bits: U) -> &mut Self

Writes raw bits to the register

impl W<u32, Reg<u32, _IFCR>>

pub fn cteif7(&mut self) -> CTEIF7_W<'_>

Bit 27 - Channel x transfer error clear (x = 1 ..7)

pub fn chtif7(&mut self) -> CHTIF7_W<'_>

Bit 26 - Channel x half transfer clear (x = 1 ..7)

pub fn ctcif7(&mut self) -> CTCIF7_W<'_>

Bit 25 - Channel x transfer complete clear (x = 1 ..7)

pub fn cgif7(&mut self) -> CGIF7_W<'_>

Bit 24 - Channel x global interrupt clear (x = 1 ..7)

pub fn cteif6(&mut self) -> CTEIF6_W<'_>

Bit 23 - Channel x transfer error clear (x = 1 ..7)

pub fn chtif6(&mut self) -> CHTIF6_W<'_>

Bit 22 - Channel x half transfer clear (x = 1 ..7)

pub fn ctcif6(&mut self) -> CTCIF6_W<'_>

Bit 21 - Channel x transfer complete clear (x = 1 ..7)

pub fn cgif6(&mut self) -> CGIF6_W<'_>

Bit 20 - Channel x global interrupt clear (x = 1 ..7)

pub fn cteif5(&mut self) -> CTEIF5_W<'_>

Bit 19 - Channel x transfer error clear (x = 1 ..7)

pub fn chtif5(&mut self) -> CHTIF5_W<'_>

Bit 18 - Channel x half transfer clear (x = 1 ..7)

pub fn ctcif5(&mut self) -> CTCIF5_W<'_>

Bit 17 - Channel x transfer complete clear (x = 1 ..7)

pub fn cgif5(&mut self) -> CGIF5_W<'_>

Bit 16 - Channel x global interrupt clear (x = 1 ..7)

pub fn cteif4(&mut self) -> CTEIF4_W<'_>

Bit 15 - Channel x transfer error clear (x = 1 ..7)

pub fn chtif4(&mut self) -> CHTIF4_W<'_>

Bit 14 - Channel x half transfer clear (x = 1 ..7)

pub fn ctcif4(&mut self) -> CTCIF4_W<'_>

Bit 13 - Channel x transfer complete clear (x = 1 ..7)

pub fn cgif4(&mut self) -> CGIF4_W<'_>

Bit 12 - Channel x global interrupt clear (x = 1 ..7)

pub fn cteif3(&mut self) -> CTEIF3_W<'_>

Bit 11 - Channel x transfer error clear (x = 1 ..7)

pub fn chtif3(&mut self) -> CHTIF3_W<'_>

Bit 10 - Channel x half transfer clear (x = 1 ..7)

pub fn ctcif3(&mut self) -> CTCIF3_W<'_>

Bit 9 - Channel x transfer complete clear (x = 1 ..7)

pub fn cgif3(&mut self) -> CGIF3_W<'_>

Bit 8 - Channel x global interrupt clear (x = 1 ..7)

pub fn cteif2(&mut self) -> CTEIF2_W<'_>

Bit 7 - Channel x transfer error clear (x = 1 ..7)

pub fn chtif2(&mut self) -> CHTIF2_W<'_>

Bit 6 - Channel x half transfer clear (x = 1 ..7)

pub fn ctcif2(&mut self) -> CTCIF2_W<'_>

Bit 5 - Channel x transfer complete clear (x = 1 ..7)

pub fn cgif2(&mut self) -> CGIF2_W<'_>

Bit 4 - Channel x global interrupt clear (x = 1 ..7)

pub fn cteif1(&mut self) -> CTEIF1_W<'_>

Bit 3 - Channel x transfer error clear (x = 1 ..7)

pub fn chtif1(&mut self) -> CHTIF1_W<'_>

Bit 2 - Channel x half transfer clear (x = 1 ..7)

pub fn ctcif1(&mut self) -> CTCIF1_W<'_>

Bit 1 - Channel x transfer complete clear (x = 1 ..7)

pub fn cgif1(&mut self) -> CGIF1_W<'_>

Bit 0 - Channel x global interrupt clear (x = 1 ..7)

impl W<u32, Reg<u32, _CCR1>>

pub fn mem2mem(&mut self) -> MEM2MEM_W<'_>

Bit 14 - Memory to memory mode

pub fn pl(&mut self) -> PL_W<'_>

Bits 12:13 - Channel priority level

pub fn msize(&mut self) -> MSIZE_W<'_>

Bits 10:11 - Memory size

pub fn psize(&mut self) -> PSIZE_W<'_>

Bits 8:9 - Peripheral size

pub fn minc(&mut self) -> MINC_W<'_>

Bit 7 - Memory increment mode

pub fn pinc(&mut self) -> PINC_W<'_>

Bit 6 - Peripheral increment mode

pub fn circ(&mut self) -> CIRC_W<'_>

Bit 5 - Circular mode

pub fn dir(&mut self) -> DIR_W<'_>

Bit 4 - Data transfer direction

pub fn teie(&mut self) -> TEIE_W<'_>

Bit 3 - Transfer error interrupt enable

pub fn htie(&mut self) -> HTIE_W<'_>

Bit 2 - Half transfer interrupt enable

pub fn tcie(&mut self) -> TCIE_W<'_>

Bit 1 - Transfer complete interrupt enable

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - Channel enable

impl W<u32, Reg<u32, _CNDTR1>>

pub fn ndt(&mut self) -> NDT_W<'_>

Bits 0:15 - Number of data to transfer

impl W<u32, Reg<u32, _CPAR1>>

pub fn pa(&mut self) -> PA_W<'_>

Bits 0:31 - Peripheral address

impl W<u32, Reg<u32, _CMAR1>>

pub fn ma(&mut self) -> MA_W<'_>

Bits 0:31 - Memory address

impl W<u32, Reg<u32, _CCR2>>

pub fn mem2mem(&mut self) -> MEM2MEM_W<'_>

Bit 14 - Memory to memory mode

pub fn pl(&mut self) -> PL_W<'_>

Bits 12:13 - Channel priority level

pub fn msize(&mut self) -> MSIZE_W<'_>

Bits 10:11 - Memory size

pub fn psize(&mut self) -> PSIZE_W<'_>

Bits 8:9 - Peripheral size

pub fn minc(&mut self) -> MINC_W<'_>

Bit 7 - Memory increment mode

pub fn pinc(&mut self) -> PINC_W<'_>

Bit 6 - Peripheral increment mode

pub fn circ(&mut self) -> CIRC_W<'_>

Bit 5 - Circular mode

pub fn dir(&mut self) -> DIR_W<'_>

Bit 4 - Data transfer direction

pub fn teie(&mut self) -> TEIE_W<'_>

Bit 3 - Transfer error interrupt enable

pub fn htie(&mut self) -> HTIE_W<'_>

Bit 2 - Half transfer interrupt enable

pub fn tcie(&mut self) -> TCIE_W<'_>

Bit 1 - Transfer complete interrupt enable

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - Channel enable

impl W<u32, Reg<u32, _CNDTR2>>

pub fn ndt(&mut self) -> NDT_W<'_>

Bits 0:15 - Number of data to transfer

impl W<u32, Reg<u32, _CPAR2>>

pub fn pa(&mut self) -> PA_W<'_>

Bits 0:31 - Peripheral address

impl W<u32, Reg<u32, _CMAR2>>

pub fn ma(&mut self) -> MA_W<'_>

Bits 0:31 - Memory address

impl W<u32, Reg<u32, _CCR3>>

pub fn mem2mem(&mut self) -> MEM2MEM_W<'_>

Bit 14 - Memory to memory mode

pub fn pl(&mut self) -> PL_W<'_>

Bits 12:13 - Channel priority level

pub fn msize(&mut self) -> MSIZE_W<'_>

Bits 10:11 - Memory size

pub fn psize(&mut self) -> PSIZE_W<'_>

Bits 8:9 - Peripheral size

pub fn minc(&mut self) -> MINC_W<'_>

Bit 7 - Memory increment mode

pub fn pinc(&mut self) -> PINC_W<'_>

Bit 6 - Peripheral increment mode

pub fn circ(&mut self) -> CIRC_W<'_>

Bit 5 - Circular mode

pub fn dir(&mut self) -> DIR_W<'_>

Bit 4 - Data transfer direction

pub fn teie(&mut self) -> TEIE_W<'_>

Bit 3 - Transfer error interrupt enable

pub fn htie(&mut self) -> HTIE_W<'_>

Bit 2 - Half transfer interrupt enable

pub fn tcie(&mut self) -> TCIE_W<'_>

Bit 1 - Transfer complete interrupt enable

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - Channel enable

impl W<u32, Reg<u32, _CNDTR3>>

pub fn ndt(&mut self) -> NDT_W<'_>

Bits 0:15 - Number of data to transfer

impl W<u32, Reg<u32, _CPAR3>>

pub fn pa(&mut self) -> PA_W<'_>

Bits 0:31 - Peripheral address

impl W<u32, Reg<u32, _CMAR3>>

pub fn ma(&mut self) -> MA_W<'_>

Bits 0:31 - Memory address

impl W<u32, Reg<u32, _CCR4>>

pub fn mem2mem(&mut self) -> MEM2MEM_W<'_>

Bit 14 - Memory to memory mode

pub fn pl(&mut self) -> PL_W<'_>

Bits 12:13 - Channel priority level

pub fn msize(&mut self) -> MSIZE_W<'_>

Bits 10:11 - Memory size

pub fn psize(&mut self) -> PSIZE_W<'_>

Bits 8:9 - Peripheral size

pub fn minc(&mut self) -> MINC_W<'_>

Bit 7 - Memory increment mode

pub fn pinc(&mut self) -> PINC_W<'_>

Bit 6 - Peripheral increment mode

pub fn circ(&mut self) -> CIRC_W<'_>

Bit 5 - Circular mode

pub fn dir(&mut self) -> DIR_W<'_>

Bit 4 - Data transfer direction

pub fn teie(&mut self) -> TEIE_W<'_>

Bit 3 - Transfer error interrupt enable

pub fn htie(&mut self) -> HTIE_W<'_>

Bit 2 - Half transfer interrupt enable

pub fn tcie(&mut self) -> TCIE_W<'_>

Bit 1 - Transfer complete interrupt enable

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - Channel enable

impl W<u32, Reg<u32, _CNDTR4>>

pub fn ndt(&mut self) -> NDT_W<'_>

Bits 0:15 - Number of data to transfer

impl W<u32, Reg<u32, _CPAR4>>

pub fn pa(&mut self) -> PA_W<'_>

Bits 0:31 - Peripheral address

impl W<u32, Reg<u32, _CMAR4>>

pub fn ma(&mut self) -> MA_W<'_>

Bits 0:31 - Memory address

impl W<u32, Reg<u32, _CCR5>>

pub fn mem2mem(&mut self) -> MEM2MEM_W<'_>

Bit 14 - Memory to memory mode

pub fn pl(&mut self) -> PL_W<'_>

Bits 12:13 - Channel priority level

pub fn msize(&mut self) -> MSIZE_W<'_>

Bits 10:11 - Memory size

pub fn psize(&mut self) -> PSIZE_W<'_>

Bits 8:9 - Peripheral size

pub fn minc(&mut self) -> MINC_W<'_>

Bit 7 - Memory increment mode

pub fn pinc(&mut self) -> PINC_W<'_>

Bit 6 - Peripheral increment mode

pub fn circ(&mut self) -> CIRC_W<'_>

Bit 5 - Circular mode

pub fn dir(&mut self) -> DIR_W<'_>

Bit 4 - Data transfer direction

pub fn teie(&mut self) -> TEIE_W<'_>

Bit 3 - Transfer error interrupt enable

pub fn htie(&mut self) -> HTIE_W<'_>

Bit 2 - Half transfer interrupt enable

pub fn tcie(&mut self) -> TCIE_W<'_>

Bit 1 - Transfer complete interrupt enable

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - Channel enable

impl W<u32, Reg<u32, _CNDTR5>>

pub fn ndt(&mut self) -> NDT_W<'_>

Bits 0:15 - Number of data to transfer

impl W<u32, Reg<u32, _CPAR5>>

pub fn pa(&mut self) -> PA_W<'_>

Bits 0:31 - Peripheral address

impl W<u32, Reg<u32, _CMAR5>>

pub fn ma(&mut self) -> MA_W<'_>

Bits 0:31 - Memory address

impl W<u32, Reg<u32, _CCR6>>

pub fn mem2mem(&mut self) -> MEM2MEM_W<'_>

Bit 14 - Memory to memory mode

pub fn pl(&mut self) -> PL_W<'_>

Bits 12:13 - Channel priority level

pub fn msize(&mut self) -> MSIZE_W<'_>

Bits 10:11 - Memory size

pub fn psize(&mut self) -> PSIZE_W<'_>

Bits 8:9 - Peripheral size

pub fn minc(&mut self) -> MINC_W<'_>

Bit 7 - Memory increment mode

pub fn pinc(&mut self) -> PINC_W<'_>

Bit 6 - Peripheral increment mode

pub fn circ(&mut self) -> CIRC_W<'_>

Bit 5 - Circular mode

pub fn dir(&mut self) -> DIR_W<'_>

Bit 4 - Data transfer direction

pub fn teie(&mut self) -> TEIE_W<'_>

Bit 3 - Transfer error interrupt enable

pub fn htie(&mut self) -> HTIE_W<'_>

Bit 2 - Half transfer interrupt enable

pub fn tcie(&mut self) -> TCIE_W<'_>

Bit 1 - Transfer complete interrupt enable

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - Channel enable

impl W<u32, Reg<u32, _CNDTR6>>

pub fn ndt(&mut self) -> NDT_W<'_>

Bits 0:15 - Number of data to transfer

impl W<u32, Reg<u32, _CPAR6>>

pub fn pa(&mut self) -> PA_W<'_>

Bits 0:31 - Peripheral address

impl W<u32, Reg<u32, _CMAR6>>

pub fn ma(&mut self) -> MA_W<'_>

Bits 0:31 - Memory address

impl W<u32, Reg<u32, _CCR7>>

pub fn mem2mem(&mut self) -> MEM2MEM_W<'_>

Bit 14 - Memory to memory mode

pub fn pl(&mut self) -> PL_W<'_>

Bits 12:13 - Channel priority level

pub fn msize(&mut self) -> MSIZE_W<'_>

Bits 10:11 - Memory size

pub fn psize(&mut self) -> PSIZE_W<'_>

Bits 8:9 - Peripheral size

pub fn minc(&mut self) -> MINC_W<'_>

Bit 7 - Memory increment mode

pub fn pinc(&mut self) -> PINC_W<'_>

Bit 6 - Peripheral increment mode

pub fn circ(&mut self) -> CIRC_W<'_>

Bit 5 - Circular mode

pub fn dir(&mut self) -> DIR_W<'_>

Bit 4 - Data transfer direction

pub fn teie(&mut self) -> TEIE_W<'_>

Bit 3 - Transfer error interrupt enable

pub fn htie(&mut self) -> HTIE_W<'_>

Bit 2 - Half transfer interrupt enable

pub fn tcie(&mut self) -> TCIE_W<'_>

Bit 1 - Transfer complete interrupt enable

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - Channel enable

impl W<u32, Reg<u32, _CNDTR7>>

pub fn ndt(&mut self) -> NDT_W<'_>

Bits 0:15 - Number of data to transfer

impl W<u32, Reg<u32, _CPAR7>>

pub fn pa(&mut self) -> PA_W<'_>

Bits 0:31 - Peripheral address

impl W<u32, Reg<u32, _CMAR7>>

pub fn ma(&mut self) -> MA_W<'_>

Bits 0:31 - Memory address

impl W<u32, Reg<u32, _IFCR>>

pub fn cteif7(&mut self) -> CTEIF7_W<'_>

Bit 27 - Channel x transfer error clear (x = 1 ..7)

pub fn chtif7(&mut self) -> CHTIF7_W<'_>

Bit 26 - Channel x half transfer clear (x = 1 ..7)

pub fn ctcif7(&mut self) -> CTCIF7_W<'_>

Bit 25 - Channel x transfer complete clear (x = 1 ..7)

pub fn cgif7(&mut self) -> CGIF7_W<'_>

Bit 24 - Channel x global interrupt clear (x = 1 ..7)

pub fn cteif6(&mut self) -> CTEIF6_W<'_>

Bit 23 - Channel x transfer error clear (x = 1 ..7)

pub fn chtif6(&mut self) -> CHTIF6_W<'_>

Bit 22 - Channel x half transfer clear (x = 1 ..7)

pub fn ctcif6(&mut self) -> CTCIF6_W<'_>

Bit 21 - Channel x transfer complete clear (x = 1 ..7)

pub fn cgif6(&mut self) -> CGIF6_W<'_>

Bit 20 - Channel x global interrupt clear (x = 1 ..7)

pub fn cteif5(&mut self) -> CTEIF5_W<'_>

Bit 19 - Channel x transfer error clear (x = 1 ..7)

pub fn chtif5(&mut self) -> CHTIF5_W<'_>

Bit 18 - Channel x half transfer clear (x = 1 ..7)

pub fn ctcif5(&mut self) -> CTCIF5_W<'_>

Bit 17 - Channel x transfer complete clear (x = 1 ..7)

pub fn cgif5(&mut self) -> CGIF5_W<'_>

Bit 16 - Channel x global interrupt clear (x = 1 ..7)

pub fn cteif4(&mut self) -> CTEIF4_W<'_>

Bit 15 - Channel x transfer error clear (x = 1 ..7)

pub fn chtif4(&mut self) -> CHTIF4_W<'_>

Bit 14 - Channel x half transfer clear (x = 1 ..7)

pub fn ctcif4(&mut self) -> CTCIF4_W<'_>

Bit 13 - Channel x transfer complete clear (x = 1 ..7)

pub fn cgif4(&mut self) -> CGIF4_W<'_>

Bit 12 - Channel x global interrupt clear (x = 1 ..7)

pub fn cteif3(&mut self) -> CTEIF3_W<'_>

Bit 11 - Channel x transfer error clear (x = 1 ..7)

pub fn chtif3(&mut self) -> CHTIF3_W<'_>

Bit 10 - Channel x half transfer clear (x = 1 ..7)

pub fn ctcif3(&mut self) -> CTCIF3_W<'_>

Bit 9 - Channel x transfer complete clear (x = 1 ..7)

pub fn cgif3(&mut self) -> CGIF3_W<'_>

Bit 8 - Channel x global interrupt clear (x = 1 ..7)

pub fn cteif2(&mut self) -> CTEIF2_W<'_>

Bit 7 - Channel x transfer error clear (x = 1 ..7)

pub fn chtif2(&mut self) -> CHTIF2_W<'_>

Bit 6 - Channel x half transfer clear (x = 1 ..7)

pub fn ctcif2(&mut self) -> CTCIF2_W<'_>

Bit 5 - Channel x transfer complete clear (x = 1 ..7)

pub fn cgif2(&mut self) -> CGIF2_W<'_>

Bit 4 - Channel x global interrupt clear (x = 1 ..7)

pub fn cteif1(&mut self) -> CTEIF1_W<'_>

Bit 3 - Channel x transfer error clear (x = 1 ..7)

pub fn chtif1(&mut self) -> CHTIF1_W<'_>

Bit 2 - Channel x half transfer clear (x = 1 ..7)

pub fn ctcif1(&mut self) -> CTCIF1_W<'_>

Bit 1 - Channel x transfer complete clear (x = 1 ..7)

pub fn cgif1(&mut self) -> CGIF1_W<'_>

Bit 0 - Channel x global interrupt clear (x = 1 ..7)

impl W<u32, Reg<u32, _CCR1>>

pub fn mem2mem(&mut self) -> MEM2MEM_W<'_>

Bit 14 - Memory to memory mode

pub fn pl(&mut self) -> PL_W<'_>

Bits 12:13 - Channel priority level

pub fn msize(&mut self) -> MSIZE_W<'_>

Bits 10:11 - Memory size

pub fn psize(&mut self) -> PSIZE_W<'_>

Bits 8:9 - Peripheral size

pub fn minc(&mut self) -> MINC_W<'_>

Bit 7 - Memory increment mode

pub fn pinc(&mut self) -> PINC_W<'_>

Bit 6 - Peripheral increment mode

pub fn circ(&mut self) -> CIRC_W<'_>

Bit 5 - Circular mode

pub fn dir(&mut self) -> DIR_W<'_>

Bit 4 - Data transfer direction

pub fn teie(&mut self) -> TEIE_W<'_>

Bit 3 - Transfer error interrupt enable

pub fn htie(&mut self) -> HTIE_W<'_>

Bit 2 - Half transfer interrupt enable

pub fn tcie(&mut self) -> TCIE_W<'_>

Bit 1 - Transfer complete interrupt enable

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - Channel enable

impl W<u32, Reg<u32, _CNDTR1>>

pub fn ndt(&mut self) -> NDT_W<'_>

Bits 0:15 - Number of data to transfer

impl W<u32, Reg<u32, _CPAR1>>

pub fn pa(&mut self) -> PA_W<'_>

Bits 0:31 - Peripheral address

impl W<u32, Reg<u32, _CMAR1>>

pub fn ma(&mut self) -> MA_W<'_>

Bits 0:31 - Memory address

impl W<u32, Reg<u32, _CCR2>>

pub fn mem2mem(&mut self) -> MEM2MEM_W<'_>

Bit 14 - Memory to memory mode

pub fn pl(&mut self) -> PL_W<'_>

Bits 12:13 - Channel priority level

pub fn msize(&mut self) -> MSIZE_W<'_>

Bits 10:11 - Memory size

pub fn psize(&mut self) -> PSIZE_W<'_>

Bits 8:9 - Peripheral size

pub fn minc(&mut self) -> MINC_W<'_>

Bit 7 - Memory increment mode

pub fn pinc(&mut self) -> PINC_W<'_>

Bit 6 - Peripheral increment mode

pub fn circ(&mut self) -> CIRC_W<'_>

Bit 5 - Circular mode

pub fn dir(&mut self) -> DIR_W<'_>

Bit 4 - Data transfer direction

pub fn teie(&mut self) -> TEIE_W<'_>

Bit 3 - Transfer error interrupt enable

pub fn htie(&mut self) -> HTIE_W<'_>

Bit 2 - Half transfer interrupt enable

pub fn tcie(&mut self) -> TCIE_W<'_>

Bit 1 - Transfer complete interrupt enable

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - Channel enable

impl W<u32, Reg<u32, _CNDTR2>>

pub fn ndt(&mut self) -> NDT_W<'_>

Bits 0:15 - Number of data to transfer

impl W<u32, Reg<u32, _CPAR2>>

pub fn pa(&mut self) -> PA_W<'_>

Bits 0:31 - Peripheral address

impl W<u32, Reg<u32, _CMAR2>>

pub fn ma(&mut self) -> MA_W<'_>

Bits 0:31 - Memory address

impl W<u32, Reg<u32, _CCR3>>

pub fn mem2mem(&mut self) -> MEM2MEM_W<'_>

Bit 14 - Memory to memory mode

pub fn pl(&mut self) -> PL_W<'_>

Bits 12:13 - Channel priority level

pub fn msize(&mut self) -> MSIZE_W<'_>

Bits 10:11 - Memory size

pub fn psize(&mut self) -> PSIZE_W<'_>

Bits 8:9 - Peripheral size

pub fn minc(&mut self) -> MINC_W<'_>

Bit 7 - Memory increment mode

pub fn pinc(&mut self) -> PINC_W<'_>

Bit 6 - Peripheral increment mode

pub fn circ(&mut self) -> CIRC_W<'_>

Bit 5 - Circular mode

pub fn dir(&mut self) -> DIR_W<'_>

Bit 4 - Data transfer direction

pub fn teie(&mut self) -> TEIE_W<'_>

Bit 3 - Transfer error interrupt enable

pub fn htie(&mut self) -> HTIE_W<'_>

Bit 2 - Half transfer interrupt enable

pub fn tcie(&mut self) -> TCIE_W<'_>

Bit 1 - Transfer complete interrupt enable

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - Channel enable

impl W<u32, Reg<u32, _CNDTR3>>

pub fn ndt(&mut self) -> NDT_W<'_>

Bits 0:15 - Number of data to transfer

impl W<u32, Reg<u32, _CPAR3>>

pub fn pa(&mut self) -> PA_W<'_>

Bits 0:31 - Peripheral address

impl W<u32, Reg<u32, _CMAR3>>

pub fn ma(&mut self) -> MA_W<'_>

Bits 0:31 - Memory address

impl W<u32, Reg<u32, _CCR4>>

pub fn mem2mem(&mut self) -> MEM2MEM_W<'_>

Bit 14 - Memory to memory mode

pub fn pl(&mut self) -> PL_W<'_>

Bits 12:13 - Channel priority level

pub fn msize(&mut self) -> MSIZE_W<'_>

Bits 10:11 - Memory size

pub fn psize(&mut self) -> PSIZE_W<'_>

Bits 8:9 - Peripheral size

pub fn minc(&mut self) -> MINC_W<'_>

Bit 7 - Memory increment mode

pub fn pinc(&mut self) -> PINC_W<'_>

Bit 6 - Peripheral increment mode

pub fn circ(&mut self) -> CIRC_W<'_>

Bit 5 - Circular mode

pub fn dir(&mut self) -> DIR_W<'_>

Bit 4 - Data transfer direction

pub fn teie(&mut self) -> TEIE_W<'_>

Bit 3 - Transfer error interrupt enable

pub fn htie(&mut self) -> HTIE_W<'_>

Bit 2 - Half transfer interrupt enable

pub fn tcie(&mut self) -> TCIE_W<'_>

Bit 1 - Transfer complete interrupt enable

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - Channel enable

impl W<u32, Reg<u32, _CNDTR4>>

pub fn ndt(&mut self) -> NDT_W<'_>

Bits 0:15 - Number of data to transfer

impl W<u32, Reg<u32, _CPAR4>>

pub fn pa(&mut self) -> PA_W<'_>

Bits 0:31 - Peripheral address

impl W<u32, Reg<u32, _CMAR4>>

pub fn ma(&mut self) -> MA_W<'_>

Bits 0:31 - Memory address

impl W<u32, Reg<u32, _CCR5>>

pub fn mem2mem(&mut self) -> MEM2MEM_W<'_>

Bit 14 - Memory to memory mode

pub fn pl(&mut self) -> PL_W<'_>

Bits 12:13 - Channel priority level

pub fn msize(&mut self) -> MSIZE_W<'_>

Bits 10:11 - Memory size

pub fn psize(&mut self) -> PSIZE_W<'_>

Bits 8:9 - Peripheral size

pub fn minc(&mut self) -> MINC_W<'_>

Bit 7 - Memory increment mode

pub fn pinc(&mut self) -> PINC_W<'_>

Bit 6 - Peripheral increment mode

pub fn circ(&mut self) -> CIRC_W<'_>

Bit 5 - Circular mode

pub fn dir(&mut self) -> DIR_W<'_>

Bit 4 - Data transfer direction

pub fn teie(&mut self) -> TEIE_W<'_>

Bit 3 - Transfer error interrupt enable

pub fn htie(&mut self) -> HTIE_W<'_>

Bit 2 - Half transfer interrupt enable

pub fn tcie(&mut self) -> TCIE_W<'_>

Bit 1 - Transfer complete interrupt enable

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - Channel enable

impl W<u32, Reg<u32, _CNDTR5>>

pub fn ndt(&mut self) -> NDT_W<'_>

Bits 0:15 - Number of data to transfer

impl W<u32, Reg<u32, _CPAR5>>

pub fn pa(&mut self) -> PA_W<'_>

Bits 0:31 - Peripheral address

impl W<u32, Reg<u32, _CMAR5>>

pub fn ma(&mut self) -> MA_W<'_>

Bits 0:31 - Memory address

impl W<u32, Reg<u32, _CCR6>>

pub fn mem2mem(&mut self) -> MEM2MEM_W<'_>

Bit 14 - Memory to memory mode

pub fn pl(&mut self) -> PL_W<'_>

Bits 12:13 - Channel priority level

pub fn msize(&mut self) -> MSIZE_W<'_>

Bits 10:11 - Memory size

pub fn psize(&mut self) -> PSIZE_W<'_>

Bits 8:9 - Peripheral size

pub fn minc(&mut self) -> MINC_W<'_>

Bit 7 - Memory increment mode

pub fn pinc(&mut self) -> PINC_W<'_>

Bit 6 - Peripheral increment mode

pub fn circ(&mut self) -> CIRC_W<'_>

Bit 5 - Circular mode

pub fn dir(&mut self) -> DIR_W<'_>

Bit 4 - Data transfer direction

pub fn teie(&mut self) -> TEIE_W<'_>

Bit 3 - Transfer error interrupt enable

pub fn htie(&mut self) -> HTIE_W<'_>

Bit 2 - Half transfer interrupt enable

pub fn tcie(&mut self) -> TCIE_W<'_>

Bit 1 - Transfer complete interrupt enable

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - Channel enable

impl W<u32, Reg<u32, _CNDTR6>>

pub fn ndt(&mut self) -> NDT_W<'_>

Bits 0:15 - Number of data to transfer

impl W<u32, Reg<u32, _CPAR6>>

pub fn pa(&mut self) -> PA_W<'_>

Bits 0:31 - Peripheral address

impl W<u32, Reg<u32, _CMAR6>>

pub fn ma(&mut self) -> MA_W<'_>

Bits 0:31 - Memory address

impl W<u32, Reg<u32, _CCR7>>

pub fn mem2mem(&mut self) -> MEM2MEM_W<'_>

Bit 14 - Memory to memory mode

pub fn pl(&mut self) -> PL_W<'_>

Bits 12:13 - Channel priority level

pub fn msize(&mut self) -> MSIZE_W<'_>

Bits 10:11 - Memory size

pub fn psize(&mut self) -> PSIZE_W<'_>

Bits 8:9 - Peripheral size

pub fn minc(&mut self) -> MINC_W<'_>

Bit 7 - Memory increment mode

pub fn pinc(&mut self) -> PINC_W<'_>

Bit 6 - Peripheral increment mode

pub fn circ(&mut self) -> CIRC_W<'_>

Bit 5 - Circular mode

pub fn dir(&mut self) -> DIR_W<'_>

Bit 4 - Data transfer direction

pub fn teie(&mut self) -> TEIE_W<'_>

Bit 3 - Transfer error interrupt enable

pub fn htie(&mut self) -> HTIE_W<'_>

Bit 2 - Half transfer interrupt enable

pub fn tcie(&mut self) -> TCIE_W<'_>

Bit 1 - Transfer complete interrupt enable

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - Channel enable

impl W<u32, Reg<u32, _CNDTR7>>

pub fn ndt(&mut self) -> NDT_W<'_>

Bits 0:15 - Number of data to transfer

impl W<u32, Reg<u32, _CPAR7>>

pub fn pa(&mut self) -> PA_W<'_>

Bits 0:31 - Peripheral address

impl W<u32, Reg<u32, _CMAR7>>

pub fn ma(&mut self) -> MA_W<'_>

Bits 0:31 - Memory address

impl W<u32, Reg<u32, _CSELR>>

pub fn c7s(&mut self) -> C7S_W<'_>

Bits 24:27 - DMA channel 7 selection

pub fn c6s(&mut self) -> C6S_W<'_>

Bits 20:23 - DMA channel 6 selection

pub fn c5s(&mut self) -> C5S_W<'_>

Bits 16:19 - DMA channel 5 selection

pub fn c4s(&mut self) -> C4S_W<'_>

Bits 12:15 - DMA channel 4 selection

pub fn c3s(&mut self) -> C3S_W<'_>

Bits 8:11 - DMA channel 3 selection

pub fn c2s(&mut self) -> C2S_W<'_>

Bits 4:7 - DMA channel 2 selection

pub fn c1s(&mut self) -> C1S_W<'_>

Bits 0:3 - DMA channel 1 selection

impl W<u32, Reg<u32, _C0CR>>

pub fn sync_id(&mut self) -> SYNC_ID_W<'_>

Bits 24:28 - SYNC_ID

pub fn nbreq(&mut self) -> NBREQ_W<'_>

Bits 19:23 - Nb request

pub fn spol(&mut self) -> SPOL_W<'_>

Bits 17:18 - Sync polarity

pub fn se(&mut self) -> SE_W<'_>

Bit 16 - Synchronization enable

pub fn ege(&mut self) -> EGE_W<'_>

Bit 9 - Event Generation Enable

pub fn soie(&mut self) -> SOIE_W<'_>

Bit 8 - Synchronization Overrun Interrupt Enable

pub fn dmareq_id(&mut self) -> DMAREQ_ID_W<'_>

Bits 0:7 - DMA Request ID

impl W<u32, Reg<u32, _C1CR>>

pub fn sync_id(&mut self) -> SYNC_ID_W<'_>

Bits 24:28 - SYNC_ID

pub fn nbreq(&mut self) -> NBREQ_W<'_>

Bits 19:23 - Nb request

pub fn spol(&mut self) -> SPOL_W<'_>

Bits 17:18 - Sync polarity

pub fn se(&mut self) -> SE_W<'_>

Bit 16 - Synchronization enable

pub fn ege(&mut self) -> EGE_W<'_>

Bit 9 - Event Generation Enable

pub fn soie(&mut self) -> SOIE_W<'_>

Bit 8 - Synchronization Overrun Interrupt Enable

pub fn dmareq_id(&mut self) -> DMAREQ_ID_W<'_>

Bits 0:7 - DMA Request ID

impl W<u32, Reg<u32, _C2CR>>

pub fn sync_id(&mut self) -> SYNC_ID_W<'_>

Bits 24:28 - SYNC_ID

pub fn nbreq(&mut self) -> NBREQ_W<'_>

Bits 19:23 - Nb request

pub fn spol(&mut self) -> SPOL_W<'_>

Bits 17:18 - Sync polarity

pub fn se(&mut self) -> SE_W<'_>

Bit 16 - Synchronization enable

pub fn ege(&mut self) -> EGE_W<'_>

Bit 9 - Event Generation Enable

pub fn soie(&mut self) -> SOIE_W<'_>

Bit 8 - Synchronization Overrun Interrupt Enable

pub fn dmareq_id(&mut self) -> DMAREQ_ID_W<'_>

Bits 0:7 - DMA Request ID

impl W<u32, Reg<u32, _C3CR>>

pub fn sync_id(&mut self) -> SYNC_ID_W<'_>

Bits 24:28 - SYNC_ID

pub fn nbreq(&mut self) -> NBREQ_W<'_>

Bits 19:23 - Nb request

pub fn spol(&mut self) -> SPOL_W<'_>

Bits 17:18 - Sync polarity

pub fn se(&mut self) -> SE_W<'_>

Bit 16 - Synchronization enable

pub fn ege(&mut self) -> EGE_W<'_>

Bit 9 - Event Generation Enable

pub fn soie(&mut self) -> SOIE_W<'_>

Bit 8 - Synchronization Overrun Interrupt Enable

pub fn dmareq_id(&mut self) -> DMAREQ_ID_W<'_>

Bits 0:7 - DMA Request ID

impl W<u32, Reg<u32, _C4CR>>

pub fn sync_id(&mut self) -> SYNC_ID_W<'_>

Bits 24:28 - SYNC_ID

pub fn nbreq(&mut self) -> NBREQ_W<'_>

Bits 19:23 - Nb request

pub fn spol(&mut self) -> SPOL_W<'_>

Bits 17:18 - Sync polarity

pub fn se(&mut self) -> SE_W<'_>

Bit 16 - Synchronization enable

pub fn ege(&mut self) -> EGE_W<'_>

Bit 9 - Event Generation Enable

pub fn soie(&mut self) -> SOIE_W<'_>

Bit 8 - Synchronization Overrun Interrupt Enable

pub fn dmareq_id(&mut self) -> DMAREQ_ID_W<'_>

Bits 0:7 - DMA Request ID

impl W<u32, Reg<u32, _C5CR>>

pub fn sync_id(&mut self) -> SYNC_ID_W<'_>

Bits 24:28 - SYNC_ID

pub fn nbreq(&mut self) -> NBREQ_W<'_>

Bits 19:23 - Nb request

pub fn spol(&mut self) -> SPOL_W<'_>

Bits 17:18 - Sync polarity

pub fn se(&mut self) -> SE_W<'_>

Bit 16 - Synchronization enable

pub fn ege(&mut self) -> EGE_W<'_>

Bit 9 - Event Generation Enable

pub fn soie(&mut self) -> SOIE_W<'_>

Bit 8 - Synchronization Overrun Interrupt Enable

pub fn dmareq_id(&mut self) -> DMAREQ_ID_W<'_>

Bits 0:7 - DMA Request ID

impl W<u32, Reg<u32, _C6CR>>

pub fn sync_id(&mut self) -> SYNC_ID_W<'_>

Bits 24:28 - SYNC_ID

pub fn nbreq(&mut self) -> NBREQ_W<'_>

Bits 19:23 - Nb request

pub fn spol(&mut self) -> SPOL_W<'_>

Bits 17:18 - Sync polarity

pub fn se(&mut self) -> SE_W<'_>

Bit 16 - Synchronization enable

pub fn ege(&mut self) -> EGE_W<'_>

Bit 9 - Event Generation Enable

pub fn soie(&mut self) -> SOIE_W<'_>

Bit 8 - Synchronization Overrun Interrupt Enable

pub fn dmareq_id(&mut self) -> DMAREQ_ID_W<'_>

Bits 0:7 - DMA Request ID

impl W<u32, Reg<u32, _C7CR>>

pub fn sync_id(&mut self) -> SYNC_ID_W<'_>

Bits 24:28 - SYNC_ID

pub fn nbreq(&mut self) -> NBREQ_W<'_>

Bits 19:23 - Nb request

pub fn spol(&mut self) -> SPOL_W<'_>

Bits 17:18 - Sync polarity

pub fn se(&mut self) -> SE_W<'_>

Bit 16 - Synchronization enable

pub fn ege(&mut self) -> EGE_W<'_>

Bit 9 - Event Generation Enable

pub fn soie(&mut self) -> SOIE_W<'_>

Bit 8 - Synchronization Overrun Interrupt Enable

pub fn dmareq_id(&mut self) -> DMAREQ_ID_W<'_>

Bits 0:7 - DMA Request ID

impl W<u32, Reg<u32, _C8CR>>

pub fn sync_id(&mut self) -> SYNC_ID_W<'_>

Bits 24:28 - SYNC_ID

pub fn nbreq(&mut self) -> NBREQ_W<'_>

Bits 19:23 - Nb request

pub fn spol(&mut self) -> SPOL_W<'_>

Bits 17:18 - Sync polarity

pub fn se(&mut self) -> SE_W<'_>

Bit 16 - Synchronization enable

pub fn ege(&mut self) -> EGE_W<'_>

Bit 9 - Event Generation Enable

pub fn soie(&mut self) -> SOIE_W<'_>

Bit 8 - Synchronization Overrun Interrupt Enable

pub fn dmareq_id(&mut self) -> DMAREQ_ID_W<'_>

Bits 0:7 - DMA Request ID

impl W<u32, Reg<u32, _C9CR>>

pub fn sync_id(&mut self) -> SYNC_ID_W<'_>

Bits 24:28 - SYNC_ID

pub fn nbreq(&mut self) -> NBREQ_W<'_>

Bits 19:23 - Nb request

pub fn spol(&mut self) -> SPOL_W<'_>

Bits 17:18 - Sync polarity

pub fn se(&mut self) -> SE_W<'_>

Bit 16 - Synchronization enable

pub fn ege(&mut self) -> EGE_W<'_>

Bit 9 - Event Generation Enable

pub fn soie(&mut self) -> SOIE_W<'_>

Bit 8 - Synchronization Overrun Interrupt Enable

pub fn dmareq_id(&mut self) -> DMAREQ_ID_W<'_>

Bits 0:7 - DMA Request ID

impl W<u32, Reg<u32, _C10CR>>

pub fn sync_id(&mut self) -> SYNC_ID_W<'_>

Bits 24:28 - SYNC_ID

pub fn nbreq(&mut self) -> NBREQ_W<'_>

Bits 19:23 - Nb request

pub fn spol(&mut self) -> SPOL_W<'_>

Bits 17:18 - Sync polarity

pub fn se(&mut self) -> SE_W<'_>

Bit 16 - Synchronization enable

pub fn ege(&mut self) -> EGE_W<'_>

Bit 9 - Event Generation Enable

pub fn soie(&mut self) -> SOIE_W<'_>

Bit 8 - Synchronization Overrun Interrupt Enable

pub fn dmareq_id(&mut self) -> DMAREQ_ID_W<'_>

Bits 0:7 - DMA Request ID

impl W<u32, Reg<u32, _C11CR>>

pub fn sync_id(&mut self) -> SYNC_ID_W<'_>

Bits 24:28 - SYNC_ID

pub fn nbreq(&mut self) -> NBREQ_W<'_>

Bits 19:23 - Nb request

pub fn spol(&mut self) -> SPOL_W<'_>

Bits 17:18 - Sync polarity

pub fn se(&mut self) -> SE_W<'_>

Bit 16 - Synchronization enable

pub fn ege(&mut self) -> EGE_W<'_>

Bit 9 - Event Generation Enable

pub fn soie(&mut self) -> SOIE_W<'_>

Bit 8 - Synchronization Overrun Interrupt Enable

pub fn dmareq_id(&mut self) -> DMAREQ_ID_W<'_>

Bits 0:7 - DMA Request ID

impl W<u32, Reg<u32, _C12CR>>

pub fn sync_id(&mut self) -> SYNC_ID_W<'_>

Bits 24:28 - SYNC_ID

pub fn nbreq(&mut self) -> NBREQ_W<'_>

Bits 19:23 - Nb request

pub fn spol(&mut self) -> SPOL_W<'_>

Bits 17:18 - Sync polarity

pub fn se(&mut self) -> SE_W<'_>

Bit 16 - Synchronization enable

pub fn ege(&mut self) -> EGE_W<'_>

Bit 9 - Event Generation Enable

pub fn soie(&mut self) -> SOIE_W<'_>

Bit 8 - Synchronization Overrun Interrupt Enable

pub fn dmareq_id(&mut self) -> DMAREQ_ID_W<'_>

Bits 0:7 - DMA Request ID

impl W<u32, Reg<u32, _C13CR>>

pub fn sync_id(&mut self) -> SYNC_ID_W<'_>

Bits 24:28 - SYNC_ID

pub fn nbreq(&mut self) -> NBREQ_W<'_>

Bits 19:23 - Nb request

pub fn spol(&mut self) -> SPOL_W<'_>

Bits 17:18 - Sync polarity

pub fn se(&mut self) -> SE_W<'_>

Bit 16 - Synchronization enable

pub fn ege(&mut self) -> EGE_W<'_>

Bit 9 - Event Generation Enable

pub fn soie(&mut self) -> SOIE_W<'_>

Bit 8 - Synchronization Overrun Interrupt Enable

pub fn dmareq_id(&mut self) -> DMAREQ_ID_W<'_>

Bits 0:7 - DMA Request ID

impl W<u32, Reg<u32, _CFR>>

pub fn csof0(&mut self) -> CSOF0_W<'_>

Bit 0 - Synchronization Clear Overrun Flag 0

pub fn csof1(&mut self) -> CSOF1_W<'_>

Bit 1 - Synchronization Clear Overrun Flag 1

pub fn csof2(&mut self) -> CSOF2_W<'_>

Bit 2 - Synchronization Clear Overrun Flag 2

pub fn csof3(&mut self) -> CSOF3_W<'_>

Bit 3 - Synchronization Clear Overrun Flag 3

pub fn csof4(&mut self) -> CSOF4_W<'_>

Bit 4 - Synchronization Clear Overrun Flag 4

pub fn csof5(&mut self) -> CSOF5_W<'_>

Bit 5 - Synchronization Clear Overrun Flag 5

pub fn csof6(&mut self) -> CSOF6_W<'_>

Bit 6 - Synchronization Clear Overrun Flag 6

pub fn csof7(&mut self) -> CSOF7_W<'_>

Bit 7 - Synchronization Clear Overrun Flag 7

pub fn csof8(&mut self) -> CSOF8_W<'_>

Bit 8 - Synchronization Clear Overrun Flag 8

pub fn csof9(&mut self) -> CSOF9_W<'_>

Bit 9 - Synchronization Clear Overrun Flag 9

pub fn csof10(&mut self) -> CSOF10_W<'_>

Bit 10 - Synchronization Clear Overrun Flag 10

pub fn csof11(&mut self) -> CSOF11_W<'_>

Bit 11 - Synchronization Clear Overrun Flag 11

pub fn csof12(&mut self) -> CSOF12_W<'_>

Bit 12 - Synchronization Clear Overrun Flag 12

pub fn csof13(&mut self) -> CSOF13_W<'_>

Bit 13 - Synchronization Clear Overrun Flag 13

impl W<u32, Reg<u32, _RG0CR>>

pub fn gnbreq(&mut self) -> GNBREQ_W<'_>

Bits 19:23 - Number of Request

pub fn gpol(&mut self) -> GPOL_W<'_>

Bits 17:18 - Generation Polarity

pub fn ge(&mut self) -> GE_W<'_>

Bit 16 - Generation Enable

pub fn oie(&mut self) -> OIE_W<'_>

Bit 8 - Overrun Interrupt Enable

pub fn sig_id(&mut self) -> SIG_ID_W<'_>

Bits 0:4 - Signal ID

impl W<u32, Reg<u32, _RG1CR>>

pub fn gnbreq(&mut self) -> GNBREQ_W<'_>

Bits 19:23 - Number of Request

pub fn gpol(&mut self) -> GPOL_W<'_>

Bits 17:18 - Generation Polarity

pub fn ge(&mut self) -> GE_W<'_>

Bit 16 - Generation Enable

pub fn oie(&mut self) -> OIE_W<'_>

Bit 8 - Overrun Interrupt Enable

pub fn sig_id(&mut self) -> SIG_ID_W<'_>

Bits 0:4 - Signal ID

impl W<u32, Reg<u32, _RG2CR>>

pub fn gnbreq(&mut self) -> GNBREQ_W<'_>

Bits 19:23 - Number of Request

pub fn gpol(&mut self) -> GPOL_W<'_>

Bits 17:18 - Generation Polarity

pub fn ge(&mut self) -> GE_W<'_>

Bit 16 - Generation Enable

pub fn oie(&mut self) -> OIE_W<'_>

Bit 8 - Overrun Interrupt Enable

pub fn sig_id(&mut self) -> SIG_ID_W<'_>

Bits 0:4 - Signal ID

impl W<u32, Reg<u32, _RG3CR>>

pub fn gnbreq(&mut self) -> GNBREQ_W<'_>

Bits 19:23 - Number of Request

pub fn gpol(&mut self) -> GPOL_W<'_>

Bits 17:18 - Generation Polarity

pub fn ge(&mut self) -> GE_W<'_>

Bit 16 - Generation Enable

pub fn oie(&mut self) -> OIE_W<'_>

Bit 8 - Overrun Interrupt Enable

pub fn sig_id(&mut self) -> SIG_ID_W<'_>

Bits 0:4 - Signal ID

impl W<u32, Reg<u32, _DR>>

pub fn dr(&mut self) -> DR_W<'_>

Bits 0:31 - Data register bits

impl W<u32, Reg<u32, _IDR>>

pub fn idr(&mut self) -> IDR_W<'_>

Bits 0:31 - General-purpose 32-bit data register bits

impl W<u32, Reg<u32, _CR>>

pub fn rev_out(&mut self) -> REV_OUT_W<'_>

Bit 7 - Reverse output data

pub fn rev_in(&mut self) -> REV_IN_W<'_>

Bits 5:6 - Reverse input data

pub fn polysize(&mut self) -> POLYSIZE_W<'_>

Bits 3:4 - Polynomial size

pub fn reset(&mut self) -> RESET_W<'_>

Bit 0 - RESET bit

impl W<u32, Reg<u32, _INIT>>

pub fn crc_init(&mut self) -> CRC_INIT_W<'_>

Bits 0:31 - Programmable initial CRC value

impl W<u32, Reg<u32, _POL>>

pub fn pol(&mut self) -> POL_W<'_>

Bits 0:31 - Programmable polynomial

impl W<u32, Reg<u32, _CR>>

pub fn bias(&mut self) -> BIAS_W<'_>

Bits 5:6 - Bias selector

pub fn duty(&mut self) -> DUTY_W<'_>

Bits 2:4 - Duty selection

pub fn vsel(&mut self) -> VSEL_W<'_>

Bit 1 - Voltage source selection

pub fn lcden(&mut self) -> LCDEN_W<'_>

Bit 0 - LCD controller enable

pub fn mux_seg(&mut self) -> MUX_SEG_W<'_>

Bit 7 - Mux segment enable

pub fn bufen(&mut self) -> BUFEN_W<'_>

Bit 8 - Voltage output buffer enable

impl W<u32, Reg<u32, _FCR>>

pub fn ps(&mut self) -> PS_W<'_>

Bits 22:25 - PS 16-bit prescaler

pub fn div(&mut self) -> DIV_W<'_>

Bits 18:21 - DIV clock divider

pub fn blink(&mut self) -> BLINK_W<'_>

Bits 16:17 - Blink mode selection

pub fn blinkf(&mut self) -> BLINKF_W<'_>

Bits 13:15 - Blink frequency selection

pub fn cc(&mut self) -> CC_W<'_>

Bits 10:12 - Contrast control

pub fn dead(&mut self) -> DEAD_W<'_>

Bits 7:9 - Dead time duration

pub fn pon(&mut self) -> PON_W<'_>

Bits 4:6 - Pulse ON duration

pub fn uddie(&mut self) -> UDDIE_W<'_>

Bit 3 - Update display done interrupt enable

pub fn sofie(&mut self) -> SOFIE_W<'_>

Bit 1 - Start of frame interrupt enable

pub fn hd(&mut self) -> HD_W<'_>

Bit 0 - High drive enable

impl W<u32, Reg<u32, _SR>>

pub fn udr(&mut self) -> UDR_W<'_>

Bit 2 - Update display request

impl W<u32, Reg<u32, _CLR>>

pub fn uddc(&mut self) -> UDDC_W<'_>

Bit 3 - Update display done clear

pub fn sofc(&mut self) -> SOFC_W<'_>

Bit 1 - Start of frame flag clear

impl W<u32, Reg<u32, _RAM_COM0>>

pub fn s31(&mut self) -> S31_W<'_>

Bit 31 - S31

pub fn s30(&mut self) -> S30_W<'_>

Bit 30 - S30

pub fn s29(&mut self) -> S29_W<'_>

Bit 29 - S29

pub fn s28(&mut self) -> S28_W<'_>

Bit 28 - S28

pub fn s27(&mut self) -> S27_W<'_>

Bit 27 - S27

pub fn s26(&mut self) -> S26_W<'_>

Bit 26 - S26

pub fn s25(&mut self) -> S25_W<'_>

Bit 25 - S25

pub fn s24(&mut self) -> S24_W<'_>

Bit 24 - S24

pub fn s23(&mut self) -> S23_W<'_>

Bit 23 - S23

pub fn s22(&mut self) -> S22_W<'_>

Bit 22 - S22

pub fn s21(&mut self) -> S21_W<'_>

Bit 21 - S21

pub fn s20(&mut self) -> S20_W<'_>

Bit 20 - S20

pub fn s19(&mut self) -> S19_W<'_>

Bit 19 - S19

pub fn s18(&mut self) -> S18_W<'_>

Bit 18 - S18

pub fn s17(&mut self) -> S17_W<'_>

Bit 17 - S17

pub fn s16(&mut self) -> S16_W<'_>

Bit 16 - S16

pub fn s15(&mut self) -> S15_W<'_>

Bit 15 - S15

pub fn s14(&mut self) -> S14_W<'_>

Bit 14 - S14

pub fn s13(&mut self) -> S13_W<'_>

Bit 13 - S13

pub fn s12(&mut self) -> S12_W<'_>

Bit 12 - S12

pub fn s11(&mut self) -> S11_W<'_>

Bit 11 - S11

pub fn s10(&mut self) -> S10_W<'_>

Bit 10 - S10

pub fn s09(&mut self) -> S09_W<'_>

Bit 9 - S09

pub fn s08(&mut self) -> S08_W<'_>

Bit 8 - S08

pub fn s07(&mut self) -> S07_W<'_>

Bit 7 - S07

pub fn s06(&mut self) -> S06_W<'_>

Bit 6 - S06

pub fn s05(&mut self) -> S05_W<'_>

Bit 5 - S05

pub fn s04(&mut self) -> S04_W<'_>

Bit 4 - S04

pub fn s03(&mut self) -> S03_W<'_>

Bit 3 - S03

pub fn s02(&mut self) -> S02_W<'_>

Bit 2 - S02

pub fn s01(&mut self) -> S01_W<'_>

Bit 1 - S01

pub fn s00(&mut self) -> S00_W<'_>

Bit 0 - S00

impl W<u32, Reg<u32, _RAM_COM1>>

pub fn s31(&mut self) -> S31_W<'_>

Bit 31 - S31

pub fn s30(&mut self) -> S30_W<'_>

Bit 30 - S30

pub fn s29(&mut self) -> S29_W<'_>

Bit 29 - S29

pub fn s28(&mut self) -> S28_W<'_>

Bit 28 - S28

pub fn s27(&mut self) -> S27_W<'_>

Bit 27 - S27

pub fn s26(&mut self) -> S26_W<'_>

Bit 26 - S26

pub fn s25(&mut self) -> S25_W<'_>

Bit 25 - S25

pub fn s24(&mut self) -> S24_W<'_>

Bit 24 - S24

pub fn s23(&mut self) -> S23_W<'_>

Bit 23 - S23

pub fn s22(&mut self) -> S22_W<'_>

Bit 22 - S22

pub fn s21(&mut self) -> S21_W<'_>

Bit 21 - S21

pub fn s20(&mut self) -> S20_W<'_>

Bit 20 - S20

pub fn s19(&mut self) -> S19_W<'_>

Bit 19 - S19

pub fn s18(&mut self) -> S18_W<'_>

Bit 18 - S18

pub fn s17(&mut self) -> S17_W<'_>

Bit 17 - S17

pub fn s16(&mut self) -> S16_W<'_>

Bit 16 - S16

pub fn s15(&mut self) -> S15_W<'_>

Bit 15 - S15

pub fn s14(&mut self) -> S14_W<'_>

Bit 14 - S14

pub fn s13(&mut self) -> S13_W<'_>

Bit 13 - S13

pub fn s12(&mut self) -> S12_W<'_>

Bit 12 - S12

pub fn s11(&mut self) -> S11_W<'_>

Bit 11 - S11

pub fn s10(&mut self) -> S10_W<'_>

Bit 10 - S10

pub fn s09(&mut self) -> S09_W<'_>

Bit 9 - S09

pub fn s08(&mut self) -> S08_W<'_>

Bit 8 - S08

pub fn s07(&mut self) -> S07_W<'_>

Bit 7 - S07

pub fn s06(&mut self) -> S06_W<'_>

Bit 6 - S06

pub fn s05(&mut self) -> S05_W<'_>

Bit 5 - S05

pub fn s04(&mut self) -> S04_W<'_>

Bit 4 - S04

pub fn s03(&mut self) -> S03_W<'_>

Bit 3 - S03

pub fn s02(&mut self) -> S02_W<'_>

Bit 2 - S02

pub fn s01(&mut self) -> S01_W<'_>

Bit 1 - S01

pub fn s00(&mut self) -> S00_W<'_>

Bit 0 - S00

impl W<u32, Reg<u32, _RAM_COM2>>

pub fn s31(&mut self) -> S31_W<'_>

Bit 31 - S31

pub fn s30(&mut self) -> S30_W<'_>

Bit 30 - S30

pub fn s29(&mut self) -> S29_W<'_>

Bit 29 - S29

pub fn s28(&mut self) -> S28_W<'_>

Bit 28 - S28

pub fn s27(&mut self) -> S27_W<'_>

Bit 27 - S27

pub fn s26(&mut self) -> S26_W<'_>

Bit 26 - S26

pub fn s25(&mut self) -> S25_W<'_>

Bit 25 - S25

pub fn s24(&mut self) -> S24_W<'_>

Bit 24 - S24

pub fn s23(&mut self) -> S23_W<'_>

Bit 23 - S23

pub fn s22(&mut self) -> S22_W<'_>

Bit 22 - S22

pub fn s21(&mut self) -> S21_W<'_>

Bit 21 - S21

pub fn s20(&mut self) -> S20_W<'_>

Bit 20 - S20

pub fn s19(&mut self) -> S19_W<'_>

Bit 19 - S19

pub fn s18(&mut self) -> S18_W<'_>

Bit 18 - S18

pub fn s17(&mut self) -> S17_W<'_>

Bit 17 - S17

pub fn s16(&mut self) -> S16_W<'_>

Bit 16 - S16

pub fn s15(&mut self) -> S15_W<'_>

Bit 15 - S15

pub fn s14(&mut self) -> S14_W<'_>

Bit 14 - S14

pub fn s13(&mut self) -> S13_W<'_>

Bit 13 - S13

pub fn s12(&mut self) -> S12_W<'_>

Bit 12 - S12

pub fn s11(&mut self) -> S11_W<'_>

Bit 11 - S11

pub fn s10(&mut self) -> S10_W<'_>

Bit 10 - S10

pub fn s09(&mut self) -> S09_W<'_>

Bit 9 - S09

pub fn s08(&mut self) -> S08_W<'_>

Bit 8 - S08

pub fn s07(&mut self) -> S07_W<'_>

Bit 7 - S07

pub fn s06(&mut self) -> S06_W<'_>

Bit 6 - S06

pub fn s05(&mut self) -> S05_W<'_>

Bit 5 - S05

pub fn s04(&mut self) -> S04_W<'_>

Bit 4 - S04

pub fn s03(&mut self) -> S03_W<'_>

Bit 3 - S03

pub fn s02(&mut self) -> S02_W<'_>

Bit 2 - S02

pub fn s01(&mut self) -> S01_W<'_>

Bit 1 - S01

pub fn s00(&mut self) -> S00_W<'_>

Bit 0 - S00

impl W<u32, Reg<u32, _RAM_COM3>>

pub fn s31(&mut self) -> S31_W<'_>

Bit 31 - S31

pub fn s30(&mut self) -> S30_W<'_>

Bit 30 - S30

pub fn s29(&mut self) -> S29_W<'_>

Bit 29 - S29

pub fn s28(&mut self) -> S28_W<'_>

Bit 28 - S28

pub fn s27(&mut self) -> S27_W<'_>

Bit 27 - S27

pub fn s26(&mut self) -> S26_W<'_>

Bit 26 - S26

pub fn s25(&mut self) -> S25_W<'_>

Bit 25 - S25

pub fn s24(&mut self) -> S24_W<'_>

Bit 24 - S24

pub fn s23(&mut self) -> S23_W<'_>

Bit 23 - S23

pub fn s22(&mut self) -> S22_W<'_>

Bit 22 - S22

pub fn s21(&mut self) -> S21_W<'_>

Bit 21 - S21

pub fn s20(&mut self) -> S20_W<'_>

Bit 20 - S20

pub fn s19(&mut self) -> S19_W<'_>

Bit 19 - S19

pub fn s18(&mut self) -> S18_W<'_>

Bit 18 - S18

pub fn s17(&mut self) -> S17_W<'_>

Bit 17 - S17

pub fn s16(&mut self) -> S16_W<'_>

Bit 16 - S16

pub fn s15(&mut self) -> S15_W<'_>

Bit 15 - S15

pub fn s14(&mut self) -> S14_W<'_>

Bit 14 - S14

pub fn s13(&mut self) -> S13_W<'_>

Bit 13 - S13

pub fn s12(&mut self) -> S12_W<'_>

Bit 12 - S12

pub fn s11(&mut self) -> S11_W<'_>

Bit 11 - S11

pub fn s10(&mut self) -> S10_W<'_>

Bit 10 - S10

pub fn s09(&mut self) -> S09_W<'_>

Bit 9 - S09

pub fn s08(&mut self) -> S08_W<'_>

Bit 8 - S08

pub fn s07(&mut self) -> S07_W<'_>

Bit 7 - S07

pub fn s06(&mut self) -> S06_W<'_>

Bit 6 - S06

pub fn s05(&mut self) -> S05_W<'_>

Bit 5 - S05

pub fn s04(&mut self) -> S04_W<'_>

Bit 4 - S04

pub fn s03(&mut self) -> S03_W<'_>

Bit 3 - S03

pub fn s02(&mut self) -> S02_W<'_>

Bit 2 - S02

pub fn s01(&mut self) -> S01_W<'_>

Bit 1 - S01

pub fn s00(&mut self) -> S00_W<'_>

Bit 0 - S00

impl W<u32, Reg<u32, _RAM_COM4>>

pub fn s31(&mut self) -> S31_W<'_>

Bit 31 - S31

pub fn s30(&mut self) -> S30_W<'_>

Bit 30 - S30

pub fn s29(&mut self) -> S29_W<'_>

Bit 29 - S29

pub fn s28(&mut self) -> S28_W<'_>

Bit 28 - S28

pub fn s27(&mut self) -> S27_W<'_>

Bit 27 - S27

pub fn s26(&mut self) -> S26_W<'_>

Bit 26 - S26

pub fn s25(&mut self) -> S25_W<'_>

Bit 25 - S25

pub fn s24(&mut self) -> S24_W<'_>

Bit 24 - S24

pub fn s23(&mut self) -> S23_W<'_>

Bit 23 - S23

pub fn s22(&mut self) -> S22_W<'_>

Bit 22 - S22

pub fn s21(&mut self) -> S21_W<'_>

Bit 21 - S21

pub fn s20(&mut self) -> S20_W<'_>

Bit 20 - S20

pub fn s19(&mut self) -> S19_W<'_>

Bit 19 - S19

pub fn s18(&mut self) -> S18_W<'_>

Bit 18 - S18

pub fn s17(&mut self) -> S17_W<'_>

Bit 17 - S17

pub fn s16(&mut self) -> S16_W<'_>

Bit 16 - S16

pub fn s15(&mut self) -> S15_W<'_>

Bit 15 - S15

pub fn s14(&mut self) -> S14_W<'_>

Bit 14 - S14

pub fn s13(&mut self) -> S13_W<'_>

Bit 13 - S13

pub fn s12(&mut self) -> S12_W<'_>

Bit 12 - S12

pub fn s11(&mut self) -> S11_W<'_>

Bit 11 - S11

pub fn s10(&mut self) -> S10_W<'_>

Bit 10 - S10

pub fn s09(&mut self) -> S09_W<'_>

Bit 9 - S09

pub fn s08(&mut self) -> S08_W<'_>

Bit 8 - S08

pub fn s07(&mut self) -> S07_W<'_>

Bit 7 - S07

pub fn s06(&mut self) -> S06_W<'_>

Bit 6 - S06

pub fn s05(&mut self) -> S05_W<'_>

Bit 5 - S05

pub fn s04(&mut self) -> S04_W<'_>

Bit 4 - S04

pub fn s03(&mut self) -> S03_W<'_>

Bit 3 - S03

pub fn s02(&mut self) -> S02_W<'_>

Bit 2 - S02

pub fn s01(&mut self) -> S01_W<'_>

Bit 1 - S01

pub fn s00(&mut self) -> S00_W<'_>

Bit 0 - S00

impl W<u32, Reg<u32, _RAM_COM5>>

pub fn s31(&mut self) -> S31_W<'_>

Bit 31 - S31

pub fn s30(&mut self) -> S30_W<'_>

Bit 30 - S30

pub fn s29(&mut self) -> S29_W<'_>

Bit 29 - S29

pub fn s28(&mut self) -> S28_W<'_>

Bit 28 - S28

pub fn s27(&mut self) -> S27_W<'_>

Bit 27 - S27

pub fn s26(&mut self) -> S26_W<'_>

Bit 26 - S26

pub fn s25(&mut self) -> S25_W<'_>

Bit 25 - S25

pub fn s24(&mut self) -> S24_W<'_>

Bit 24 - S24

pub fn s23(&mut self) -> S23_W<'_>

Bit 23 - S23

pub fn s22(&mut self) -> S22_W<'_>

Bit 22 - S22

pub fn s21(&mut self) -> S21_W<'_>

Bit 21 - S21

pub fn s20(&mut self) -> S20_W<'_>

Bit 20 - S20

pub fn s19(&mut self) -> S19_W<'_>

Bit 19 - S19

pub fn s18(&mut self) -> S18_W<'_>

Bit 18 - S18

pub fn s17(&mut self) -> S17_W<'_>

Bit 17 - S17

pub fn s16(&mut self) -> S16_W<'_>

Bit 16 - S16

pub fn s15(&mut self) -> S15_W<'_>

Bit 15 - S15

pub fn s14(&mut self) -> S14_W<'_>

Bit 14 - S14

pub fn s13(&mut self) -> S13_W<'_>

Bit 13 - S13

pub fn s12(&mut self) -> S12_W<'_>

Bit 12 - S12

pub fn s11(&mut self) -> S11_W<'_>

Bit 11 - S11

pub fn s10(&mut self) -> S10_W<'_>

Bit 10 - S10

pub fn s09(&mut self) -> S09_W<'_>

Bit 9 - S09

pub fn s08(&mut self) -> S08_W<'_>

Bit 8 - S08

pub fn s07(&mut self) -> S07_W<'_>

Bit 7 - S07

pub fn s06(&mut self) -> S06_W<'_>

Bit 6 - S06

pub fn s05(&mut self) -> S05_W<'_>

Bit 5 - S05

pub fn s04(&mut self) -> S04_W<'_>

Bit 4 - S04

pub fn s03(&mut self) -> S03_W<'_>

Bit 3 - S03

pub fn s02(&mut self) -> S02_W<'_>

Bit 2 - S02

pub fn s01(&mut self) -> S01_W<'_>

Bit 1 - S01

pub fn s00(&mut self) -> S00_W<'_>

Bit 0 - S00

impl W<u32, Reg<u32, _RAM_COM6>>

pub fn s31(&mut self) -> S31_W<'_>

Bit 31 - S31

pub fn s30(&mut self) -> S30_W<'_>

Bit 30 - S30

pub fn s29(&mut self) -> S29_W<'_>

Bit 29 - S29

pub fn s28(&mut self) -> S28_W<'_>

Bit 28 - S28

pub fn s27(&mut self) -> S27_W<'_>

Bit 27 - S27

pub fn s26(&mut self) -> S26_W<'_>

Bit 26 - S26

pub fn s25(&mut self) -> S25_W<'_>

Bit 25 - S25

pub fn s24(&mut self) -> S24_W<'_>

Bit 24 - S24

pub fn s23(&mut self) -> S23_W<'_>

Bit 23 - S23

pub fn s22(&mut self) -> S22_W<'_>

Bit 22 - S22

pub fn s21(&mut self) -> S21_W<'_>

Bit 21 - S21

pub fn s20(&mut self) -> S20_W<'_>

Bit 20 - S20

pub fn s19(&mut self) -> S19_W<'_>

Bit 19 - S19

pub fn s18(&mut self) -> S18_W<'_>

Bit 18 - S18

pub fn s17(&mut self) -> S17_W<'_>

Bit 17 - S17

pub fn s16(&mut self) -> S16_W<'_>

Bit 16 - S16

pub fn s15(&mut self) -> S15_W<'_>

Bit 15 - S15

pub fn s14(&mut self) -> S14_W<'_>

Bit 14 - S14

pub fn s13(&mut self) -> S13_W<'_>

Bit 13 - S13

pub fn s12(&mut self) -> S12_W<'_>

Bit 12 - S12

pub fn s11(&mut self) -> S11_W<'_>

Bit 11 - S11

pub fn s10(&mut self) -> S10_W<'_>

Bit 10 - S10

pub fn s09(&mut self) -> S09_W<'_>

Bit 9 - S09

pub fn s08(&mut self) -> S08_W<'_>

Bit 8 - S08

pub fn s07(&mut self) -> S07_W<'_>

Bit 7 - S07

pub fn s06(&mut self) -> S06_W<'_>

Bit 6 - S06

pub fn s05(&mut self) -> S05_W<'_>

Bit 5 - S05

pub fn s04(&mut self) -> S04_W<'_>

Bit 4 - S04

pub fn s03(&mut self) -> S03_W<'_>

Bit 3 - S03

pub fn s02(&mut self) -> S02_W<'_>

Bit 2 - S02

pub fn s01(&mut self) -> S01_W<'_>

Bit 1 - S01

pub fn s00(&mut self) -> S00_W<'_>

Bit 0 - S00

impl W<u32, Reg<u32, _RAM_COM7>>

pub fn s31(&mut self) -> S31_W<'_>

Bit 31 - S31

pub fn s30(&mut self) -> S30_W<'_>

Bit 30 - S30

pub fn s29(&mut self) -> S29_W<'_>

Bit 29 - S29

pub fn s28(&mut self) -> S28_W<'_>

Bit 28 - S28

pub fn s27(&mut self) -> S27_W<'_>

Bit 27 - S27

pub fn s26(&mut self) -> S26_W<'_>

Bit 26 - S26

pub fn s25(&mut self) -> S25_W<'_>

Bit 25 - S25

pub fn s24(&mut self) -> S24_W<'_>

Bit 24 - S24

pub fn s23(&mut self) -> S23_W<'_>

Bit 23 - S23

pub fn s22(&mut self) -> S22_W<'_>

Bit 22 - S22

pub fn s21(&mut self) -> S21_W<'_>

Bit 21 - S21

pub fn s20(&mut self) -> S20_W<'_>

Bit 20 - S20

pub fn s19(&mut self) -> S19_W<'_>

Bit 19 - S19

pub fn s18(&mut self) -> S18_W<'_>

Bit 18 - S18

pub fn s17(&mut self) -> S17_W<'_>

Bit 17 - S17

pub fn s16(&mut self) -> S16_W<'_>

Bit 16 - S16

pub fn s15(&mut self) -> S15_W<'_>

Bit 15 - S15

pub fn s14(&mut self) -> S14_W<'_>

Bit 14 - S14

pub fn s13(&mut self) -> S13_W<'_>

Bit 13 - S13

pub fn s12(&mut self) -> S12_W<'_>

Bit 12 - S12

pub fn s11(&mut self) -> S11_W<'_>

Bit 11 - S11

pub fn s10(&mut self) -> S10_W<'_>

Bit 10 - S10

pub fn s09(&mut self) -> S09_W<'_>

Bit 9 - S09

pub fn s08(&mut self) -> S08_W<'_>

Bit 8 - S08

pub fn s07(&mut self) -> S07_W<'_>

Bit 7 - S07

pub fn s06(&mut self) -> S06_W<'_>

Bit 6 - S06

pub fn s05(&mut self) -> S05_W<'_>

Bit 5 - S05

pub fn s04(&mut self) -> S04_W<'_>

Bit 4 - S04

pub fn s03(&mut self) -> S03_W<'_>

Bit 3 - S03

pub fn s02(&mut self) -> S02_W<'_>

Bit 2 - S02

pub fn s01(&mut self) -> S01_W<'_>

Bit 1 - S01

pub fn s00(&mut self) -> S00_W<'_>

Bit 0 - S00

impl W<u32, Reg<u32, _CR>>

pub fn ctph(&mut self) -> CTPH_W<'_>

Bits 28:31 - Charge transfer pulse high

pub fn ctpl(&mut self) -> CTPL_W<'_>

Bits 24:27 - Charge transfer pulse low

pub fn ssd(&mut self) -> SSD_W<'_>

Bits 17:23 - Spread spectrum deviation

pub fn sse(&mut self) -> SSE_W<'_>

Bit 16 - Spread spectrum enable

pub fn sspsc(&mut self) -> SSPSC_W<'_>

Bit 15 - Spread spectrum prescaler

pub fn pgpsc(&mut self) -> PGPSC_W<'_>

Bits 12:14 - pulse generator prescaler

pub fn mcv(&mut self) -> MCV_W<'_>

Bits 5:7 - Max count value

pub fn iodef(&mut self) -> IODEF_W<'_>

Bit 4 - I/O Default mode

pub fn syncpol(&mut self) -> SYNCPOL_W<'_>

Bit 3 - Synchronization pin polarity

pub fn am(&mut self) -> AM_W<'_>

Bit 2 - Acquisition mode

pub fn start(&mut self) -> START_W<'_>

Bit 1 - Start a new acquisition

pub fn tsce(&mut self) -> TSCE_W<'_>

Bit 0 - Touch sensing controller enable

impl W<u32, Reg<u32, _IER>>

pub fn mceie(&mut self) -> MCEIE_W<'_>

Bit 1 - Max count error interrupt enable

pub fn eoaie(&mut self) -> EOAIE_W<'_>

Bit 0 - End of acquisition interrupt enable

impl W<u32, Reg<u32, _ICR>>

pub fn mceic(&mut self) -> MCEIC_W<'_>

Bit 1 - Max count error interrupt clear

pub fn eoaic(&mut self) -> EOAIC_W<'_>

Bit 0 - End of acquisition interrupt clear

impl W<u32, Reg<u32, _ISR>>

pub fn mcef(&mut self) -> MCEF_W<'_>

Bit 1 - Max count error flag

pub fn eoaf(&mut self) -> EOAF_W<'_>

Bit 0 - End of acquisition flag

impl W<u32, Reg<u32, _IOHCR>>

pub fn g7_io4(&mut self) -> G7_IO4_W<'_>

Bit 27 - G7_IO4

pub fn g7_io3(&mut self) -> G7_IO3_W<'_>

Bit 26 - G7_IO3

pub fn g7_io2(&mut self) -> G7_IO2_W<'_>

Bit 25 - G7_IO2

pub fn g7_io1(&mut self) -> G7_IO1_W<'_>

Bit 24 - G7_IO1

pub fn g6_io4(&mut self) -> G6_IO4_W<'_>

Bit 23 - G6_IO4

pub fn g6_io3(&mut self) -> G6_IO3_W<'_>

Bit 22 - G6_IO3

pub fn g6_io2(&mut self) -> G6_IO2_W<'_>

Bit 21 - G6_IO2

pub fn g6_io1(&mut self) -> G6_IO1_W<'_>

Bit 20 - G6_IO1

pub fn g5_io4(&mut self) -> G5_IO4_W<'_>

Bit 19 - G5_IO4

pub fn g5_io3(&mut self) -> G5_IO3_W<'_>

Bit 18 - G5_IO3

pub fn g5_io2(&mut self) -> G5_IO2_W<'_>

Bit 17 - G5_IO2

pub fn g5_io1(&mut self) -> G5_IO1_W<'_>

Bit 16 - G5_IO1

pub fn g4_io4(&mut self) -> G4_IO4_W<'_>

Bit 15 - G4_IO4

pub fn g4_io3(&mut self) -> G4_IO3_W<'_>

Bit 14 - G4_IO3

pub fn g4_io2(&mut self) -> G4_IO2_W<'_>

Bit 13 - G4_IO2

pub fn g4_io1(&mut self) -> G4_IO1_W<'_>

Bit 12 - G4_IO1

pub fn g3_io4(&mut self) -> G3_IO4_W<'_>

Bit 11 - G3_IO4

pub fn g3_io3(&mut self) -> G3_IO3_W<'_>

Bit 10 - G3_IO3

pub fn g3_io2(&mut self) -> G3_IO2_W<'_>

Bit 9 - G3_IO2

pub fn g3_io1(&mut self) -> G3_IO1_W<'_>

Bit 8 - G3_IO1

pub fn g2_io4(&mut self) -> G2_IO4_W<'_>

Bit 7 - G2_IO4

pub fn g2_io3(&mut self) -> G2_IO3_W<'_>

Bit 6 - G2_IO3

pub fn g2_io2(&mut self) -> G2_IO2_W<'_>

Bit 5 - G2_IO2

pub fn g2_io1(&mut self) -> G2_IO1_W<'_>

Bit 4 - G2_IO1

pub fn g1_io4(&mut self) -> G1_IO4_W<'_>

Bit 3 - G1_IO4

pub fn g1_io3(&mut self) -> G1_IO3_W<'_>

Bit 2 - G1_IO3

pub fn g1_io2(&mut self) -> G1_IO2_W<'_>

Bit 1 - G1_IO2

pub fn g1_io1(&mut self) -> G1_IO1_W<'_>

Bit 0 - G1_IO1

impl W<u32, Reg<u32, _IOASCR>>

pub fn g7_io4(&mut self) -> G7_IO4_W<'_>

Bit 27 - G7_IO4

pub fn g7_io3(&mut self) -> G7_IO3_W<'_>

Bit 26 - G7_IO3

pub fn g7_io2(&mut self) -> G7_IO2_W<'_>

Bit 25 - G7_IO2

pub fn g7_io1(&mut self) -> G7_IO1_W<'_>

Bit 24 - G7_IO1

pub fn g6_io4(&mut self) -> G6_IO4_W<'_>

Bit 23 - G6_IO4

pub fn g6_io3(&mut self) -> G6_IO3_W<'_>

Bit 22 - G6_IO3

pub fn g6_io2(&mut self) -> G6_IO2_W<'_>

Bit 21 - G6_IO2

pub fn g6_io1(&mut self) -> G6_IO1_W<'_>

Bit 20 - G6_IO1

pub fn g5_io4(&mut self) -> G5_IO4_W<'_>

Bit 19 - G5_IO4

pub fn g5_io3(&mut self) -> G5_IO3_W<'_>

Bit 18 - G5_IO3

pub fn g5_io2(&mut self) -> G5_IO2_W<'_>

Bit 17 - G5_IO2

pub fn g5_io1(&mut self) -> G5_IO1_W<'_>

Bit 16 - G5_IO1

pub fn g4_io4(&mut self) -> G4_IO4_W<'_>

Bit 15 - G4_IO4

pub fn g4_io3(&mut self) -> G4_IO3_W<'_>

Bit 14 - G4_IO3

pub fn g4_io2(&mut self) -> G4_IO2_W<'_>

Bit 13 - G4_IO2

pub fn g4_io1(&mut self) -> G4_IO1_W<'_>

Bit 12 - G4_IO1

pub fn g3_io4(&mut self) -> G3_IO4_W<'_>

Bit 11 - G3_IO4

pub fn g3_io3(&mut self) -> G3_IO3_W<'_>

Bit 10 - G3_IO3

pub fn g3_io2(&mut self) -> G3_IO2_W<'_>

Bit 9 - G3_IO2

pub fn g3_io1(&mut self) -> G3_IO1_W<'_>

Bit 8 - G3_IO1

pub fn g2_io4(&mut self) -> G2_IO4_W<'_>

Bit 7 - G2_IO4

pub fn g2_io3(&mut self) -> G2_IO3_W<'_>

Bit 6 - G2_IO3

pub fn g2_io2(&mut self) -> G2_IO2_W<'_>

Bit 5 - G2_IO2

pub fn g2_io1(&mut self) -> G2_IO1_W<'_>

Bit 4 - G2_IO1

pub fn g1_io4(&mut self) -> G1_IO4_W<'_>

Bit 3 - G1_IO4

pub fn g1_io3(&mut self) -> G1_IO3_W<'_>

Bit 2 - G1_IO3

pub fn g1_io2(&mut self) -> G1_IO2_W<'_>

Bit 1 - G1_IO2

pub fn g1_io1(&mut self) -> G1_IO1_W<'_>

Bit 0 - G1_IO1

impl W<u32, Reg<u32, _IOSCR>>

pub fn g7_io4(&mut self) -> G7_IO4_W<'_>

Bit 27 - G7_IO4

pub fn g7_io3(&mut self) -> G7_IO3_W<'_>

Bit 26 - G7_IO3

pub fn g7_io2(&mut self) -> G7_IO2_W<'_>

Bit 25 - G7_IO2

pub fn g7_io1(&mut self) -> G7_IO1_W<'_>

Bit 24 - G7_IO1

pub fn g6_io4(&mut self) -> G6_IO4_W<'_>

Bit 23 - G6_IO4

pub fn g6_io3(&mut self) -> G6_IO3_W<'_>

Bit 22 - G6_IO3

pub fn g6_io2(&mut self) -> G6_IO2_W<'_>

Bit 21 - G6_IO2

pub fn g6_io1(&mut self) -> G6_IO1_W<'_>

Bit 20 - G6_IO1

pub fn g5_io4(&mut self) -> G5_IO4_W<'_>

Bit 19 - G5_IO4

pub fn g5_io3(&mut self) -> G5_IO3_W<'_>

Bit 18 - G5_IO3

pub fn g5_io2(&mut self) -> G5_IO2_W<'_>

Bit 17 - G5_IO2

pub fn g5_io1(&mut self) -> G5_IO1_W<'_>

Bit 16 - G5_IO1

pub fn g4_io4(&mut self) -> G4_IO4_W<'_>

Bit 15 - G4_IO4

pub fn g4_io3(&mut self) -> G4_IO3_W<'_>

Bit 14 - G4_IO3

pub fn g4_io2(&mut self) -> G4_IO2_W<'_>

Bit 13 - G4_IO2

pub fn g4_io1(&mut self) -> G4_IO1_W<'_>

Bit 12 - G4_IO1

pub fn g3_io4(&mut self) -> G3_IO4_W<'_>

Bit 11 - G3_IO4

pub fn g3_io3(&mut self) -> G3_IO3_W<'_>

Bit 10 - G3_IO3

pub fn g3_io2(&mut self) -> G3_IO2_W<'_>

Bit 9 - G3_IO2

pub fn g3_io1(&mut self) -> G3_IO1_W<'_>

Bit 8 - G3_IO1

pub fn g2_io4(&mut self) -> G2_IO4_W<'_>

Bit 7 - G2_IO4

pub fn g2_io3(&mut self) -> G2_IO3_W<'_>

Bit 6 - G2_IO3

pub fn g2_io2(&mut self) -> G2_IO2_W<'_>

Bit 5 - G2_IO2

pub fn g2_io1(&mut self) -> G2_IO1_W<'_>

Bit 4 - G2_IO1

pub fn g1_io4(&mut self) -> G1_IO4_W<'_>

Bit 3 - G1_IO4

pub fn g1_io3(&mut self) -> G1_IO3_W<'_>

Bit 2 - G1_IO3

pub fn g1_io2(&mut self) -> G1_IO2_W<'_>

Bit 1 - G1_IO2

pub fn g1_io1(&mut self) -> G1_IO1_W<'_>

Bit 0 - G1_IO1

impl W<u32, Reg<u32, _IOCCR>>

pub fn g7_io4(&mut self) -> G7_IO4_W<'_>

Bit 27 - G7_IO4

pub fn g7_io3(&mut self) -> G7_IO3_W<'_>

Bit 26 - G7_IO3

pub fn g7_io2(&mut self) -> G7_IO2_W<'_>

Bit 25 - G7_IO2

pub fn g7_io1(&mut self) -> G7_IO1_W<'_>

Bit 24 - G7_IO1

pub fn g6_io4(&mut self) -> G6_IO4_W<'_>

Bit 23 - G6_IO4

pub fn g6_io3(&mut self) -> G6_IO3_W<'_>

Bit 22 - G6_IO3

pub fn g6_io2(&mut self) -> G6_IO2_W<'_>

Bit 21 - G6_IO2

pub fn g6_io1(&mut self) -> G6_IO1_W<'_>

Bit 20 - G6_IO1

pub fn g5_io4(&mut self) -> G5_IO4_W<'_>

Bit 19 - G5_IO4

pub fn g5_io3(&mut self) -> G5_IO3_W<'_>

Bit 18 - G5_IO3

pub fn g5_io2(&mut self) -> G5_IO2_W<'_>

Bit 17 - G5_IO2

pub fn g5_io1(&mut self) -> G5_IO1_W<'_>

Bit 16 - G5_IO1

pub fn g4_io4(&mut self) -> G4_IO4_W<'_>

Bit 15 - G4_IO4

pub fn g4_io3(&mut self) -> G4_IO3_W<'_>

Bit 14 - G4_IO3

pub fn g4_io2(&mut self) -> G4_IO2_W<'_>

Bit 13 - G4_IO2

pub fn g4_io1(&mut self) -> G4_IO1_W<'_>

Bit 12 - G4_IO1

pub fn g3_io4(&mut self) -> G3_IO4_W<'_>

Bit 11 - G3_IO4

pub fn g3_io3(&mut self) -> G3_IO3_W<'_>

Bit 10 - G3_IO3

pub fn g3_io2(&mut self) -> G3_IO2_W<'_>

Bit 9 - G3_IO2

pub fn g3_io1(&mut self) -> G3_IO1_W<'_>

Bit 8 - G3_IO1

pub fn g2_io4(&mut self) -> G2_IO4_W<'_>

Bit 7 - G2_IO4

pub fn g2_io3(&mut self) -> G2_IO3_W<'_>

Bit 6 - G2_IO3

pub fn g2_io2(&mut self) -> G2_IO2_W<'_>

Bit 5 - G2_IO2

pub fn g2_io1(&mut self) -> G2_IO1_W<'_>

Bit 4 - G2_IO1

pub fn g1_io4(&mut self) -> G1_IO4_W<'_>

Bit 3 - G1_IO4

pub fn g1_io3(&mut self) -> G1_IO3_W<'_>

Bit 2 - G1_IO3

pub fn g1_io2(&mut self) -> G1_IO2_W<'_>

Bit 1 - G1_IO2

pub fn g1_io1(&mut self) -> G1_IO1_W<'_>

Bit 0 - G1_IO1

impl W<u32, Reg<u32, _IOGCSR>>

pub fn g7e(&mut self) -> G7E_W<'_>

Bit 6 - Analog I/O group x enable

pub fn g6e(&mut self) -> G6E_W<'_>

Bit 5 - Analog I/O group x enable

pub fn g5e(&mut self) -> G5E_W<'_>

Bit 4 - Analog I/O group x enable

pub fn g4e(&mut self) -> G4E_W<'_>

Bit 3 - Analog I/O group x enable

pub fn g3e(&mut self) -> G3E_W<'_>

Bit 2 - Analog I/O group x enable

pub fn g2e(&mut self) -> G2E_W<'_>

Bit 1 - Analog I/O group x enable

pub fn g1e(&mut self) -> G1E_W<'_>

Bit 0 - Analog I/O group x enable

impl W<u32, Reg<u32, _KR>>

pub fn key(&mut self) -> KEY_W<'_>

Bits 0:15 - Key value (write only, read 0x0000)

impl W<u32, Reg<u32, _PR>>

pub fn pr(&mut self) -> PR_W<'_>

Bits 0:2 - Prescaler divider

impl W<u32, Reg<u32, _RLR>>

pub fn rl(&mut self) -> RL_W<'_>

Bits 0:11 - Watchdog counter reload value

impl W<u32, Reg<u32, _WINR>>

pub fn win(&mut self) -> WIN_W<'_>

Bits 0:11 - Watchdog counter window value

impl W<u32, Reg<u32, _CR>>

pub fn wdga(&mut self) -> WDGA_W<'_>

Bit 7 - Activation bit

pub fn t(&mut self) -> T_W<'_>

Bits 0:6 - 7-bit counter (MSB to LSB)

impl W<u32, Reg<u32, _CFR>>

pub fn wdgtb(&mut self) -> WDGTB_W<'_>

Bits 11:13 - Timer base

pub fn ewi(&mut self) -> EWI_W<'_>

Bit 9 - Early wakeup interrupt

pub fn w(&mut self) -> W_W<'_>

Bits 0:6 - 7-bit window value

impl W<u32, Reg<u32, _SR>>

pub fn ewif(&mut self) -> EWIF_W<'_>

Bit 0 - Early wakeup interrupt flag

impl W<u32, Reg<u32, _COMP1_CSR>>

pub fn comp1_en(&mut self) -> COMP1_EN_W<'_>

Bit 0 - Comparator enable

pub fn comp1_pwrmode(&mut self) -> COMP1_PWRMODE_W<'_>

Bits 2:3 - Comparator power mode

pub fn comp1_inmsel(&mut self) -> COMP1_INMSEL_W<'_>

Bits 4:6 - Comparator input minus selection

pub fn comp1_inpsel(&mut self) -> COMP1_INPSEL_W<'_>

Bits 7:8 - Comparator input plus selection

pub fn comp1_polarity(&mut self) -> COMP1_POLARITY_W<'_>

Bit 15 - Comparator output polarity

pub fn comp1_hyst(&mut self) -> COMP1_HYST_W<'_>

Bits 16:17 - Comparator hysteresis

pub fn comp1_blanking(&mut self) -> COMP1_BLANKING_W<'_>

Bits 18:20 - Comparator blanking source

pub fn comp1_brgen(&mut self) -> COMP1_BRGEN_W<'_>

Bit 22 - Comparator voltage scaler enable

pub fn comp1_scalen(&mut self) -> COMP1_SCALEN_W<'_>

Bit 23 - Comparator scaler bridge enable

pub fn comp1_inmesel(&mut self) -> COMP1_INMESEL_W<'_>

Bits 25:26 - Comparator input minus extended selection

pub fn comp1_lock(&mut self) -> COMP1_LOCK_W<'_>

Bit 31 - Comparator lock

impl W<u32, Reg<u32, _COMP2_CSR>>

pub fn comp2_en(&mut self) -> COMP2_EN_W<'_>

Bit 0 - Comparator 2 enable bit

pub fn comp2_pwrmode(&mut self) -> COMP2_PWRMODE_W<'_>

Bits 2:3 - Power Mode of the comparator 2

pub fn comp2_inmsel(&mut self) -> COMP2_INMSEL_W<'_>

Bits 4:5 - Comparator 2 input minus selection bits

pub fn comp2_inpsel(&mut self) -> COMP2_INPSEL_W<'_>

Bits 7:8 - Comparator 1 input plus selection bit

pub fn comp2_winmode(&mut self) -> COMP2_WINMODE_W<'_>

Bit 9 - Windows mode selection bit

pub fn comp2_polarity(&mut self) -> COMP2_POLARITY_W<'_>

Bit 15 - Comparator 2 polarity selection bit

pub fn comp2_hyst(&mut self) -> COMP2_HYST_W<'_>

Bits 16:17 - Comparator 2 hysteresis selection bits

pub fn comp2_blanking(&mut self) -> COMP2_BLANKING_W<'_>

Bits 18:20 - Comparator 2 blanking source selection bits

pub fn comp2_brgen(&mut self) -> COMP2_BRGEN_W<'_>

Bit 22 - Scaler bridge enable

pub fn comp2_scalen(&mut self) -> COMP2_SCALEN_W<'_>

Bit 23 - Voltage scaler enable bit

pub fn comp2_inmesel(&mut self) -> COMP2_INMESEL_W<'_>

Bits 25:26 - comparator 2 input minus extended selection bits.

pub fn comp2_lock(&mut self) -> COMP2_LOCK_W<'_>

Bit 31 - CSR register lock bit

impl W<u32, Reg<u32, _CR1>>

pub fn pe(&mut self) -> PE_W<'_>

Bit 0 - Peripheral enable

pub fn txie(&mut self) -> TXIE_W<'_>

Bit 1 - TX Interrupt enable

pub fn rxie(&mut self) -> RXIE_W<'_>

Bit 2 - RX Interrupt enable

pub fn addrie(&mut self) -> ADDRIE_W<'_>

Bit 3 - Address match interrupt enable (slave only)

pub fn nackie(&mut self) -> NACKIE_W<'_>

Bit 4 - Not acknowledge received interrupt enable

pub fn stopie(&mut self) -> STOPIE_W<'_>

Bit 5 - STOP detection Interrupt enable

pub fn tcie(&mut self) -> TCIE_W<'_>

Bit 6 - Transfer Complete interrupt enable

pub fn errie(&mut self) -> ERRIE_W<'_>

Bit 7 - Error interrupts enable

pub fn dnf(&mut self) -> DNF_W<'_>

Bits 8:11 - Digital noise filter

pub fn anfoff(&mut self) -> ANFOFF_W<'_>

Bit 12 - Analog noise filter OFF

pub fn txdmaen(&mut self) -> TXDMAEN_W<'_>

Bit 14 - DMA transmission requests enable

pub fn rxdmaen(&mut self) -> RXDMAEN_W<'_>

Bit 15 - DMA reception requests enable

pub fn sbc(&mut self) -> SBC_W<'_>

Bit 16 - Slave byte control

pub fn nostretch(&mut self) -> NOSTRETCH_W<'_>

Bit 17 - Clock stretching disable

pub fn wupen(&mut self) -> WUPEN_W<'_>

Bit 18 - Wakeup from STOP enable

pub fn gcen(&mut self) -> GCEN_W<'_>

Bit 19 - General call enable

pub fn smbhen(&mut self) -> SMBHEN_W<'_>

Bit 20 - SMBus Host address enable

pub fn smbden(&mut self) -> SMBDEN_W<'_>

Bit 21 - SMBus Device Default address enable

pub fn alerten(&mut self) -> ALERTEN_W<'_>

Bit 22 - SMBUS alert enable

pub fn pecen(&mut self) -> PECEN_W<'_>

Bit 23 - PEC enable

impl W<u32, Reg<u32, _CR2>>

pub fn pecbyte(&mut self) -> PECBYTE_W<'_>

Bit 26 - Packet error checking byte

pub fn autoend(&mut self) -> AUTOEND_W<'_>

Bit 25 - Automatic end mode (master mode)

pub fn reload(&mut self) -> RELOAD_W<'_>

Bit 24 - NBYTES reload mode

pub fn nbytes(&mut self) -> NBYTES_W<'_>

Bits 16:23 - Number of bytes

pub fn nack(&mut self) -> NACK_W<'_>

Bit 15 - NACK generation (slave mode)

pub fn stop(&mut self) -> STOP_W<'_>

Bit 14 - Stop generation (master mode)

pub fn start(&mut self) -> START_W<'_>

Bit 13 - Start generation

pub fn head10r(&mut self) -> HEAD10R_W<'_>

Bit 12 - 10-bit address header only read direction (master receiver mode)

pub fn add10(&mut self) -> ADD10_W<'_>

Bit 11 - 10-bit addressing mode (master mode)

pub fn rd_wrn(&mut self) -> RD_WRN_W<'_>

Bit 10 - Transfer direction (master mode)

pub fn sadd(&mut self) -> SADD_W<'_>

Bits 0:9 - Slave address bit (master mode)

impl W<u32, Reg<u32, _OAR1>>

pub fn oa1(&mut self) -> OA1_W<'_>

Bits 0:9 - Interface address

pub fn oa1mode(&mut self) -> OA1MODE_W<'_>

Bit 10 - Own Address 1 10-bit mode

pub fn oa1en(&mut self) -> OA1EN_W<'_>

Bit 15 - Own Address 1 enable

impl W<u32, Reg<u32, _OAR2>>

pub fn oa2(&mut self) -> OA2_W<'_>

Bits 1:7 - Interface address

pub fn oa2msk(&mut self) -> OA2MSK_W<'_>

Bits 8:10 - Own Address 2 masks

pub fn oa2en(&mut self) -> OA2EN_W<'_>

Bit 15 - Own Address 2 enable

impl W<u32, Reg<u32, _TIMINGR>>

pub fn scll(&mut self) -> SCLL_W<'_>

Bits 0:7 - SCL low period (master mode)

pub fn sclh(&mut self) -> SCLH_W<'_>

Bits 8:15 - SCL high period (master mode)

pub fn sdadel(&mut self) -> SDADEL_W<'_>

Bits 16:19 - Data hold time

pub fn scldel(&mut self) -> SCLDEL_W<'_>

Bits 20:23 - Data setup time

pub fn presc(&mut self) -> PRESC_W<'_>

Bits 28:31 - Timing prescaler

impl W<u32, Reg<u32, _TIMEOUTR>>

pub fn timeouta(&mut self) -> TIMEOUTA_W<'_>

Bits 0:11 - Bus timeout A

pub fn tidle(&mut self) -> TIDLE_W<'_>

Bit 12 - Idle clock timeout detection

pub fn timouten(&mut self) -> TIMOUTEN_W<'_>

Bit 15 - Clock timeout enable

pub fn timeoutb(&mut self) -> TIMEOUTB_W<'_>

Bits 16:27 - Bus timeout B

pub fn texten(&mut self) -> TEXTEN_W<'_>

Bit 31 - Extended clock timeout enable

impl W<u32, Reg<u32, _ISR>>

pub fn txis(&mut self) -> TXIS_W<'_>

Bit 1 - Transmit interrupt status (transmitters)

pub fn txe(&mut self) -> TXE_W<'_>

Bit 0 - Transmit data register empty (transmitters)

impl W<u32, Reg<u32, _ICR>>

pub fn alertcf(&mut self) -> ALERTCF_W<'_>

Bit 13 - Alert flag clear

pub fn timoutcf(&mut self) -> TIMOUTCF_W<'_>

Bit 12 - Timeout detection flag clear

pub fn peccf(&mut self) -> PECCF_W<'_>

Bit 11 - PEC Error flag clear

pub fn ovrcf(&mut self) -> OVRCF_W<'_>

Bit 10 - Overrun/Underrun flag clear

pub fn arlocf(&mut self) -> ARLOCF_W<'_>

Bit 9 - Arbitration lost flag clear

pub fn berrcf(&mut self) -> BERRCF_W<'_>

Bit 8 - Bus error flag clear

pub fn stopcf(&mut self) -> STOPCF_W<'_>

Bit 5 - Stop detection flag clear

pub fn nackcf(&mut self) -> NACKCF_W<'_>

Bit 4 - Not Acknowledge flag clear

pub fn addrcf(&mut self) -> ADDRCF_W<'_>

Bit 3 - Address Matched flag clear

impl W<u32, Reg<u32, _TXDR>>

pub fn txdata(&mut self) -> TXDATA_W<'_>

Bits 0:7 - 8-bit transmit data

impl W<u32, Reg<u32, _ACR>>

pub fn latency(&mut self) -> LATENCY_W<'_>

Bits 0:2 - Latency

pub fn prften(&mut self) -> PRFTEN_W<'_>

Bit 8 - Prefetch enable

pub fn icen(&mut self) -> ICEN_W<'_>

Bit 9 - Instruction cache enable

pub fn dcen(&mut self) -> DCEN_W<'_>

Bit 10 - Data cache enable

pub fn icrst(&mut self) -> ICRST_W<'_>

Bit 11 - Instruction cache reset

pub fn dcrst(&mut self) -> DCRST_W<'_>

Bit 12 - Data cache reset

pub fn pes(&mut self) -> PES_W<'_>

Bit 15 - CPU1 CortexM4 program erase suspend request

pub fn empty(&mut self) -> EMPTY_W<'_>

Bit 16 - Flash User area empty

impl W<u32, Reg<u32, _KEYR>>

pub fn keyr(&mut self) -> KEYR_W<'_>

Bits 0:31 - KEYR

impl W<u32, Reg<u32, _OPTKEYR>>

pub fn optkeyr(&mut self) -> OPTKEYR_W<'_>

Bits 0:31 - Option byte key

impl W<u32, Reg<u32, _SR>>

pub fn eop(&mut self) -> EOP_W<'_>

Bit 0 - End of operation

pub fn operr(&mut self) -> OPERR_W<'_>

Bit 1 - Operation error

pub fn progerr(&mut self) -> PROGERR_W<'_>

Bit 3 - Programming error

pub fn wrperr(&mut self) -> WRPERR_W<'_>

Bit 4 - Write protected error

pub fn pgaerr(&mut self) -> PGAERR_W<'_>

Bit 5 - Programming alignment error

pub fn sizerr(&mut self) -> SIZERR_W<'_>

Bit 6 - Size error

pub fn pgserr(&mut self) -> PGSERR_W<'_>

Bit 7 - Programming sequence error

pub fn miserr(&mut self) -> MISERR_W<'_>

Bit 8 - Fast programming data miss error

pub fn fasterr(&mut self) -> FASTERR_W<'_>

Bit 9 - Fast programming error

pub fn rderr(&mut self) -> RDERR_W<'_>

Bit 14 - PCROP read error

pub fn optverr(&mut self) -> OPTVERR_W<'_>

Bit 15 - Option validity error

impl W<u32, Reg<u32, _CR>>

pub fn pg(&mut self) -> PG_W<'_>

Bit 0 - Programming

pub fn per(&mut self) -> PER_W<'_>

Bit 1 - Page erase

pub fn mer(&mut self) -> MER_W<'_>

Bit 2 - This bit triggers the mass erase (all user pages) when set

pub fn pnb(&mut self) -> PNB_W<'_>

Bits 3:10 - Page number selection

pub fn strt(&mut self) -> STRT_W<'_>

Bit 16 - Start

pub fn optstrt(&mut self) -> OPTSTRT_W<'_>

Bit 17 - Options modification start

pub fn fstpg(&mut self) -> FSTPG_W<'_>

Bit 18 - Fast programming

pub fn eopie(&mut self) -> EOPIE_W<'_>

Bit 24 - End of operation interrupt enable

pub fn errie(&mut self) -> ERRIE_W<'_>

Bit 25 - Error interrupt enable

pub fn rderrie(&mut self) -> RDERRIE_W<'_>

Bit 26 - PCROP read error interrupt enable

pub fn obl_launch(&mut self) -> OBL_LAUNCH_W<'_>

Bit 27 - Force the option byte loading

pub fn optlock(&mut self) -> OPTLOCK_W<'_>

Bit 30 - Options Lock

pub fn lock(&mut self) -> LOCK_W<'_>

Bit 31 - FLASH_CR Lock

impl W<u32, Reg<u32, _ECCR>>

pub fn ecccie(&mut self) -> ECCCIE_W<'_>

Bit 24 - ECC correction interrupt enable

pub fn eccc(&mut self) -> ECCC_W<'_>

Bit 30 - ECC correction

pub fn eccd(&mut self) -> ECCD_W<'_>

Bit 31 - ECC detection

impl W<u32, Reg<u32, _OPTR>>

pub fn rdp(&mut self) -> RDP_W<'_>

Bits 0:7 - Read protection level

pub fn ese(&mut self) -> ESE_W<'_>

Bit 8 - Security enabled

pub fn bor_lev(&mut self) -> BOR_LEV_W<'_>

Bits 9:11 - BOR reset Level

pub fn n_rst_stop(&mut self) -> NRST_STOP_W<'_>

Bit 12 - nRST_STOP

pub fn n_rst_stdby(&mut self) -> NRST_STDBY_W<'_>

Bit 13 - nRST_STDBY

pub fn n_rst_shdw(&mut self) -> NRST_SHDW_W<'_>

Bit 14 - nRST_SHDW

pub fn idwg_sw(&mut self) -> IDWG_SW_W<'_>

Bit 16 - Independent watchdog selection

pub fn iwdg_stop(&mut self) -> IWDG_STOP_W<'_>

Bit 17 - Independent watchdog counter freeze in Stop mode

pub fn iwdg_stdby(&mut self) -> IWDG_STDBY_W<'_>

Bit 18 - Independent watchdog counter freeze in Standby mode

pub fn wwdg_sw(&mut self) -> WWDG_SW_W<'_>

Bit 19 - Window watchdog selection

pub fn n_boot1(&mut self) -> NBOOT1_W<'_>

Bit 23 - Boot configuration

pub fn sram2_pe(&mut self) -> SRAM2_PE_W<'_>

Bit 24 - SRAM2 parity check enable

pub fn sram2_rst(&mut self) -> SRAM2_RST_W<'_>

Bit 25 - SRAM2 Erase when system reset

pub fn n_swboot0(&mut self) -> NSWBOOT0_W<'_>

Bit 26 - Software Boot0

pub fn n_boot0(&mut self) -> NBOOT0_W<'_>

Bit 27 - nBoot0 option bit

pub fn agc_trim(&mut self) -> AGC_TRIM_W<'_>

Bits 29:31 - Radio Automatic Gain Control Trimming

impl W<u32, Reg<u32, _PCROP1ASR>>

pub fn pcrop1a_strt(&mut self) -> PCROP1A_STRT_W<'_>

Bits 0:8 - Bank 1 PCROPQ area start offset

impl W<u32, Reg<u32, _PCROP1AER>>

pub fn pcrop1a_end(&mut self) -> PCROP1A_END_W<'_>

Bits 0:8 - Bank 1 PCROP area end offset

pub fn pcrop_rdp(&mut self) -> PCROP_RDP_W<'_>

Bit 31 - PCROP area preserved when RDP level decreased

impl W<u32, Reg<u32, _WRP1AR>>

pub fn wrp1a_strt(&mut self) -> WRP1A_STRT_W<'_>

Bits 0:7 - Bank 1 WRP first area A start offset

pub fn wrp1a_end(&mut self) -> WRP1A_END_W<'_>

Bits 16:23 - Bank 1 WRP first area A end offset

impl W<u32, Reg<u32, _WRP1BR>>

pub fn wrp1b_strt(&mut self) -> WRP1B_STRT_W<'_>

Bits 16:23 - Bank 1 WRP second area B end offset

pub fn wrp1b_end(&mut self) -> WRP1B_END_W<'_>

Bits 0:7 - Bank 1 WRP second area B start offset

impl W<u32, Reg<u32, _PCROP1BSR>>

pub fn pcrop1b_strt(&mut self) -> PCROP1B_STRT_W<'_>

Bits 0:8 - Bank 1 PCROP area B start offset

impl W<u32, Reg<u32, _PCROP1BER>>

pub fn pcrop1b_end(&mut self) -> PCROP1B_END_W<'_>

Bits 0:8 - Bank 1 PCROP area end area B offset

impl W<u32, Reg<u32, _IPCCBR>>

pub fn ipccdba(&mut self) -> IPCCDBA_W<'_>

Bits 0:13 - PCC mailbox data buffer base address

impl W<u32, Reg<u32, _C2ACR>>

pub fn prften(&mut self) -> PRFTEN_W<'_>

Bit 8 - CPU2 cortex M0 prefetch enable

pub fn icen(&mut self) -> ICEN_W<'_>

Bit 9 - CPU2 cortex M0 instruction cache enable

pub fn icrst(&mut self) -> ICRST_W<'_>

Bit 11 - CPU2 cortex M0 instruction cache reset

pub fn pes(&mut self) -> PES_W<'_>

Bit 15 - CPU2 cortex M0 program erase suspend request

impl W<u32, Reg<u32, _C2SR>>

pub fn eop(&mut self) -> EOP_W<'_>

Bit 0 - End of operation

pub fn operr(&mut self) -> OPERR_W<'_>

Bit 1 - Operation error

pub fn progerr(&mut self) -> PROGERR_W<'_>

Bit 3 - Programming error

pub fn wrperr(&mut self) -> WRPERR_W<'_>

Bit 4 - write protection error

pub fn pgaerr(&mut self) -> PGAERR_W<'_>

Bit 5 - Programming alignment error

pub fn sizerr(&mut self) -> SIZERR_W<'_>

Bit 6 - Size error

pub fn pgserr(&mut self) -> PGSERR_W<'_>

Bit 7 - Programming sequence error

pub fn misserr(&mut self) -> MISSERR_W<'_>

Bit 8 - Fast programming data miss error

pub fn fasterr(&mut self) -> FASTERR_W<'_>

Bit 9 - Fast programming error

pub fn rderr(&mut self) -> RDERR_W<'_>

Bit 14 - PCROP read error

pub fn bsy(&mut self) -> BSY_W<'_>

Bit 16 - Busy

pub fn cfgbsy(&mut self) -> CFGBSY_W<'_>

Bit 18 - Programming or erase configuration busy

pub fn pesd(&mut self) -> PESD_W<'_>

Bit 19 - Programming or erase operation suspended

impl W<u32, Reg<u32, _C2CR>>

pub fn pg(&mut self) -> PG_W<'_>

Bit 0 - Programming

pub fn per(&mut self) -> PER_W<'_>

Bit 1 - Page erase

pub fn mer(&mut self) -> MER_W<'_>

Bit 2 - Masse erase

pub fn pnb(&mut self) -> PNB_W<'_>

Bits 3:10 - Page Number selection

pub fn strt(&mut self) -> STRT_W<'_>

Bit 16 - Start

pub fn fstpg(&mut self) -> FSTPG_W<'_>

Bit 18 - Fast programming

pub fn eopie(&mut self) -> EOPIE_W<'_>

Bit 24 - End of operation interrupt enable

pub fn errie(&mut self) -> ERRIE_W<'_>

Bit 25 - Error interrupt enable

pub fn rderrie(&mut self) -> RDERRIE_W<'_>

Bit 26 - PCROP read error interrupt enable

impl W<u32, Reg<u32, _SFR>>

pub fn sfsa(&mut self) -> SFSA_W<'_>

Bits 0:7 - Secure flash start address

pub fn dds(&mut self) -> DDS_W<'_>

Bit 12 - Disable Cortex M0 debug access

pub fn fsd(&mut self) -> FSD_W<'_>

Bit 8 - Flash security disable

impl W<u32, Reg<u32, _SRRVR>>

pub fn sbrv(&mut self) -> SBRV_W<'_>

Bits 0:17 - cortex M0 access control register

pub fn sbrsa(&mut self) -> SBRSA_W<'_>

Bits 18:22 - Secure backup SRAM2a start address

pub fn brsd(&mut self) -> BRSD_W<'_>

Bit 23 - backup SRAM2a security disable

pub fn snbrsa(&mut self) -> SNBRSA_W<'_>

Bits 25:29 - Secure non backup SRAM2a start address

pub fn c2opt(&mut self) -> C2OPT_W<'_>

Bit 31 - CPU2 cortex M0 boot reset vector memory selection

pub fn nbrsd(&mut self) -> NBRSD_W<'_>

Bit 30 - non-backup SRAM2b security disable

impl W<u32, Reg<u32, _CR>>

pub fn prescaler(&mut self) -> PRESCALER_W<'_>

Bits 24:31 - Clock prescaler

pub fn pmm(&mut self) -> PMM_W<'_>

Bit 23 - Polling match mode

pub fn apms(&mut self) -> APMS_W<'_>

Bit 22 - Automatic poll mode stop

pub fn toie(&mut self) -> TOIE_W<'_>

Bit 20 - TimeOut interrupt enable

pub fn smie(&mut self) -> SMIE_W<'_>

Bit 19 - Status match interrupt enable

pub fn ftie(&mut self) -> FTIE_W<'_>

Bit 18 - FIFO threshold interrupt enable

pub fn tcie(&mut self) -> TCIE_W<'_>

Bit 17 - Transfer complete interrupt enable

pub fn teie(&mut self) -> TEIE_W<'_>

Bit 16 - Transfer error interrupt enable

pub fn fthres(&mut self) -> FTHRES_W<'_>

Bits 8:11 - FIFO threshold level

pub fn sshift(&mut self) -> SSHIFT_W<'_>

Bit 4 - Sample shift

pub fn tcen(&mut self) -> TCEN_W<'_>

Bit 3 - Timeout counter enable

pub fn dmaen(&mut self) -> DMAEN_W<'_>

Bit 2 - DMA enable

pub fn abort(&mut self) -> ABORT_W<'_>

Bit 1 - Abort request

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - Enable

impl W<u32, Reg<u32, _DCR>>

pub fn fsize(&mut self) -> FSIZE_W<'_>

Bits 16:20 - FLASH memory size

pub fn csht(&mut self) -> CSHT_W<'_>

Bits 8:10 - Chip select high time

pub fn ckmode(&mut self) -> CKMODE_W<'_>

Bit 0 - Mode 0 / mode 3

impl W<u32, Reg<u32, _FCR>>

pub fn ctof(&mut self) -> CTOF_W<'_>

Bit 4 - Clear timeout flag

pub fn csmf(&mut self) -> CSMF_W<'_>

Bit 3 - Clear status match flag

pub fn ctcf(&mut self) -> CTCF_W<'_>

Bit 1 - Clear transfer complete flag

pub fn ctef(&mut self) -> CTEF_W<'_>

Bit 0 - Clear transfer error flag

impl W<u32, Reg<u32, _DLR>>

pub fn dl(&mut self) -> DL_W<'_>

Bits 0:31 - Data length

impl W<u32, Reg<u32, _CCR>>

pub fn ddrm(&mut self) -> DDRM_W<'_>

Bit 31 - Double data rate mode

pub fn sioo(&mut self) -> SIOO_W<'_>

Bit 28 - Send instruction only once mode

pub fn fmode(&mut self) -> FMODE_W<'_>

Bits 26:27 - Functional mode

pub fn dmode(&mut self) -> DMODE_W<'_>

Bits 24:25 - Data mode

pub fn dcyc(&mut self) -> DCYC_W<'_>

Bits 18:22 - Number of dummy cycles

pub fn absize(&mut self) -> ABSIZE_W<'_>

Bits 16:17 - Alternate bytes size

pub fn abmode(&mut self) -> ABMODE_W<'_>

Bits 14:15 - Alternate bytes mode

pub fn adsize(&mut self) -> ADSIZE_W<'_>

Bits 12:13 - Address size

pub fn admode(&mut self) -> ADMODE_W<'_>

Bits 10:11 - Address mode

pub fn imode(&mut self) -> IMODE_W<'_>

Bits 8:9 - Instruction mode

pub fn instruction(&mut self) -> INSTRUCTION_W<'_>

Bits 0:7 - Instruction

impl W<u32, Reg<u32, _AR>>

pub fn address(&mut self) -> ADDRESS_W<'_>

Bits 0:31 - Address

impl W<u32, Reg<u32, _ABR>>

pub fn alternate(&mut self) -> ALTERNATE_W<'_>

Bits 0:31 - ALTERNATE

impl W<u32, Reg<u32, _DR>>

pub fn data(&mut self) -> DATA_W<'_>

Bits 0:31 - Data

impl W<u32, Reg<u32, _PSMKR>>

pub fn mask(&mut self) -> MASK_W<'_>

Bits 0:31 - Status mask

impl W<u32, Reg<u32, _PSMAR>>

pub fn match_(&mut self) -> MATCH_W<'_>

Bits 0:31 - Status match

impl W<u32, Reg<u32, _PIR>>

pub fn interval(&mut self) -> INTERVAL_W<'_>

Bits 0:15 - Polling interval

impl W<u32, Reg<u32, _LPTR>>

pub fn timeout(&mut self) -> TIMEOUT_W<'_>

Bits 0:15 - Timeout period

impl W<u32, Reg<u32, _CR>>

pub fn pllsai1on(&mut self) -> PLLSAI1ON_W<'_>

Bit 26 - SAI1 PLL enable

pub fn pllon(&mut self) -> PLLON_W<'_>

Bit 24 - Main PLL enable

pub fn hsepre(&mut self) -> HSEPRE_W<'_>

Bit 20 - HSE sysclk and PLL M divider prescaler

pub fn csson(&mut self) -> CSSON_W<'_>

Bit 19 - HSE Clock security system enable

pub fn hsebyp(&mut self) -> HSEBYP_W<'_>

Bit 18 - HSE crystal oscillator bypass

pub fn hseon(&mut self) -> HSEON_W<'_>

Bit 16 - HSE clock enabled

pub fn hsiasfs(&mut self) -> HSIASFS_W<'_>

Bit 11 - HSI automatic start from Stop

pub fn hsikeron(&mut self) -> HSIKERON_W<'_>

Bit 9 - HSI always enable for peripheral kernels

pub fn hsion(&mut self) -> HSION_W<'_>

Bit 8 - HSI clock enabled

pub fn msirange(&mut self) -> MSIRANGE_W<'_>

Bits 4:7 - MSI clock ranges

pub fn msipllen(&mut self) -> MSIPLLEN_W<'_>

Bit 2 - MSI clock PLL enable

pub fn msion(&mut self) -> MSION_W<'_>

Bit 0 - MSI clock enable

impl W<u32, Reg<u32, _ICSCR>>

pub fn hsitrim(&mut self) -> HSITRIM_W<'_>

Bits 24:30 - HSI clock trimming

pub fn msitrim(&mut self) -> MSITRIM_W<'_>

Bits 8:15 - MSI clock trimming

impl W<u32, Reg<u32, _CFGR>>

pub fn mcopre(&mut self) -> MCOPRE_W<'_>

Bits 28:30 - Microcontroller clock output prescaler

pub fn mcosel(&mut self) -> MCOSEL_W<'_>

Bits 24:27 - Microcontroller clock output

pub fn stopwuck(&mut self) -> STOPWUCK_W<'_>

Bit 15 - Wakeup from Stop and CSS backup clock selection

pub fn ppre2(&mut self) -> PPRE2_W<'_>

Bits 11:13 - APB high-speed prescaler (APB2)

pub fn ppre1(&mut self) -> PPRE1_W<'_>

Bits 8:10 - PB low-speed prescaler (APB1)

pub fn hpre(&mut self) -> HPRE_W<'_>

Bits 4:7 - AHB prescaler

pub fn sw(&mut self) -> SW_W<'_>

Bits 0:1 - System clock switch

impl W<u32, Reg<u32, _PLLCFGR>>

pub fn pllr(&mut self) -> PLLR_W<'_>

Bits 29:31 - Main PLLSYS division factor R for SYSCLK (system clock)

pub fn pllren(&mut self) -> PLLREN_W<'_>

Bit 28 - Main PLLSYSR PLLCLK output enable

pub fn pllq(&mut self) -> PLLQ_W<'_>

Bits 25:27 - Main PLLSYS division factor Q for PLLSYSUSBCLK

pub fn pllqen(&mut self) -> PLLQEN_W<'_>

Bit 24 - Main PLLSYSQ output enable

pub fn pllp(&mut self) -> PLLP_W<'_>

Bits 17:21 - Main PLL division factor P for PPLSYSSAICLK

pub fn pllpen(&mut self) -> PLLPEN_W<'_>

Bit 16 - Main PLLSYSP output enable

pub fn plln(&mut self) -> PLLN_W<'_>

Bits 8:14 - Main PLLSYS multiplication factor N

pub fn pllm(&mut self) -> PLLM_W<'_>

Bits 4:6 - Division factor M for the main PLL and audio PLL (PLLSAI1 and PLLSAI2) input clock

pub fn pllsrc(&mut self) -> PLLSRC_W<'_>

Bits 0:1 - Main PLL, PLLSAI1 and PLLSAI2 entry clock source

impl W<u32, Reg<u32, _PLLSAI1CFGR>>

pub fn pllr(&mut self) -> PLLR_W<'_>

Bits 29:31 - PLLSAI division factor R for PLLADC1CLK (ADC clock)

pub fn pllren(&mut self) -> PLLREN_W<'_>

Bit 28 - PLLSAI PLLADC1CLK output enable

pub fn pllq(&mut self) -> PLLQ_W<'_>

Bits 25:27 - SAIPLL division factor Q for PLLSAIUSBCLK (48 MHz clock)

pub fn pllqen(&mut self) -> PLLQEN_W<'_>

Bit 24 - SAIPLL PLLSAIUSBCLK output enable

pub fn pllp(&mut self) -> PLLP_W<'_>

Bits 17:21 - SAI1PLL division factor P for PLLSAICLK (SAI1clock)

pub fn pllpen(&mut self) -> PLLPEN_W<'_>

Bit 16 - SAIPLL PLLSAI1CLK output enable

pub fn plln(&mut self) -> PLLN_W<'_>

Bits 8:14 - SAIPLL multiplication factor for VCO

impl W<u32, Reg<u32, _CIER>>

pub fn lsi2rdyie(&mut self) -> LSI2RDYIE_W<'_>

Bit 11 - LSI2 ready interrupt enable

pub fn hsi48rdyie(&mut self) -> HSI48RDYIE_W<'_>

Bit 10 - HSI48 ready interrupt enable

pub fn lsecssie(&mut self) -> LSECSSIE_W<'_>

Bit 9 - LSE clock security system interrupt enable

pub fn pllsai1rdyie(&mut self) -> PLLSAI1RDYIE_W<'_>

Bit 6 - PLLSAI1 ready interrupt enable

pub fn pllrdyie(&mut self) -> PLLRDYIE_W<'_>

Bit 5 - PLLSYS ready interrupt enable

pub fn hserdyie(&mut self) -> HSERDYIE_W<'_>

Bit 4 - HSE ready interrupt enable

pub fn hsirdyie(&mut self) -> HSIRDYIE_W<'_>

Bit 3 - HSI ready interrupt enable

pub fn msirdyie(&mut self) -> MSIRDYIE_W<'_>

Bit 2 - MSI ready interrupt enable

pub fn lserdyie(&mut self) -> LSERDYIE_W<'_>

Bit 1 - LSE ready interrupt enable

pub fn lsi1rdyie(&mut self) -> LSI1RDYIE_W<'_>

Bit 0 - LSI1 ready interrupt enable

impl W<u32, Reg<u32, _CICR>>

pub fn lsi2rdyc(&mut self) -> LSI2RDYC_W<'_>

Bit 11 - LSI2 ready interrupt clear

pub fn hsi48rdyc(&mut self) -> HSI48RDYC_W<'_>

Bit 10 - HSI48 ready interrupt clear

pub fn lsecssc(&mut self) -> LSECSSC_W<'_>

Bit 9 - LSE Clock security system interrupt clear

pub fn hsecssc(&mut self) -> HSECSSC_W<'_>

Bit 8 - HSE Clock security system interrupt clear

pub fn pllsai1rdyc(&mut self) -> PLLSAI1RDYC_W<'_>

Bit 6 - PLLSAI1 ready interrupt clear

pub fn pllrdyc(&mut self) -> PLLRDYC_W<'_>

Bit 5 - PLL ready interrupt clear

pub fn hserdyc(&mut self) -> HSERDYC_W<'_>

Bit 4 - HSE ready interrupt clear

pub fn hsirdyc(&mut self) -> HSIRDYC_W<'_>

Bit 3 - HSI ready interrupt clear

pub fn msirdyc(&mut self) -> MSIRDYC_W<'_>

Bit 2 - MSI ready interrupt clear

pub fn lserdyc(&mut self) -> LSERDYC_W<'_>

Bit 1 - LSE ready interrupt clear

pub fn lsi1rdyc(&mut self) -> LSI1RDYC_W<'_>

Bit 0 - LSI1 ready interrupt clear

impl W<u32, Reg<u32, _SMPSCR>>

pub fn smpsdiv(&mut self) -> SMPSDIV_W<'_>

Bits 4:5 - Step Down converter clock prescaler

pub fn smpssel(&mut self) -> SMPSSEL_W<'_>

Bits 0:1 - Step Down converter clock selection

impl W<u32, Reg<u32, _AHB1RSTR>>

pub fn tscrst(&mut self) -> TSCRST_W<'_>

Bit 16 - Touch Sensing Controller reset

pub fn crcrst(&mut self) -> CRCRST_W<'_>

Bit 12 - CRC reset

pub fn dmamuxrst(&mut self) -> DMAMUXRST_W<'_>

Bit 2 - DMAMUX reset

pub fn dma2rst(&mut self) -> DMA2RST_W<'_>

Bit 1 - DMA2 reset

pub fn dma1rst(&mut self) -> DMA1RST_W<'_>

Bit 0 - DMA1 reset

impl W<u32, Reg<u32, _AHB2RSTR>>

pub fn aes1rst(&mut self) -> AES1RST_W<'_>

Bit 16 - AES1 hardware accelerator reset

pub fn adcrst(&mut self) -> ADCRST_W<'_>

Bit 13 - ADC reset

pub fn gpiohrst(&mut self) -> GPIOHRST_W<'_>

Bit 7 - IO port H reset

pub fn gpioerst(&mut self) -> GPIOERST_W<'_>

Bit 4 - IO port E reset

pub fn gpiodrst(&mut self) -> GPIODRST_W<'_>

Bit 3 - IO port D reset

pub fn gpiocrst(&mut self) -> GPIOCRST_W<'_>

Bit 2 - IO port C reset

pub fn gpiobrst(&mut self) -> GPIOBRST_W<'_>

Bit 1 - IO port B reset

pub fn gpioarst(&mut self) -> GPIOARST_W<'_>

Bit 0 - IO port A reset

impl W<u32, Reg<u32, _AHB3RSTR>>

pub fn flashrst(&mut self) -> FLASHRST_W<'_>

Bit 25 - Flash interface reset

pub fn ipccrst(&mut self) -> IPCCRST_W<'_>

Bit 20 - IPCC interface reset

pub fn hsemrst(&mut self) -> HSEMRST_W<'_>

Bit 19 - HSEM interface reset

pub fn rngrst(&mut self) -> RNGRST_W<'_>

Bit 18 - RNG interface reset

pub fn aes2rst(&mut self) -> AES2RST_W<'_>

Bit 17 - AES2 interface reset

pub fn pkarst(&mut self) -> PKARST_W<'_>

Bit 16 - PKA interface reset

pub fn qspirst(&mut self) -> QSPIRST_W<'_>

Bit 8 - Quad SPI memory interface reset

impl W<u32, Reg<u32, _APB1RSTR1>>

pub fn lptim1rst(&mut self) -> LPTIM1RST_W<'_>

Bit 31 - Low Power Timer 1 reset

pub fn usbfsrst(&mut self) -> USBFSRST_W<'_>

Bit 26 - USB FS reset

pub fn crsrst(&mut self) -> CRSRST_W<'_>

Bit 24 - CRS reset

pub fn i2c3rst(&mut self) -> I2C3RST_W<'_>

Bit 23 - I2C3 reset

pub fn i2c1rst(&mut self) -> I2C1RST_W<'_>

Bit 21 - I2C1 reset

pub fn spi2rst(&mut self) -> SPI2RST_W<'_>

Bit 14 - SPI2 reset

pub fn lcdrst(&mut self) -> LCDRST_W<'_>

Bit 9 - LCD interface reset

pub fn tim2rst(&mut self) -> TIM2RST_W<'_>

Bit 0 - TIM2 timer reset

impl W<u32, Reg<u32, _APB1RSTR2>>

pub fn lptim2rst(&mut self) -> LPTIM2RST_W<'_>

Bit 5 - Low-power timer 2 reset

pub fn lpuart1rst(&mut self) -> LPUART1RST_W<'_>

Bit 0 - Low-power UART 1 reset

impl W<u32, Reg<u32, _APB2RSTR>>

pub fn sai1rst(&mut self) -> SAI1RST_W<'_>

Bit 21 - Serial audio interface 1 (SAI1) reset

pub fn tim17rst(&mut self) -> TIM17RST_W<'_>

Bit 18 - TIM17 timer reset

pub fn tim16rst(&mut self) -> TIM16RST_W<'_>

Bit 17 - TIM16 timer reset

pub fn usart1rst(&mut self) -> USART1RST_W<'_>

Bit 14 - USART1 reset

pub fn spi1rst(&mut self) -> SPI1RST_W<'_>

Bit 12 - SPI1 reset

pub fn tim1rst(&mut self) -> TIM1RST_W<'_>

Bit 11 - TIM1 timer reset

impl W<u32, Reg<u32, _APB3RSTR>>

pub fn rfrst(&mut self) -> RFRST_W<'_>

Bit 0 - Radio system BLE reset

impl W<u32, Reg<u32, _AHB1ENR>>

pub fn tscen(&mut self) -> TSCEN_W<'_>

Bit 16 - Touch Sensing Controller clock enable

pub fn crcen(&mut self) -> CRCEN_W<'_>

Bit 12 - CPU1 CRC clock enable

pub fn dmamuxen(&mut self) -> DMAMUXEN_W<'_>

Bit 2 - DMAMUX clock enable

pub fn dma2en(&mut self) -> DMA2EN_W<'_>

Bit 1 - DMA2 clock enable

pub fn dma1en(&mut self) -> DMA1EN_W<'_>

Bit 0 - DMA1 clock enable

impl W<u32, Reg<u32, _AHB2ENR>>

pub fn aes1en(&mut self) -> AES1EN_W<'_>

Bit 16 - AES1 accelerator clock enable

pub fn adcen(&mut self) -> ADCEN_W<'_>

Bit 13 - ADC clock enable

pub fn gpiohen(&mut self) -> GPIOHEN_W<'_>

Bit 7 - IO port H clock enable

pub fn gpioeen(&mut self) -> GPIOEEN_W<'_>

Bit 4 - IO port E clock enable

pub fn gpioden(&mut self) -> GPIODEN_W<'_>

Bit 3 - IO port D clock enable

pub fn gpiocen(&mut self) -> GPIOCEN_W<'_>

Bit 2 - IO port C clock enable

pub fn gpioben(&mut self) -> GPIOBEN_W<'_>

Bit 1 - IO port B clock enable

pub fn gpioaen(&mut self) -> GPIOAEN_W<'_>

Bit 0 - IO port A clock enable

impl W<u32, Reg<u32, _AHB3ENR>>

pub fn flashen(&mut self) -> FLASHEN_W<'_>

Bit 25 - FLASHEN

pub fn ipccen(&mut self) -> IPCCEN_W<'_>

Bit 20 - IPCCEN

pub fn hsemen(&mut self) -> HSEMEN_W<'_>

Bit 19 - HSEMEN

pub fn rngen(&mut self) -> RNGEN_W<'_>

Bit 18 - RNGEN

pub fn aes2en(&mut self) -> AES2EN_W<'_>

Bit 17 - AES2EN

pub fn pkaen(&mut self) -> PKAEN_W<'_>

Bit 16 - PKAEN

pub fn qspien(&mut self) -> QSPIEN_W<'_>

Bit 8 - QSPIEN

impl W<u32, Reg<u32, _APB1ENR1>>

pub fn lptim1en(&mut self) -> LPTIM1EN_W<'_>

Bit 31 - CPU1 Low power timer 1 clock enable

pub fn usben(&mut self) -> USBEN_W<'_>

Bit 26 - CPU1 USB clock enable

pub fn crsen(&mut self) -> CRSEN_W<'_>

Bit 24 - CPU1 CRS clock enable

pub fn i2c3en(&mut self) -> I2C3EN_W<'_>

Bit 23 - CPU1 I2C3 clock enable

pub fn i2c1en(&mut self) -> I2C1EN_W<'_>

Bit 21 - CPU1 I2C1 clock enable

pub fn spi2en(&mut self) -> SPI2EN_W<'_>

Bit 14 - CPU1 SPI2 clock enable

pub fn wwdgen(&mut self) -> WWDGEN_W<'_>

Bit 11 - CPU1 Window watchdog clock enable

pub fn rtcapben(&mut self) -> RTCAPBEN_W<'_>

Bit 10 - CPU1 RTC APB clock enable

pub fn lcden(&mut self) -> LCDEN_W<'_>

Bit 9 - CPU1 LCD clock enable

pub fn tim2en(&mut self) -> TIM2EN_W<'_>

Bit 0 - CPU1 TIM2 timer clock enable

impl W<u32, Reg<u32, _APB1ENR2>>

pub fn lptim2en(&mut self) -> LPTIM2EN_W<'_>

Bit 5 - CPU1 LPTIM2EN

pub fn lpuart1en(&mut self) -> LPUART1EN_W<'_>

Bit 0 - CPU1 Low power UART 1 clock enable

impl W<u32, Reg<u32, _APB2ENR>>

pub fn sai1en(&mut self) -> SAI1EN_W<'_>

Bit 21 - CPU1 SAI1 clock enable

pub fn tim17en(&mut self) -> TIM17EN_W<'_>

Bit 18 - CPU1 TIM17 timer clock enable

pub fn tim16en(&mut self) -> TIM16EN_W<'_>

Bit 17 - CPU1 TIM16 timer clock enable

pub fn usart1en(&mut self) -> USART1EN_W<'_>

Bit 14 - CPU1 USART1clock enable

pub fn spi1en(&mut self) -> SPI1EN_W<'_>

Bit 12 - CPU1 SPI1 clock enable

pub fn tim1en(&mut self) -> TIM1EN_W<'_>

Bit 11 - CPU1 TIM1 timer clock enable

impl W<u32, Reg<u32, _AHB1SMENR>>

pub fn tscsmen(&mut self) -> TSCSMEN_W<'_>

Bit 16 - CPU1 Touch Sensing Controller clocks enable during Sleep and Stop modes

pub fn crcsmen(&mut self) -> CRCSMEN_W<'_>

Bit 12 - CPU1 CRCSMEN

pub fn sram1smen(&mut self) -> SRAM1SMEN_W<'_>

Bit 9 - CPU1 SRAM1 interface clocks enable during Sleep and Stop modes

pub fn dmamuxsmen(&mut self) -> DMAMUXSMEN_W<'_>

Bit 2 - CPU1 DMAMUX clocks enable during Sleep and Stop modes

pub fn dma2smen(&mut self) -> DMA2SMEN_W<'_>

Bit 1 - CPU1 DMA2 clocks enable during Sleep and Stop modes

pub fn dma1smen(&mut self) -> DMA1SMEN_W<'_>

Bit 0 - CPU1 DMA1 clocks enable during Sleep and Stop modes

impl W<u32, Reg<u32, _AHB2SMENR>>

pub fn aes1smen(&mut self) -> AES1SMEN_W<'_>

Bit 16 - CPU1 AES1 accelerator clocks enable during Sleep and Stop modes

pub fn adcfssmen(&mut self) -> ADCFSSMEN_W<'_>

Bit 13 - CPU1 ADC clocks enable during Sleep and Stop modes

pub fn gpiohsmen(&mut self) -> GPIOHSMEN_W<'_>

Bit 7 - CPU1 IO port H clocks enable during Sleep and Stop modes

pub fn gpioesmen(&mut self) -> GPIOESMEN_W<'_>

Bit 4 - CPU1 IO port E clocks enable during Sleep and Stop modes

pub fn gpiodsmen(&mut self) -> GPIODSMEN_W<'_>

Bit 3 - CPU1 IO port D clocks enable during Sleep and Stop modes

pub fn gpiocsmen(&mut self) -> GPIOCSMEN_W<'_>

Bit 2 - CPU1 IO port C clocks enable during Sleep and Stop modes

pub fn gpiobsmen(&mut self) -> GPIOBSMEN_W<'_>

Bit 1 - CPU1 IO port B clocks enable during Sleep and Stop modes

pub fn gpioasmen(&mut self) -> GPIOASMEN_W<'_>

Bit 0 - CPU1 IO port A clocks enable during Sleep and Stop modes

impl W<u32, Reg<u32, _AHB3SMENR>>

pub fn flashsmen(&mut self) -> FLASHSMEN_W<'_>

Bit 25 - Flash interface clocks enable during CPU1 sleep mode

pub fn sram2smen(&mut self) -> SRAM2SMEN_W<'_>

Bit 24 - SRAM2a and SRAM2b memory interface clocks enable during CPU1 sleep mode

pub fn rngsmen(&mut self) -> RNGSMEN_W<'_>

Bit 18 - True RNG clocks enable during CPU1 sleep mode

pub fn aes2smen(&mut self) -> AES2SMEN_W<'_>

Bit 17 - AES2 accelerator clocks enable during CPU1 sleep mode

pub fn pkasmen(&mut self) -> PKASMEN_W<'_>

Bit 16 - PKA accelerator clocks enable during CPU1 sleep mode

pub fn qspismen(&mut self) -> QSPISMEN_W<'_>

Bit 8 - QSPISMEN

impl W<u32, Reg<u32, _APB1SMENR1>>

pub fn lptim1smen(&mut self) -> LPTIM1SMEN_W<'_>

Bit 31 - Low power timer 1 clocks enable during CPU1 Sleep mode

pub fn usbsmen(&mut self) -> USBSMEN_W<'_>

Bit 26 - USB FS clocks enable during CPU1 Sleep mode

pub fn crsmen(&mut self) -> CRSMEN_W<'_>

Bit 24 - CRS clocks enable during CPU1 Sleep mode

pub fn i2c3smen(&mut self) -> I2C3SMEN_W<'_>

Bit 23 - I2C3 clocks enable during CPU1 Sleep mode

pub fn i2c1smen(&mut self) -> I2C1SMEN_W<'_>

Bit 21 - I2C1 clocks enable during CPU1 Sleep mode

pub fn spi2smen(&mut self) -> SPI2SMEN_W<'_>

Bit 14 - SPI2 clocks enable during CPU1 Sleep mode

pub fn wwdgsmen(&mut self) -> WWDGSMEN_W<'_>

Bit 11 - Window watchdog clocks enable during CPU1 Sleep mode

pub fn rtcapbsmen(&mut self) -> RTCAPBSMEN_W<'_>

Bit 10 - RTC APB clocks enable during CPU1 Sleep mode

pub fn lcdsmen(&mut self) -> LCDSMEN_W<'_>

Bit 9 - LCD clocks enable during CPU1 Sleep mode

pub fn tim2smen(&mut self) -> TIM2SMEN_W<'_>

Bit 0 - TIM2 timer clocks enable during CPU1 Sleep mode

impl W<u32, Reg<u32, _APB1SMENR2>>

pub fn lptim2smen(&mut self) -> LPTIM2SMEN_W<'_>

Bit 5 - Low power timer 2 clocks enable during CPU1 Sleep mode

pub fn lpuart1smen(&mut self) -> LPUART1SMEN_W<'_>

Bit 0 - Low power UART 1 clocks enable during CPU1 Sleep mode

impl W<u32, Reg<u32, _APB2SMENR>>

pub fn sai1smen(&mut self) -> SAI1SMEN_W<'_>

Bit 21 - SAI1 clocks enable during CPU1 Sleep mode

pub fn tim17smen(&mut self) -> TIM17SMEN_W<'_>

Bit 18 - TIM17 timer clocks enable during CPU1 Sleep mode

pub fn tim16smen(&mut self) -> TIM16SMEN_W<'_>

Bit 17 - TIM16 timer clocks enable during CPU1 Sleep mode

pub fn usart1smen(&mut self) -> USART1SMEN_W<'_>

Bit 14 - USART1clocks enable during CPU1 Sleep mode

pub fn spi1smen(&mut self) -> SPI1SMEN_W<'_>

Bit 12 - SPI1 clocks enable during CPU1 Sleep mode

pub fn tim1smen(&mut self) -> TIM1SMEN_W<'_>

Bit 11 - TIM1 timer clocks enable during CPU1 Sleep mode

impl W<u32, Reg<u32, _CCIPR>>

pub fn rngsel(&mut self) -> RNGSEL_W<'_>

Bits 30:31 - RNG clock source selection

pub fn adcsel(&mut self) -> ADCSEL_W<'_>

Bits 28:29 - ADCs clock source selection

pub fn clk48sel(&mut self) -> CLK48SEL_W<'_>

Bits 26:27 - 48 MHz clock source selection

pub fn sai1sel(&mut self) -> SAI1SEL_W<'_>

Bits 22:23 - SAI1 clock source selection

pub fn lptim2sel(&mut self) -> LPTIM2SEL_W<'_>

Bits 20:21 - Low power timer 2 clock source selection

pub fn lptim1sel(&mut self) -> LPTIM1SEL_W<'_>

Bits 18:19 - Low power timer 1 clock source selection

pub fn i2c3sel(&mut self) -> I2C3SEL_W<'_>

Bits 16:17 - I2C3 clock source selection

pub fn i2c1sel(&mut self) -> I2C1SEL_W<'_>

Bits 12:13 - I2C1 clock source selection

pub fn lpuart1sel(&mut self) -> LPUART1SEL_W<'_>

Bits 10:11 - LPUART1 clock source selection

pub fn usart1sel(&mut self) -> USART1SEL_W<'_>

Bits 0:1 - USART1 clock source selection

impl W<u32, Reg<u32, _BDCR>>

pub fn lscosel(&mut self) -> LSCOSEL_W<'_>

Bits 25:26 - Low speed clock output selection

pub fn lscoen(&mut self) -> LSCOEN_W<'_>

Bit 24 - Low speed clock output enable

pub fn bdrst(&mut self) -> BDRST_W<'_>

Bit 16 - Backup domain software reset

pub fn rtcen(&mut self) -> RTCEN_W<'_>

Bit 15 - RTC clock enable

pub fn rtcsel(&mut self) -> RTCSEL_W<'_>

Bits 8:9 - RTC clock source selection

pub fn lsecsson(&mut self) -> LSECSSON_W<'_>

Bit 5 - LSECSSON

pub fn lsedrv(&mut self) -> LSEDRV_W<'_>

Bits 3:4 - SE oscillator drive capability

pub fn lsebyp(&mut self) -> LSEBYP_W<'_>

Bit 2 - LSE oscillator bypass

pub fn lseon(&mut self) -> LSEON_W<'_>

Bit 0 - LSE oscillator enable

impl W<u32, Reg<u32, _CSR>>

pub fn rmvf(&mut self) -> RMVF_W<'_>

Bit 23 - Remove reset flag

pub fn rfwkpsel(&mut self) -> RFWKPSEL_W<'_>

Bits 14:15 - RF system wakeup clock source selection

pub fn lsi2bw(&mut self) -> LSI2BW_W<'_>

Bits 8:11 - LSI2 oscillator bias configuration

pub fn lsi2trimen(&mut self) -> LSI2TRIMEN_W<'_>

Bit 4 - LSI2 oscillator trimming enable

pub fn lsi2on(&mut self) -> LSI2ON_W<'_>

Bit 2 - LSI2 oscillator enabled

pub fn lsi1on(&mut self) -> LSI1ON_W<'_>

Bit 0 - LSI1 oscillator enabled

impl W<u32, Reg<u32, _CRRCR>>

pub fn hsi48on(&mut self) -> HSI48ON_W<'_>

Bit 0 - HSI48 oscillator enabled

impl W<u32, Reg<u32, _HSECR>>

pub fn hsegmc(&mut self) -> HSEGMC_W<'_>

Bits 4:6 - HSE current control

pub fn hses(&mut self) -> HSES_W<'_>

Bit 3 - HSE Sense amplifier threshold

pub fn unlocked(&mut self) -> UNLOCKED_W<'_>

Bit 0 - Register lock system

impl W<u32, Reg<u32, _EXTCFGR>>

pub fn c2hpre(&mut self) -> C2HPRE_W<'_>

Bits 4:7 - CPU2 AHB prescaler

pub fn shdhpre(&mut self) -> SHDHPRE_W<'_>

Bits 0:3 - Shared AHB prescaler

impl W<u32, Reg<u32, _C2AHB1ENR>>

pub fn tscen(&mut self) -> TSCEN_W<'_>

Bit 16 - CPU2 Touch Sensing Controller clock enable

pub fn crcen(&mut self) -> CRCEN_W<'_>

Bit 12 - CPU2 CRC clock enable

pub fn sram1en(&mut self) -> SRAM1EN_W<'_>

Bit 9 - CPU2 SRAM1 clock enable

pub fn dmamuxen(&mut self) -> DMAMUXEN_W<'_>

Bit 2 - CPU2 DMAMUX clock enable

pub fn dma2en(&mut self) -> DMA2EN_W<'_>

Bit 1 - CPU2 DMA2 clock enable

pub fn dma1en(&mut self) -> DMA1EN_W<'_>

Bit 0 - CPU2 DMA1 clock enable

impl W<u32, Reg<u32, _C2AHB2ENR>>

pub fn aes1en(&mut self) -> AES1EN_W<'_>

Bit 16 - CPU2 AES1 accelerator clock enable

pub fn adcen(&mut self) -> ADCEN_W<'_>

Bit 13 - CPU2 ADC clock enable

pub fn gpiohen(&mut self) -> GPIOHEN_W<'_>

Bit 7 - CPU2 IO port H clock enable

pub fn gpioeen(&mut self) -> GPIOEEN_W<'_>

Bit 4 - CPU2 IO port E clock enable

pub fn gpioden(&mut self) -> GPIODEN_W<'_>

Bit 3 - CPU2 IO port D clock enable

pub fn gpiocen(&mut self) -> GPIOCEN_W<'_>

Bit 2 - CPU2 IO port C clock enable

pub fn gpioben(&mut self) -> GPIOBEN_W<'_>

Bit 1 - CPU2 IO port B clock enable

pub fn gpioaen(&mut self) -> GPIOAEN_W<'_>

Bit 0 - CPU2 IO port A clock enable

impl W<u32, Reg<u32, _C2AHB3ENR>>

pub fn flashen(&mut self) -> FLASHEN_W<'_>

Bit 25 - CPU2 FLASHEN

pub fn ipccen(&mut self) -> IPCCEN_W<'_>

Bit 20 - CPU2 IPCCEN

pub fn hsemen(&mut self) -> HSEMEN_W<'_>

Bit 19 - CPU2 HSEMEN

pub fn rngen(&mut self) -> RNGEN_W<'_>

Bit 18 - CPU2 RNGEN

pub fn aes2en(&mut self) -> AES2EN_W<'_>

Bit 17 - CPU2 AES2EN

pub fn pkaen(&mut self) -> PKAEN_W<'_>

Bit 16 - CPU2 PKAEN

impl W<u32, Reg<u32, _C2APB1ENR1>>

pub fn lptim1en(&mut self) -> LPTIM1EN_W<'_>

Bit 31 - CPU2 Low power timer 1 clock enable

pub fn usben(&mut self) -> USBEN_W<'_>

Bit 26 - CPU2 USB clock enable

pub fn crsen(&mut self) -> CRSEN_W<'_>

Bit 24 - CPU2 CRS clock enable

pub fn i2c3en(&mut self) -> I2C3EN_W<'_>

Bit 23 - CPU2 I2C3 clock enable

pub fn i2c1en(&mut self) -> I2C1EN_W<'_>

Bit 21 - CPU2 I2C1 clock enable

pub fn spi2en(&mut self) -> SPI2EN_W<'_>

Bit 14 - CPU2 SPI2 clock enable

pub fn rtcapben(&mut self) -> RTCAPBEN_W<'_>

Bit 10 - CPU2 RTC APB clock enable

pub fn lcden(&mut self) -> LCDEN_W<'_>

Bit 9 - CPU2 LCD clock enable

pub fn tim2en(&mut self) -> TIM2EN_W<'_>

Bit 0 - CPU2 TIM2 timer clock enable

impl W<u32, Reg<u32, _C2APB1ENR2>>

pub fn lptim2en(&mut self) -> LPTIM2EN_W<'_>

Bit 5 - CPU2 LPTIM2EN

pub fn lpuart1en(&mut self) -> LPUART1EN_W<'_>

Bit 0 - CPU2 Low power UART 1 clock enable

impl W<u32, Reg<u32, _C2APB2ENR>>

pub fn sai1en(&mut self) -> SAI1EN_W<'_>

Bit 21 - CPU2 SAI1 clock enable

pub fn tim17en(&mut self) -> TIM17EN_W<'_>

Bit 18 - CPU2 TIM17 timer clock enable

pub fn tim16en(&mut self) -> TIM16EN_W<'_>

Bit 17 - CPU2 TIM16 timer clock enable

pub fn usart1en(&mut self) -> USART1EN_W<'_>

Bit 14 - CPU2 USART1clock enable

pub fn spi1en(&mut self) -> SPI1EN_W<'_>

Bit 12 - CPU2 SPI1 clock enable

pub fn tim1en(&mut self) -> TIM1EN_W<'_>

Bit 11 - CPU2 TIM1 timer clock enable

impl W<u32, Reg<u32, _C2APB3ENR>>

pub fn en802(&mut self) -> EN802_W<'_>

Bit 1 - CPU2 802.15.4 interface clock enable

pub fn bleen(&mut self) -> BLEEN_W<'_>

Bit 0 - CPU2 BLE interface clock enable

impl W<u32, Reg<u32, _C2AHB1SMENR>>

pub fn tscsmen(&mut self) -> TSCSMEN_W<'_>

Bit 16 - CPU2 Touch Sensing Controller clocks enable during Sleep and Stop modes

pub fn crcsmen(&mut self) -> CRCSMEN_W<'_>

Bit 12 - CPU2 CRCSMEN

pub fn sram1smen(&mut self) -> SRAM1SMEN_W<'_>

Bit 9 - SRAM1 interface clock enable during CPU1 CSleep mode

pub fn dmamuxsmen(&mut self) -> DMAMUXSMEN_W<'_>

Bit 2 - CPU2 DMAMUX clocks enable during Sleep and Stop modes

pub fn dma2smen(&mut self) -> DMA2SMEN_W<'_>

Bit 1 - CPU2 DMA2 clocks enable during Sleep and Stop modes

pub fn dma1smen(&mut self) -> DMA1SMEN_W<'_>

Bit 0 - CPU2 DMA1 clocks enable during Sleep and Stop modes

impl W<u32, Reg<u32, _C2AHB2SMENR>>

pub fn aes1smen(&mut self) -> AES1SMEN_W<'_>

Bit 16 - CPU2 AES1 accelerator clocks enable during Sleep and Stop modes

pub fn adcfssmen(&mut self) -> ADCFSSMEN_W<'_>

Bit 13 - CPU2 ADC clocks enable during Sleep and Stop modes

pub fn gpiohsmen(&mut self) -> GPIOHSMEN_W<'_>

Bit 7 - CPU2 IO port H clocks enable during Sleep and Stop modes

pub fn gpioesmen(&mut self) -> GPIOESMEN_W<'_>

Bit 4 - CPU2 IO port E clocks enable during Sleep and Stop modes

pub fn gpiodsmen(&mut self) -> GPIODSMEN_W<'_>

Bit 3 - CPU2 IO port D clocks enable during Sleep and Stop modes

pub fn gpiocsmen(&mut self) -> GPIOCSMEN_W<'_>

Bit 2 - CPU2 IO port C clocks enable during Sleep and Stop modes

pub fn gpiobsmen(&mut self) -> GPIOBSMEN_W<'_>

Bit 1 - CPU2 IO port B clocks enable during Sleep and Stop modes

pub fn gpioasmen(&mut self) -> GPIOASMEN_W<'_>

Bit 0 - CPU2 IO port A clocks enable during Sleep and Stop modes

impl W<u32, Reg<u32, _C2AHB3SMENR>>

pub fn flashsmen(&mut self) -> FLASHSMEN_W<'_>

Bit 25 - Flash interface clocks enable during CPU2 sleep modes

pub fn sram2smen(&mut self) -> SRAM2SMEN_W<'_>

Bit 24 - SRAM2a and SRAM2b memory interface clocks enable during CPU2 sleep modes

pub fn rngsmen(&mut self) -> RNGSMEN_W<'_>

Bit 18 - True RNG clocks enable during CPU2 sleep modes

pub fn aes2smen(&mut self) -> AES2SMEN_W<'_>

Bit 17 - AES2 accelerator clocks enable during CPU2 sleep modes

pub fn pkasmen(&mut self) -> PKASMEN_W<'_>

Bit 16 - PKA accelerator clocks enable during CPU2 sleep modes

impl W<u32, Reg<u32, _C2APB1SMENR1>>

pub fn lptim1smen(&mut self) -> LPTIM1SMEN_W<'_>

Bit 31 - Low power timer 1 clocks enable during CPU2 Sleep mode

pub fn usbsmen(&mut self) -> USBSMEN_W<'_>

Bit 26 - USB FS clocks enable during CPU2 Sleep mode

pub fn crsmen(&mut self) -> CRSMEN_W<'_>

Bit 24 - CRS clocks enable during CPU2 Sleep mode

pub fn i2c3smen(&mut self) -> I2C3SMEN_W<'_>

Bit 23 - I2C3 clocks enable during CPU2 Sleep mode

pub fn i2c1smen(&mut self) -> I2C1SMEN_W<'_>

Bit 21 - I2C1 clocks enable during CPU2 Sleep mode

pub fn spi2smen(&mut self) -> SPI2SMEN_W<'_>

Bit 14 - SPI2 clocks enable during CPU2 Sleep mode

pub fn rtcapbsmen(&mut self) -> RTCAPBSMEN_W<'_>

Bit 10 - RTC APB clocks enable during CPU2 Sleep mode

pub fn lcdsmen(&mut self) -> LCDSMEN_W<'_>

Bit 9 - LCD clocks enable during CPU2 Sleep mode

pub fn tim2smen(&mut self) -> TIM2SMEN_W<'_>

Bit 0 - TIM2 timer clocks enable during CPU2 Sleep mode

impl W<u32, Reg<u32, _C2APB1SMENR2>>

pub fn lptim2smen(&mut self) -> LPTIM2SMEN_W<'_>

Bit 5 - Low power timer 2 clocks enable during CPU2 Sleep mode

pub fn lpuart1smen(&mut self) -> LPUART1SMEN_W<'_>

Bit 0 - Low power UART 1 clocks enable during CPU2 Sleep mode

impl W<u32, Reg<u32, _C2APB2SMENR>>

pub fn sai1smen(&mut self) -> SAI1SMEN_W<'_>

Bit 21 - SAI1 clocks enable during CPU2 Sleep mode

pub fn tim17smen(&mut self) -> TIM17SMEN_W<'_>

Bit 18 - TIM17 timer clocks enable during CPU2 Sleep mode

pub fn tim16smen(&mut self) -> TIM16SMEN_W<'_>

Bit 17 - TIM16 timer clocks enable during CPU2 Sleep mode

pub fn usart1smen(&mut self) -> USART1SMEN_W<'_>

Bit 14 - USART1clocks enable during CPU2 Sleep mode

pub fn spi1smen(&mut self) -> SPI1SMEN_W<'_>

Bit 12 - SPI1 clocks enable during CPU2 Sleep mode

pub fn tim1smen(&mut self) -> TIM1SMEN_W<'_>

Bit 11 - TIM1 timer clocks enable during CPU2 Sleep mode

impl W<u32, Reg<u32, _C2APB3SMENR>>

pub fn smen802(&mut self) -> SMEN802_W<'_>

Bit 1 - 802.15.4 interface clocks enable during CPU2 Sleep modes

pub fn blesmen(&mut self) -> BLESMEN_W<'_>

Bit 0 - BLE interface clocks enable during CPU2 Sleep mode

impl W<u32, Reg<u32, _CR1>>

pub fn lpr(&mut self) -> LPR_W<'_>

Bit 14 - Low-power run

pub fn vos(&mut self) -> VOS_W<'_>

Bits 9:10 - Voltage scaling range selection

pub fn dbp(&mut self) -> DBP_W<'_>

Bit 8 - Disable backup domain write protection

pub fn fpds(&mut self) -> FPDS_W<'_>

Bit 5 - Flash power down mode during LPsSleep for CPU1

pub fn fpdr(&mut self) -> FPDR_W<'_>

Bit 4 - Flash power down mode during LPRun for CPU1

pub fn lpms(&mut self) -> LPMS_W<'_>

Bits 0:2 - Low-power mode selection for CPU1

impl W<u32, Reg<u32, _CR2>>

pub fn usv(&mut self) -> USV_W<'_>

Bit 10 - VDDUSB USB supply valid

pub fn pvme3(&mut self) -> PVME3_W<'_>

Bit 6 - Peripheral voltage monitoring 3 enable: VDDA vs. 1.62V

pub fn pvme1(&mut self) -> PVME1_W<'_>

Bit 4 - Peripheral voltage monitoring 1 enable: VDDUSB vs. 1.2V

pub fn pls(&mut self) -> PLS_W<'_>

Bits 1:3 - Power voltage detector level selection

pub fn pvde(&mut self) -> PVDE_W<'_>

Bit 0 - Power voltage detector enable

impl W<u32, Reg<u32, _CR3>>

pub fn eiwul(&mut self) -> EIWUL_W<'_>

Bit 15 - Enable internal wakeup line for CPU1

pub fn ec2h(&mut self) -> EC2H_W<'_>

Bit 14 - Enable CPU2 Hold interrupt for CPU1

pub fn e802a(&mut self) -> E802A_W<'_>

Bit 13 - Enable end of activity interrupt for CPU1

pub fn eblea(&mut self) -> EBLEA_W<'_>

Bit 11 - Enable BLE end of activity interrupt for CPU1

pub fn ecrpe(&mut self) -> ECRPE_W<'_>

Bit 12 - Enable critical radio phase end of activity interrupt for CPU1

pub fn apc(&mut self) -> APC_W<'_>

Bit 10 - Apply pull-up and pull-down configuration

pub fn rrs(&mut self) -> RRS_W<'_>

Bit 9 - SRAM2a retention in Standby mode

pub fn eborhsdfb(&mut self) -> EBORHSDFB_W<'_>

Bit 8 - Enable BORH and Step Down counverter forced in Bypass interrups for CPU1

pub fn ewup5(&mut self) -> EWUP5_W<'_>

Bit 4 - Enable Wakeup pin WKUP5

pub fn ewup4(&mut self) -> EWUP4_W<'_>

Bit 3 - Enable Wakeup pin WKUP4

pub fn ewup3(&mut self) -> EWUP3_W<'_>

Bit 2 - Enable Wakeup pin WKUP3

pub fn ewup2(&mut self) -> EWUP2_W<'_>

Bit 1 - Enable Wakeup pin WKUP2

pub fn ewup1(&mut self) -> EWUP1_W<'_>

Bit 0 - Enable Wakeup pin WKUP1

impl W<u32, Reg<u32, _CR4>>

pub fn c2boot(&mut self) -> C2BOOT_W<'_>

Bit 15 - BOOT CPU2 after reset or wakeup from Stop or Standby modes

pub fn vbrs(&mut self) -> VBRS_W<'_>

Bit 9 - VBAT battery charging resistor selection

pub fn vbe(&mut self) -> VBE_W<'_>

Bit 8 - VBAT battery charging enable

pub fn wp5(&mut self) -> WP5_W<'_>

Bit 4 - Wakeup pin WKUP5 polarity

pub fn wp4(&mut self) -> WP4_W<'_>

Bit 3 - Wakeup pin WKUP4 polarity

pub fn wp3(&mut self) -> WP3_W<'_>

Bit 2 - Wakeup pin WKUP3 polarity

pub fn wp2(&mut self) -> WP2_W<'_>

Bit 1 - Wakeup pin WKUP2 polarity

pub fn wp1(&mut self) -> WP1_W<'_>

Bit 0 - Wakeup pin WKUP1 polarity

impl W<u32, Reg<u32, _SCR>>

pub fn cc2hf(&mut self) -> CC2HF_W<'_>

Bit 14 - Clear CPU2 Hold interrupt flag

pub fn c802af(&mut self) -> C802AF_W<'_>

Bit 13 - Clear 802.15.4 end of activity interrupt flag

pub fn cbleaf(&mut self) -> CBLEAF_W<'_>

Bit 12 - Clear BLE end of activity interrupt flag

pub fn ccrpef(&mut self) -> CCRPEF_W<'_>

Bit 11 - Clear critical radio phase end of activity interrupt flag

pub fn c802wuf(&mut self) -> C802WUF_W<'_>

Bit 10 - Clear 802.15.4 wakeup interrupt flag

pub fn cblewuf(&mut self) -> CBLEWUF_W<'_>

Bit 9 - Clear BLE wakeup interrupt flag

pub fn cborhf(&mut self) -> CBORHF_W<'_>

Bit 8 - Clear BORH interrupt flag

pub fn csmpsfbf(&mut self) -> CSMPSFBF_W<'_>

Bit 7 - Clear SMPS Step Down converter forced in Bypass interrupt flag

pub fn cwuf5(&mut self) -> CWUF5_W<'_>

Bit 4 - Clear wakeup flag 5

pub fn cwuf4(&mut self) -> CWUF4_W<'_>

Bit 3 - Clear wakeup flag 4

pub fn cwuf3(&mut self) -> CWUF3_W<'_>

Bit 2 - Clear wakeup flag 3

pub fn cwuf2(&mut self) -> CWUF2_W<'_>

Bit 1 - Clear wakeup flag 2

pub fn cwuf1(&mut self) -> CWUF1_W<'_>

Bit 0 - Clear wakeup flag 1

impl W<u32, Reg<u32, _CR5>>

pub fn sdeb(&mut self) -> SDEB_W<'_>

Bit 15 - Enable Step Down converter SMPS mode enabled

pub fn sdben(&mut self) -> SDBEN_W<'_>

Bit 14 - Enable Step Down converter Bypass mode enabled

pub fn smpscfg(&mut self) -> SMPSCFG_W<'_>

Bit 9 - VOS configuration selection (non user)

pub fn borhc(&mut self) -> BORHC_W<'_>

Bit 8 - BORH configuration selection

pub fn sdsc(&mut self) -> SDSC_W<'_>

Bits 4:6 - Step Down converter supplt startup current selection

pub fn sdvos(&mut self) -> SDVOS_W<'_>

Bits 0:3 - Step Down converter voltage output scaling

impl W<u32, Reg<u32, _PUCRA>>

pub fn pu15(&mut self) -> PU15_W<'_>

Bit 15 - Port A pull-up bit y (y=0..15)

pub fn pu13(&mut self) -> PU13_W<'_>

Bit 13 - Port A pull-up bit y (y=0..15)

pub fn pu12(&mut self) -> PU12_W<'_>

Bit 12 - Port A pull-up bit y (y=0..15)

pub fn pu11(&mut self) -> PU11_W<'_>

Bit 11 - Port A pull-up bit y (y=0..15)

pub fn pu10(&mut self) -> PU10_W<'_>

Bit 10 - Port A pull-up bit y (y=0..15)

pub fn pu9(&mut self) -> PU9_W<'_>

Bit 9 - Port A pull-up bit y (y=0..15)

pub fn pu8(&mut self) -> PU8_W<'_>

Bit 8 - Port A pull-up bit y (y=0..15)

pub fn pu7(&mut self) -> PU7_W<'_>

Bit 7 - Port A pull-up bit y (y=0..15)

pub fn pu6(&mut self) -> PU6_W<'_>

Bit 6 - Port A pull-up bit y (y=0..15)

pub fn pu5(&mut self) -> PU5_W<'_>

Bit 5 - Port A pull-up bit y (y=0..15)

pub fn pu4(&mut self) -> PU4_W<'_>

Bit 4 - Port A pull-up bit y (y=0..15)

pub fn pu3(&mut self) -> PU3_W<'_>

Bit 3 - Port A pull-up bit y (y=0..15)

pub fn pu2(&mut self) -> PU2_W<'_>

Bit 2 - Port A pull-up bit y (y=0..15)

pub fn pu1(&mut self) -> PU1_W<'_>

Bit 1 - Port A pull-up bit y (y=0..15)

pub fn pu0(&mut self) -> PU0_W<'_>

Bit 0 - Port A pull-up bit y (y=0..15)

impl W<u32, Reg<u32, _PDCRA>>

pub fn pd14(&mut self) -> PD14_W<'_>

Bit 14 - Port A pull-down bit y (y=0..15)

pub fn pd12(&mut self) -> PD12_W<'_>

Bit 12 - Port A pull-down bit y (y=0..15)

pub fn pd11(&mut self) -> PD11_W<'_>

Bit 11 - Port A pull-down bit y (y=0..15)

pub fn pd10(&mut self) -> PD10_W<'_>

Bit 10 - Port A pull-down bit y (y=0..15)

pub fn pd9(&mut self) -> PD9_W<'_>

Bit 9 - Port A pull-down bit y (y=0..15)

pub fn pd8(&mut self) -> PD8_W<'_>

Bit 8 - Port A pull-down bit y (y=0..15)

pub fn pd7(&mut self) -> PD7_W<'_>

Bit 7 - Port A pull-down bit y (y=0..15)

pub fn pd6(&mut self) -> PD6_W<'_>

Bit 6 - Port A pull-down bit y (y=0..15)

pub fn pd5(&mut self) -> PD5_W<'_>

Bit 5 - Port A pull-down bit y (y=0..15)

pub fn pd4(&mut self) -> PD4_W<'_>

Bit 4 - Port A pull-down bit y (y=0..15)

pub fn pd3(&mut self) -> PD3_W<'_>

Bit 3 - Port A pull-down bit y (y=0..15)

pub fn pd2(&mut self) -> PD2_W<'_>

Bit 2 - Port A pull-down bit y (y=0..15)

pub fn pd1(&mut self) -> PD1_W<'_>

Bit 1 - Port A pull-down bit y (y=0..15)

pub fn pd0(&mut self) -> PD0_W<'_>

Bit 0 - Port A pull-down bit y (y=0..15)

impl W<u32, Reg<u32, _PUCRB>>

pub fn pu15(&mut self) -> PU15_W<'_>

Bit 15 - Port B pull-up bit y (y=0..15)

pub fn pu14(&mut self) -> PU14_W<'_>

Bit 14 - Port B pull-up bit y (y=0..15)

pub fn pu13(&mut self) -> PU13_W<'_>

Bit 13 - Port B pull-up bit y (y=0..15)

pub fn pu12(&mut self) -> PU12_W<'_>

Bit 12 - Port B pull-up bit y (y=0..15)

pub fn pu11(&mut self) -> PU11_W<'_>

Bit 11 - Port B pull-up bit y (y=0..15)

pub fn pu10(&mut self) -> PU10_W<'_>

Bit 10 - Port B pull-up bit y (y=0..15)

pub fn pu9(&mut self) -> PU9_W<'_>

Bit 9 - Port B pull-up bit y (y=0..15)

pub fn pu8(&mut self) -> PU8_W<'_>

Bit 8 - Port B pull-up bit y (y=0..15)

pub fn pu7(&mut self) -> PU7_W<'_>

Bit 7 - Port B pull-up bit y (y=0..15)

pub fn pu6(&mut self) -> PU6_W<'_>

Bit 6 - Port B pull-up bit y (y=0..15)

pub fn pu5(&mut self) -> PU5_W<'_>

Bit 5 - Port B pull-up bit y (y=0..15)

pub fn pu4(&mut self) -> PU4_W<'_>

Bit 4 - Port B pull-up bit y (y=0..15)

pub fn pu3(&mut self) -> PU3_W<'_>

Bit 3 - Port B pull-up bit y (y=0..15)

pub fn pu2(&mut self) -> PU2_W<'_>

Bit 2 - Port B pull-up bit y (y=0..15)

pub fn pu1(&mut self) -> PU1_W<'_>

Bit 1 - Port B pull-up bit y (y=0..15)

pub fn pu0(&mut self) -> PU0_W<'_>

Bit 0 - Port B pull-up bit y (y=0..15)

impl W<u32, Reg<u32, _PDCRB>>

pub fn pd15(&mut self) -> PD15_W<'_>

Bit 15 - Port B pull-down bit y (y=0..15)

pub fn pd14(&mut self) -> PD14_W<'_>

Bit 14 - Port B pull-down bit y (y=0..15)

pub fn pd13(&mut self) -> PD13_W<'_>

Bit 13 - Port B pull-down bit y (y=0..15)

pub fn pd12(&mut self) -> PD12_W<'_>

Bit 12 - Port B pull-down bit y (y=0..15)

pub fn pd11(&mut self) -> PD11_W<'_>

Bit 11 - Port B pull-down bit y (y=0..15)

pub fn pd10(&mut self) -> PD10_W<'_>

Bit 10 - Port B pull-down bit y (y=0..15)

pub fn pd9(&mut self) -> PD9_W<'_>

Bit 9 - Port B pull-down bit y (y=0..15)

pub fn pd8(&mut self) -> PD8_W<'_>

Bit 8 - Port B pull-down bit y (y=0..15)

pub fn pd7(&mut self) -> PD7_W<'_>

Bit 7 - Port B pull-down bit y (y=0..15)

pub fn pd6(&mut self) -> PD6_W<'_>

Bit 6 - Port B pull-down bit y (y=0..15)

pub fn pd5(&mut self) -> PD5_W<'_>

Bit 5 - Port B pull-down bit y (y=0..15)

pub fn pd3(&mut self) -> PD3_W<'_>

Bit 3 - Port B pull-down bit y (y=0..15)

pub fn pd2(&mut self) -> PD2_W<'_>

Bit 2 - Port B pull-down bit y (y=0..15)

pub fn pd1(&mut self) -> PD1_W<'_>

Bit 1 - Port B pull-down bit y (y=0..15)

pub fn pd0(&mut self) -> PD0_W<'_>

Bit 0 - Port B pull-down bit y (y=0..15)

impl W<u32, Reg<u32, _PUCRC>>

pub fn pu15(&mut self) -> PU15_W<'_>

Bit 15 - Port C pull-up bit y (y=0..15)

pub fn pu14(&mut self) -> PU14_W<'_>

Bit 14 - Port C pull-up bit y (y=0..15)

pub fn pu13(&mut self) -> PU13_W<'_>

Bit 13 - Port C pull-up bit y (y=0..15)

pub fn pu12(&mut self) -> PU12_W<'_>

Bit 12 - Port C pull-up bit y (y=0..15)

pub fn pu11(&mut self) -> PU11_W<'_>

Bit 11 - Port C pull-up bit y (y=0..15)

pub fn pu10(&mut self) -> PU10_W<'_>

Bit 10 - Port C pull-up bit y (y=0..15)

pub fn pu9(&mut self) -> PU9_W<'_>

Bit 9 - Port C pull-up bit y (y=0..15)

pub fn pu8(&mut self) -> PU8_W<'_>

Bit 8 - Port C pull-up bit y (y=0..15)

pub fn pu7(&mut self) -> PU7_W<'_>

Bit 7 - Port C pull-up bit y (y=0..15)

pub fn pu6(&mut self) -> PU6_W<'_>

Bit 6 - Port C pull-up bit y (y=0..15)

pub fn pu5(&mut self) -> PU5_W<'_>

Bit 5 - Port C pull-up bit y (y=0..15)

pub fn pu4(&mut self) -> PU4_W<'_>

Bit 4 - Port C pull-up bit y (y=0..15)

pub fn pu3(&mut self) -> PU3_W<'_>

Bit 3 - Port C pull-up bit y (y=0..15)

pub fn pu2(&mut self) -> PU2_W<'_>

Bit 2 - Port C pull-up bit y (y=0..15)

pub fn pu1(&mut self) -> PU1_W<'_>

Bit 1 - Port C pull-up bit y (y=0..15)

pub fn pu0(&mut self) -> PU0_W<'_>

Bit 0 - Port C pull-up bit y (y=0..15)

impl W<u32, Reg<u32, _PDCRC>>

pub fn pd15(&mut self) -> PD15_W<'_>

Bit 15 - Port C pull-down bit y (y=0..15)

pub fn pd14(&mut self) -> PD14_W<'_>

Bit 14 - Port C pull-down bit y (y=0..15)

pub fn pd13(&mut self) -> PD13_W<'_>

Bit 13 - Port C pull-down bit y (y=0..15)

pub fn pd12(&mut self) -> PD12_W<'_>

Bit 12 - Port C pull-down bit y (y=0..15)

pub fn pd11(&mut self) -> PD11_W<'_>

Bit 11 - Port C pull-down bit y (y=0..15)

pub fn pd10(&mut self) -> PD10_W<'_>

Bit 10 - Port C pull-down bit y (y=0..15)

pub fn pd9(&mut self) -> PD9_W<'_>

Bit 9 - Port C pull-down bit y (y=0..15)

pub fn pd8(&mut self) -> PD8_W<'_>

Bit 8 - Port C pull-down bit y (y=0..15)

pub fn pd7(&mut self) -> PD7_W<'_>

Bit 7 - Port C pull-down bit y (y=0..15)

pub fn pd6(&mut self) -> PD6_W<'_>

Bit 6 - Port C pull-down bit y (y=0..15)

pub fn pd5(&mut self) -> PD5_W<'_>

Bit 5 - Port C pull-down bit y (y=0..15)

pub fn pd4(&mut self) -> PD4_W<'_>

Bit 4 - Port C pull-down bit y (y=0..15)

pub fn pd3(&mut self) -> PD3_W<'_>

Bit 3 - Port C pull-down bit y (y=0..15)

pub fn pd2(&mut self) -> PD2_W<'_>

Bit 2 - Port C pull-down bit y (y=0..15)

pub fn pd1(&mut self) -> PD1_W<'_>

Bit 1 - Port C pull-down bit y (y=0..15)

pub fn pd0(&mut self) -> PD0_W<'_>

Bit 0 - Port C pull-down bit y (y=0..15)

impl W<u32, Reg<u32, _PUCRD>>

pub fn pu15(&mut self) -> PU15_W<'_>

Bit 15 - Port D pull-up bit y (y=0..15)

pub fn pu14(&mut self) -> PU14_W<'_>

Bit 14 - Port D pull-up bit y (y=0..15)

pub fn pu13(&mut self) -> PU13_W<'_>

Bit 13 - Port D pull-up bit y (y=0..15)

pub fn pu12(&mut self) -> PU12_W<'_>

Bit 12 - Port D pull-up bit y (y=0..15)

pub fn pu11(&mut self) -> PU11_W<'_>

Bit 11 - Port D pull-up bit y (y=0..15)

pub fn pu10(&mut self) -> PU10_W<'_>

Bit 10 - Port D pull-up bit y (y=0..15)

pub fn pu9(&mut self) -> PU9_W<'_>

Bit 9 - Port D pull-up bit y (y=0..15)

pub fn pu8(&mut self) -> PU8_W<'_>

Bit 8 - Port D pull-up bit y (y=0..15)

pub fn pu7(&mut self) -> PU7_W<'_>

Bit 7 - Port D pull-up bit y (y=0..15)

pub fn pu6(&mut self) -> PU6_W<'_>

Bit 6 - Port D pull-up bit y (y=0..15)

pub fn pu5(&mut self) -> PU5_W<'_>

Bit 5 - Port D pull-up bit y (y=0..15)

pub fn pu4(&mut self) -> PU4_W<'_>

Bit 4 - Port D pull-up bit y (y=0..15)

pub fn pu3(&mut self) -> PU3_W<'_>

Bit 3 - Port D pull-up bit y (y=0..15)

pub fn pu2(&mut self) -> PU2_W<'_>

Bit 2 - Port D pull-up bit y (y=0..15)

pub fn pu1(&mut self) -> PU1_W<'_>

Bit 1 - Port D pull-up bit y (y=0..15)

pub fn pu0(&mut self) -> PU0_W<'_>

Bit 0 - Port D pull-up bit y (y=0..15)

impl W<u32, Reg<u32, _PDCRD>>

pub fn pd15(&mut self) -> PD15_W<'_>

Bit 15 - Port D pull-down bit y (y=0..15)

pub fn pd14(&mut self) -> PD14_W<'_>

Bit 14 - Port D pull-down bit y (y=0..15)

pub fn pd13(&mut self) -> PD13_W<'_>

Bit 13 - Port D pull-down bit y (y=0..15)

pub fn pd12(&mut self) -> PD12_W<'_>

Bit 12 - Port D pull-down bit y (y=0..15)

pub fn pd11(&mut self) -> PD11_W<'_>

Bit 11 - Port D pull-down bit y (y=0..15)

pub fn pd10(&mut self) -> PD10_W<'_>

Bit 10 - Port D pull-down bit y (y=0..15)

pub fn pd9(&mut self) -> PD9_W<'_>

Bit 9 - Port D pull-down bit y (y=0..15)

pub fn pd8(&mut self) -> PD8_W<'_>

Bit 8 - Port D pull-down bit y (y=0..15)

pub fn pd7(&mut self) -> PD7_W<'_>

Bit 7 - Port D pull-down bit y (y=0..15)

pub fn pd6(&mut self) -> PD6_W<'_>

Bit 6 - Port D pull-down bit y (y=0..15)

pub fn pd5(&mut self) -> PD5_W<'_>

Bit 5 - Port D pull-down bit y (y=0..15)

pub fn pd4(&mut self) -> PD4_W<'_>

Bit 4 - Port D pull-down bit y (y=0..15)

pub fn pd3(&mut self) -> PD3_W<'_>

Bit 3 - Port D pull-down bit y (y=0..15)

pub fn pd2(&mut self) -> PD2_W<'_>

Bit 2 - Port D pull-down bit y (y=0..15)

pub fn pd1(&mut self) -> PD1_W<'_>

Bit 1 - Port D pull-down bit y (y=0..15)

pub fn pd0(&mut self) -> PD0_W<'_>

Bit 0 - Port D pull-down bit y (y=0..15)

impl W<u32, Reg<u32, _PUCRE>>

pub fn pu4(&mut self) -> PU4_W<'_>

Bit 4 - Port E pull-up bit y (y=0..15)

pub fn pu3(&mut self) -> PU3_W<'_>

Bit 3 - Port E pull-up bit y (y=0..15)

pub fn pu2(&mut self) -> PU2_W<'_>

Bit 2 - Port E pull-up bit y (y=0..15)

pub fn pu1(&mut self) -> PU1_W<'_>

Bit 1 - Port E pull-up bit y (y=0..15)

pub fn pu0(&mut self) -> PU0_W<'_>

Bit 0 - Port E pull-up bit y (y=0..15)

impl W<u32, Reg<u32, _PDCRE>>

pub fn pd4(&mut self) -> PD4_W<'_>

Bit 4 - Port E pull-down bit y (y=0..15)

pub fn pd3(&mut self) -> PD3_W<'_>

Bit 3 - Port E pull-down bit y (y=0..15)

pub fn pd2(&mut self) -> PD2_W<'_>

Bit 2 - Port E pull-down bit y (y=0..15)

pub fn pd1(&mut self) -> PD1_W<'_>

Bit 1 - Port E pull-down bit y (y=0..15)

pub fn pd0(&mut self) -> PD0_W<'_>

Bit 0 - Port E pull-down bit y (y=0..15)

impl W<u32, Reg<u32, _PUCRH>>

pub fn pu3(&mut self) -> PU3_W<'_>

Bit 3 - Port H pull-up bit y (y=0..1)

pub fn pu1(&mut self) -> PU1_W<'_>

Bit 1 - Port H pull-up bit y (y=0..1)

pub fn pu0(&mut self) -> PU0_W<'_>

Bit 0 - Port H pull-up bit y (y=0..1)

impl W<u32, Reg<u32, _PDCRH>>

pub fn pd3(&mut self) -> PD3_W<'_>

Bit 3 - Port H pull-down bit y (y=0..1)

pub fn pd1(&mut self) -> PD1_W<'_>

Bit 1 - Port H pull-down bit y (y=0..1)

pub fn pd0(&mut self) -> PD0_W<'_>

Bit 0 - Port H pull-down bit y (y=0..1)

impl W<u32, Reg<u32, _C2CR1>>

pub fn _802ewkup(&mut self) -> _802EWKUP_W<'_>

Bit 15 - 802.15.4 external wakeup signal

pub fn bleewkup(&mut self) -> BLEEWKUP_W<'_>

Bit 14 - BLE external wakeup signal

pub fn fpds(&mut self) -> FPDS_W<'_>

Bit 5 - Flash power down mode during LPSleep for CPU2

pub fn fpdr(&mut self) -> FPDR_W<'_>

Bit 4 - Flash power down mode during LPRun for CPU2

pub fn lpms(&mut self) -> LPMS_W<'_>

Bits 0:2 - Low-power mode selection for CPU2

impl W<u32, Reg<u32, _C2CR3>>

pub fn eiwul(&mut self) -> EIWUL_W<'_>

Bit 15 - Enable internal wakeup line for CPU2

pub fn apc(&mut self) -> APC_W<'_>

Bit 12 - Apply pull-up and pull-down configuration for CPU2

pub fn e802wup(&mut self) -> E802WUP_W<'_>

Bit 10 - Enable 802.15.4 host wakeup interrupt for CPU2

pub fn eblewup(&mut self) -> EBLEWUP_W<'_>

Bit 9 - Enable BLE host wakeup interrupt for CPU2

pub fn ewup5(&mut self) -> EWUP5_W<'_>

Bit 4 - Enable Wakeup pin WKUP5 for CPU2

pub fn ewup4(&mut self) -> EWUP4_W<'_>

Bit 3 - Enable Wakeup pin WKUP4 for CPU2

pub fn ewup3(&mut self) -> EWUP3_W<'_>

Bit 2 - Enable Wakeup pin WKUP3 for CPU2

pub fn ewup2(&mut self) -> EWUP2_W<'_>

Bit 1 - Enable Wakeup pin WKUP2 for CPU2

pub fn ewup1(&mut self) -> EWUP1_W<'_>

Bit 0 - Enable Wakeup pin WKUP1 for CPU2

impl W<u32, Reg<u32, _EXTSCR>>

pub fn ccrpf(&mut self) -> CCRPF_W<'_>

Bit 2 - Clear Critical Radio system phase

pub fn c2cssf(&mut self) -> C2CSSF_W<'_>

Bit 1 - Clear CPU2 Stop Standby flags

pub fn c1cssf(&mut self) -> C1CSSF_W<'_>

Bit 0 - Clear CPU1 Stop Standby flags

impl W<u32, Reg<u32, _MEMRMP>>

pub fn mem_mode(&mut self) -> MEM_MODE_W<'_>

Bits 0:2 - Memory mapping selection

impl W<u32, Reg<u32, _CFGR1>>

pub fn fpu_ie(&mut self) -> FPU_IE_W<'_>

Bits 26:31 - Floating Point Unit interrupts enable bits

pub fn i2c3_fmp(&mut self) -> I2C3_FMP_W<'_>

Bit 22 - I2C3 Fast-mode Plus driving capability activation

pub fn i2c1_fmp(&mut self) -> I2C1_FMP_W<'_>

Bit 20 - I2C1 Fast-mode Plus driving capability activation

pub fn i2c_pb9_fmp(&mut self) -> I2C_PB9_FMP_W<'_>

Bit 19 - Fast-mode Plus (Fm+) driving capability activation on PB9

pub fn i2c_pb8_fmp(&mut self) -> I2C_PB8_FMP_W<'_>

Bit 18 - Fast-mode Plus (Fm+) driving capability activation on PB8

pub fn i2c_pb7_fmp(&mut self) -> I2C_PB7_FMP_W<'_>

Bit 17 - Fast-mode Plus (Fm+) driving capability activation on PB7

pub fn i2c_pb6_fmp(&mut self) -> I2C_PB6_FMP_W<'_>

Bit 16 - Fast-mode Plus (Fm+) driving capability activation on PB6

pub fn boosten(&mut self) -> BOOSTEN_W<'_>

Bit 8 - I/O analog switch voltage booster enable

impl W<u32, Reg<u32, _EXTICR1>>

pub fn exti3(&mut self) -> EXTI3_W<'_>

Bits 12:14 - EXTI 3 configuration bits

pub fn exti2(&mut self) -> EXTI2_W<'_>

Bits 8:10 - EXTI 2 configuration bits

pub fn exti1(&mut self) -> EXTI1_W<'_>

Bits 4:6 - EXTI 1 configuration bits

pub fn exti0(&mut self) -> EXTI0_W<'_>

Bits 0:2 - EXTI 0 configuration bits

impl W<u32, Reg<u32, _EXTICR2>>

pub fn exti7(&mut self) -> EXTI7_W<'_>

Bits 12:14 - EXTI 7 configuration bits

pub fn exti6(&mut self) -> EXTI6_W<'_>

Bits 8:10 - EXTI 6 configuration bits

pub fn exti5(&mut self) -> EXTI5_W<'_>

Bits 4:6 - EXTI 5 configuration bits

pub fn exti4(&mut self) -> EXTI4_W<'_>

Bits 0:2 - EXTI 4 configuration bits

impl W<u32, Reg<u32, _EXTICR3>>

pub fn exti11(&mut self) -> EXTI11_W<'_>

Bits 12:14 - EXTI 11 configuration bits

pub fn exti10(&mut self) -> EXTI10_W<'_>

Bits 8:10 - EXTI 10 configuration bits

pub fn exti9(&mut self) -> EXTI9_W<'_>

Bits 4:6 - EXTI 9 configuration bits

pub fn exti8(&mut self) -> EXTI8_W<'_>

Bits 0:2 - EXTI 8 configuration bits

impl W<u32, Reg<u32, _EXTICR4>>

pub fn exti15(&mut self) -> EXTI15_W<'_>

Bits 12:14 - EXTI15 configuration bits

pub fn exti14(&mut self) -> EXTI14_W<'_>

Bits 8:10 - EXTI14 configuration bits

pub fn exti13(&mut self) -> EXTI13_W<'_>

Bits 4:6 - EXTI13 configuration bits

pub fn exti12(&mut self) -> EXTI12_W<'_>

Bits 0:2 - EXTI12 configuration bits

impl W<u32, Reg<u32, _SCSR>>

pub fn sram2er(&mut self) -> SRAM2ER_W<'_>

Bit 0 - SRAM2 Erase

pub fn c2rfd(&mut self) -> C2RFD_W<'_>

Bit 31 - CPU2 SRAM fetch (execution) disable.

impl W<u32, Reg<u32, _CFGR2>>

pub fn spf(&mut self) -> SPF_W<'_>

Bit 8 - SRAM2 parity error flag

pub fn eccl(&mut self) -> ECCL_W<'_>

Bit 3 - ECC Lock

pub fn pvdl(&mut self) -> PVDL_W<'_>

Bit 2 - PVD lock enable bit

pub fn spl(&mut self) -> SPL_W<'_>

Bit 1 - SRAM2 parity lock bit

pub fn cll(&mut self) -> CLL_W<'_>

Bit 0 - Cortex-M4 LOCKUP (Hardfault) output enable bit

impl W<u32, Reg<u32, _SWPR>>

pub fn p31wp(&mut self) -> P31WP_W<'_>

Bit 31 - SRAM2 page 31 write protection

pub fn p30wp(&mut self) -> P30WP_W<'_>

Bit 30 - P30WP

pub fn p29wp(&mut self) -> P29WP_W<'_>

Bit 29 - P29WP

pub fn p28wp(&mut self) -> P28WP_W<'_>

Bit 28 - P28WP

pub fn p27wp(&mut self) -> P27WP_W<'_>

Bit 27 - P27WP

pub fn p26wp(&mut self) -> P26WP_W<'_>

Bit 26 - P26WP

pub fn p25wp(&mut self) -> P25WP_W<'_>

Bit 25 - P25WP

pub fn p24wp(&mut self) -> P24WP_W<'_>

Bit 24 - P24WP

pub fn p23wp(&mut self) -> P23WP_W<'_>

Bit 23 - P23WP

pub fn p22wp(&mut self) -> P22WP_W<'_>

Bit 22 - P22WP

pub fn p21wp(&mut self) -> P21WP_W<'_>

Bit 21 - P21WP

pub fn p20wp(&mut self) -> P20WP_W<'_>

Bit 20 - P20WP

pub fn p19wp(&mut self) -> P19WP_W<'_>

Bit 19 - P19WP

pub fn p18wp(&mut self) -> P18WP_W<'_>

Bit 18 - P18WP

pub fn p17wp(&mut self) -> P17WP_W<'_>

Bit 17 - P17WP

pub fn p16wp(&mut self) -> P16WP_W<'_>

Bit 16 - P16WP

pub fn p15wp(&mut self) -> P15WP_W<'_>

Bit 15 - P15WP

pub fn p14wp(&mut self) -> P14WP_W<'_>

Bit 14 - P14WP

pub fn p13wp(&mut self) -> P13WP_W<'_>

Bit 13 - P13WP

pub fn p12wp(&mut self) -> P12WP_W<'_>

Bit 12 - P12WP

pub fn p11wp(&mut self) -> P11WP_W<'_>

Bit 11 - P11WP

pub fn p10wp(&mut self) -> P10WP_W<'_>

Bit 10 - P10WP

pub fn p9wp(&mut self) -> P9WP_W<'_>

Bit 9 - P9WP

pub fn p8wp(&mut self) -> P8WP_W<'_>

Bit 8 - P8WP

pub fn p7wp(&mut self) -> P7WP_W<'_>

Bit 7 - P7WP

pub fn p6wp(&mut self) -> P6WP_W<'_>

Bit 6 - P6WP

pub fn p5wp(&mut self) -> P5WP_W<'_>

Bit 5 - P5WP

pub fn p4wp(&mut self) -> P4WP_W<'_>

Bit 4 - P4WP

pub fn p3wp(&mut self) -> P3WP_W<'_>

Bit 3 - P3WP

pub fn p2wp(&mut self) -> P2WP_W<'_>

Bit 2 - P2WP

pub fn p1wp(&mut self) -> P1WP_W<'_>

Bit 1 - P1WP

pub fn p0wp(&mut self) -> P0WP_W<'_>

Bit 0 - P0WP

impl W<u32, Reg<u32, _SKR>>

pub fn key(&mut self) -> KEY_W<'_>

Bits 0:7 - SRAM2 write protection key for software erase

impl W<u32, Reg<u32, _SWPR2>>

pub fn p63wp(&mut self) -> P63WP_W<'_>

Bit 31 - SRAM2 page 63 write protection

pub fn p62wp(&mut self) -> P62WP_W<'_>

Bit 30 - P62WP

pub fn p61wp(&mut self) -> P61WP_W<'_>

Bit 29 - P61WP

pub fn p60wp(&mut self) -> P60WP_W<'_>

Bit 28 - P60WP

pub fn p59wp(&mut self) -> P59WP_W<'_>

Bit 27 - P59WP

pub fn p58wp(&mut self) -> P58WP_W<'_>

Bit 26 - P58WP

pub fn p57wp(&mut self) -> P57WP_W<'_>

Bit 25 - P57WP

pub fn p56wp(&mut self) -> P56WP_W<'_>

Bit 24 - P56WP

pub fn p55wp(&mut self) -> P55WP_W<'_>

Bit 23 - P55WP

pub fn p54wp(&mut self) -> P54WP_W<'_>

Bit 22 - P54WP

pub fn p53wp(&mut self) -> P53WP_W<'_>

Bit 21 - P53WP

pub fn p52wp(&mut self) -> P52WP_W<'_>

Bit 20 - P52WP

pub fn p51wp(&mut self) -> P51WP_W<'_>

Bit 19 - P51WP

pub fn p50wp(&mut self) -> P50WP_W<'_>

Bit 18 - P50WP

pub fn p49wp(&mut self) -> P49WP_W<'_>

Bit 17 - P49WP

pub fn p48wp(&mut self) -> P48WP_W<'_>

Bit 16 - P48WP

pub fn p47wp(&mut self) -> P47WP_W<'_>

Bit 15 - P47WP

pub fn p46wp(&mut self) -> P46WP_W<'_>

Bit 14 - P46WP

pub fn p45wp(&mut self) -> P45WP_W<'_>

Bit 13 - P45WP

pub fn p44wp(&mut self) -> P44WP_W<'_>

Bit 12 - P44WP

pub fn p43wp(&mut self) -> P43WP_W<'_>

Bit 11 - P43WP

pub fn p42wp(&mut self) -> P42WP_W<'_>

Bit 10 - P42WP

pub fn p41wp(&mut self) -> P41WP_W<'_>

Bit 9 - P41WP

pub fn p40wp(&mut self) -> P40WP_W<'_>

Bit 8 - P40WP

pub fn p39wp(&mut self) -> P39WP_W<'_>

Bit 7 - P39WP

pub fn p38wp(&mut self) -> P38WP_W<'_>

Bit 6 - P38WP

pub fn p37wp(&mut self) -> P37WP_W<'_>

Bit 5 - P37WP

pub fn p36wp(&mut self) -> P36WP_W<'_>

Bit 4 - P36WP

pub fn p35wp(&mut self) -> P35WP_W<'_>

Bit 3 - P35WP

pub fn p34wp(&mut self) -> P34WP_W<'_>

Bit 2 - P34WP

pub fn p33wp(&mut self) -> P33WP_W<'_>

Bit 1 - P33WP

pub fn p32wp(&mut self) -> P32WP_W<'_>

Bit 0 - P32WP

impl W<u32, Reg<u32, _IMR1>>

pub fn tim1im(&mut self) -> TIM1IM_W<'_>

Bit 13 - Peripheral TIM1 interrupt mask to CPU1

pub fn tim16im(&mut self) -> TIM16IM_W<'_>

Bit 14 - Peripheral TIM16 interrupt mask to CPU1

pub fn tim17im(&mut self) -> TIM17IM_W<'_>

Bit 15 - Peripheral TIM17 interrupt mask to CPU1

pub fn exit5im(&mut self) -> EXIT5IM_W<'_>

Bit 21 - Peripheral EXIT5 interrupt mask to CPU1

pub fn exit6im(&mut self) -> EXIT6IM_W<'_>

Bit 22 - Peripheral EXIT6 interrupt mask to CPU1

pub fn exit7im(&mut self) -> EXIT7IM_W<'_>

Bit 23 - Peripheral EXIT7 interrupt mask to CPU1

pub fn exit8im(&mut self) -> EXIT8IM_W<'_>

Bit 24 - Peripheral EXIT8 interrupt mask to CPU1

pub fn exit9im(&mut self) -> EXIT9IM_W<'_>

Bit 25 - Peripheral EXIT9 interrupt mask to CPU1

pub fn exit10im(&mut self) -> EXIT10IM_W<'_>

Bit 26 - Peripheral EXIT10 interrupt mask to CPU1

pub fn exit11im(&mut self) -> EXIT11IM_W<'_>

Bit 27 - Peripheral EXIT11 interrupt mask to CPU1

pub fn exit12im(&mut self) -> EXIT12IM_W<'_>

Bit 28 - Peripheral EXIT12 interrupt mask to CPU1

pub fn exit13im(&mut self) -> EXIT13IM_W<'_>

Bit 29 - Peripheral EXIT13 interrupt mask to CPU1

pub fn exit14im(&mut self) -> EXIT14IM_W<'_>

Bit 30 - Peripheral EXIT14 interrupt mask to CPU1

pub fn exit15im(&mut self) -> EXIT15IM_W<'_>

Bit 31 - Peripheral EXIT15 interrupt mask to CPU1

impl W<u32, Reg<u32, _IMR2>>

pub fn pvm3im(&mut self) -> PVM3IM_W<'_>

Bit 18 - Peripheral PVM3 interrupt mask to CPU1

pub fn pvm1im(&mut self) -> PVM1IM_W<'_>

Bit 16 - Peripheral PVM1 interrupt mask to CPU1

pub fn pvdim(&mut self) -> PVDIM_W<'_>

Bit 20 - Peripheral PVD interrupt mask to CPU1

impl W<u32, Reg<u32, _C2IMR1>>

pub fn rtcstamp(&mut self) -> RTCSTAMP_W<'_>

Bit 0 - Peripheral RTCSTAMP interrupt mask to CPU2

pub fn rtcwkup(&mut self) -> RTCWKUP_W<'_>

Bit 3 - Peripheral RTCWKUP interrupt mask to CPU2

pub fn rtcalarm(&mut self) -> RTCALARM_W<'_>

Bit 4 - Peripheral RTCALARM interrupt mask to CPU2

pub fn rcc(&mut self) -> RCC_W<'_>

Bit 5 - Peripheral RCC interrupt mask to CPU2

pub fn flash(&mut self) -> FLASH_W<'_>

Bit 6 - Peripheral FLASH interrupt mask to CPU2

pub fn pka(&mut self) -> PKA_W<'_>

Bit 8 - Peripheral PKA interrupt mask to CPU2

pub fn rng(&mut self) -> RNG_W<'_>

Bit 9 - Peripheral RNG interrupt mask to CPU2

pub fn aes1(&mut self) -> AES1_W<'_>

Bit 10 - Peripheral AES1 interrupt mask to CPU2

pub fn comp(&mut self) -> COMP_W<'_>

Bit 11 - Peripheral COMP interrupt mask to CPU2

pub fn adc(&mut self) -> ADC_W<'_>

Bit 12 - Peripheral ADC interrupt mask to CPU2

impl W<u32, Reg<u32, _C2IMR2>>

pub fn dma1_ch1_im(&mut self) -> DMA1_CH1_IM_W<'_>

Bit 0 - Peripheral DMA1 CH1 interrupt mask to CPU2

pub fn dma1_ch2_im(&mut self) -> DMA1_CH2_IM_W<'_>

Bit 1 - Peripheral DMA1 CH2 interrupt mask to CPU2

pub fn dma1_ch3_im(&mut self) -> DMA1_CH3_IM_W<'_>

Bit 2 - Peripheral DMA1 CH3 interrupt mask to CPU2

pub fn dma1_ch4_im(&mut self) -> DMA1_CH4_IM_W<'_>

Bit 3 - Peripheral DMA1 CH4 interrupt mask to CPU2

pub fn dma1_ch5_im(&mut self) -> DMA1_CH5_IM_W<'_>

Bit 4 - Peripheral DMA1 CH5 interrupt mask to CPU2

pub fn dma1_ch6_im(&mut self) -> DMA1_CH6_IM_W<'_>

Bit 5 - Peripheral DMA1 CH6 interrupt mask to CPU2

pub fn dma1_ch7_im(&mut self) -> DMA1_CH7_IM_W<'_>

Bit 6 - Peripheral DMA1 CH7 interrupt mask to CPU2

pub fn dma2_ch1_im(&mut self) -> DMA2_CH1_IM_W<'_>

Bit 8 - Peripheral DMA2 CH1 interrupt mask to CPU1

pub fn dma2_ch2_im(&mut self) -> DMA2_CH2_IM_W<'_>

Bit 9 - Peripheral DMA2 CH2 interrupt mask to CPU1

pub fn dma2_ch3_im(&mut self) -> DMA2_CH3_IM_W<'_>

Bit 10 - Peripheral DMA2 CH3 interrupt mask to CPU1

pub fn dma2_ch4_im(&mut self) -> DMA2_CH4_IM_W<'_>

Bit 11 - Peripheral DMA2 CH4 interrupt mask to CPU1

pub fn dma2_ch5_im(&mut self) -> DMA2_CH5_IM_W<'_>

Bit 12 - Peripheral DMA2 CH5 interrupt mask to CPU1

pub fn dma2_ch6_im(&mut self) -> DMA2_CH6_IM_W<'_>

Bit 13 - Peripheral DMA2 CH6 interrupt mask to CPU1

pub fn dma2_ch7_im(&mut self) -> DMA2_CH7_IM_W<'_>

Bit 14 - Peripheral DMA2 CH7 interrupt mask to CPU1

pub fn dmam_ux1_im(&mut self) -> DMAM_UX1_IM_W<'_>

Bit 15 - Peripheral DMAM UX1 interrupt mask to CPU1

pub fn pvm1im(&mut self) -> PVM1IM_W<'_>

Bit 16 - Peripheral PVM1IM interrupt mask to CPU1

pub fn pvm3im(&mut self) -> PVM3IM_W<'_>

Bit 18 - Peripheral PVM3IM interrupt mask to CPU1

pub fn pvdim(&mut self) -> PVDIM_W<'_>

Bit 20 - Peripheral PVDIM interrupt mask to CPU1

pub fn tscim(&mut self) -> TSCIM_W<'_>

Bit 21 - Peripheral TSCIM interrupt mask to CPU1

pub fn lcdim(&mut self) -> LCDIM_W<'_>

Bit 22 - Peripheral LCDIM interrupt mask to CPU1

impl W<u32, Reg<u32, _SIPCR>>

pub fn saes1(&mut self) -> SAES1_W<'_>

Bit 0 - Enable AES1 KEY[7:0] security.

pub fn saes2(&mut self) -> SAES2_W<'_>

Bit 1 - Enable AES2 security.

pub fn spka(&mut self) -> SPKA_W<'_>

Bit 2 - Enable PKA security

pub fn srng(&mut self) -> SRNG_W<'_>

Bit 3 - Enable True RNG security

impl W<u32, Reg<u32, _CR>>

pub fn rngen(&mut self) -> RNGEN_W<'_>

Bit 2 - Random number generator enable

pub fn ie(&mut self) -> IE_W<'_>

Bit 3 - Interrupt enable

pub fn byp(&mut self) -> BYP_W<'_>

Bit 6 - Bypass mode enable

impl W<u32, Reg<u32, _SR>>

pub fn seis(&mut self) -> SEIS_W<'_>

Bit 6 - Seed error interrupt status

pub fn ceis(&mut self) -> CEIS_W<'_>

Bit 5 - Clock error interrupt status

impl W<u32, Reg<u32, _CR>>

pub fn npblb(&mut self) -> NPBLB_W<'_>

Bits 20:23 - Number of padding bytes in last block of payload

pub fn keysize(&mut self) -> KEYSIZE_W<'_>

Bit 18 - Key size selection

pub fn chmod2(&mut self) -> CHMOD2_W<'_>

Bit 16 - AES chaining mode Bit2

pub fn gcmph(&mut self) -> GCMPH_W<'_>

Bits 13:14 - Used only for GCM, CCM and GMAC algorithms and has no effect when other algorithms are selected

pub fn dmaouten(&mut self) -> DMAOUTEN_W<'_>

Bit 12 - Enable DMA management of data output phase

pub fn dmainen(&mut self) -> DMAINEN_W<'_>

Bit 11 - Enable DMA management of data input phase

pub fn errie(&mut self) -> ERRIE_W<'_>

Bit 10 - Error interrupt enable

pub fn ccfie(&mut self) -> CCFIE_W<'_>

Bit 9 - CCF flag interrupt enable

pub fn errc(&mut self) -> ERRC_W<'_>

Bit 8 - Error clear

pub fn ccfc(&mut self) -> CCFC_W<'_>

Bit 7 - Computation Complete Flag Clear

pub fn chmod10(&mut self) -> CHMOD10_W<'_>

Bits 5:6 - AES chaining mode Bit1 Bit0

pub fn mode(&mut self) -> MODE_W<'_>

Bits 3:4 - AES operating mode

pub fn datatype(&mut self) -> DATATYPE_W<'_>

Bits 1:2 - Data type selection (for data in and data out to/from the cryptographic block)

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - AES enable

impl W<u32, Reg<u32, _DINR>>

pub fn aes_dinr(&mut self) -> AES_DINR_W<'_>

Bits 0:31 - Data Input Register

impl W<u32, Reg<u32, _KEYR0>>

pub fn aes_keyr0(&mut self) -> AES_KEYR0_W<'_>

Bits 0:31 - Data Output Register (LSB key [31:0])

impl W<u32, Reg<u32, _KEYR1>>

pub fn aes_keyr1(&mut self) -> AES_KEYR1_W<'_>

Bits 0:31 - AES key register (key [63:32])

impl W<u32, Reg<u32, _KEYR2>>

pub fn aes_keyr2(&mut self) -> AES_KEYR2_W<'_>

Bits 0:31 - AES key register (key [95:64])

impl W<u32, Reg<u32, _KEYR3>>

pub fn aes_keyr3(&mut self) -> AES_KEYR3_W<'_>

Bits 0:31 - AES key register (MSB key [127:96])

impl W<u32, Reg<u32, _IVR0>>

pub fn aes_ivr0(&mut self) -> AES_IVR0_W<'_>

Bits 0:31 - initialization vector register (LSB IVR [31:0])

impl W<u32, Reg<u32, _IVR1>>

pub fn aes_ivr1(&mut self) -> AES_IVR1_W<'_>

Bits 0:31 - Initialization Vector Register (IVR [63:32])

impl W<u32, Reg<u32, _IVR2>>

pub fn aes_ivr2(&mut self) -> AES_IVR2_W<'_>

Bits 0:31 - Initialization Vector Register (IVR [95:64])

impl W<u32, Reg<u32, _IVR3>>

pub fn aes_ivr3(&mut self) -> AES_IVR3_W<'_>

Bits 0:31 - Initialization Vector Register (MSB IVR [127:96])

impl W<u32, Reg<u32, _KEYR4>>

pub fn aes_keyr4(&mut self) -> AES_KEYR4_W<'_>

Bits 0:31 - AES key register (MSB key [159:128])

impl W<u32, Reg<u32, _KEYR5>>

pub fn aes_keyr5(&mut self) -> AES_KEYR5_W<'_>

Bits 0:31 - AES key register (MSB key [191:160])

impl W<u32, Reg<u32, _KEYR6>>

pub fn aes_keyr6(&mut self) -> AES_KEYR6_W<'_>

Bits 0:31 - AES key register (MSB key [223:192])

impl W<u32, Reg<u32, _KEYR7>>

pub fn aes_keyr7(&mut self) -> AES_KEYR7_W<'_>

Bits 0:31 - AES key register (MSB key [255:224])

impl W<u32, Reg<u32, _SUSP0R>>

pub fn aes_susp0r(&mut self) -> AES_SUSP0R_W<'_>

Bits 0:31 - AES suspend register 0

impl W<u32, Reg<u32, _SUSP1R>>

pub fn aes_susp1r(&mut self) -> AES_SUSP1R_W<'_>

Bits 0:31 - AES suspend register 1

impl W<u32, Reg<u32, _SUSP2R>>

pub fn aes_susp2r(&mut self) -> AES_SUSP2R_W<'_>

Bits 0:31 - AES suspend register 2

impl W<u32, Reg<u32, _SUSP3R>>

pub fn aes_susp3r(&mut self) -> AES_SUSP3R_W<'_>

Bits 0:31 - AES suspend register 3

impl W<u32, Reg<u32, _SUSP4R>>

pub fn aes_susp4r(&mut self) -> AES_SUSP4R_W<'_>

Bits 0:31 - AES suspend register 4

impl W<u32, Reg<u32, _SUSP5R>>

pub fn aes_susp5r(&mut self) -> AES_SUSP5R_W<'_>

Bits 0:31 - AES suspend register 5

impl W<u32, Reg<u32, _SUSP6R>>

pub fn aes_susp6r(&mut self) -> AES_SUSP6R_W<'_>

Bits 0:31 - AES suspend register 6

impl W<u32, Reg<u32, _SUSP7R>>

pub fn aes_susp7r(&mut self) -> AES_SUSP7R_W<'_>

Bits 0:31 - AES suspend register 7

impl W<u32, Reg<u32, _CR>>

pub fn npblb(&mut self) -> NPBLB_W<'_>

Bits 20:23 - Number of padding bytes in last block of payload

pub fn keysize(&mut self) -> KEYSIZE_W<'_>

Bit 18 - Key size selection

pub fn chmod2(&mut self) -> CHMOD2_W<'_>

Bit 16 - AES chaining mode Bit2

pub fn gcmph(&mut self) -> GCMPH_W<'_>

Bits 13:14 - Used only for GCM, CCM and GMAC algorithms and has no effect when other algorithms are selected

pub fn dmaouten(&mut self) -> DMAOUTEN_W<'_>

Bit 12 - Enable DMA management of data output phase

pub fn dmainen(&mut self) -> DMAINEN_W<'_>

Bit 11 - Enable DMA management of data input phase

pub fn errie(&mut self) -> ERRIE_W<'_>

Bit 10 - Error interrupt enable

pub fn ccfie(&mut self) -> CCFIE_W<'_>

Bit 9 - CCF flag interrupt enable

pub fn errc(&mut self) -> ERRC_W<'_>

Bit 8 - Error clear

pub fn ccfc(&mut self) -> CCFC_W<'_>

Bit 7 - Computation Complete Flag Clear

pub fn chmod10(&mut self) -> CHMOD10_W<'_>

Bits 5:6 - AES chaining mode Bit1 Bit0

pub fn mode(&mut self) -> MODE_W<'_>

Bits 3:4 - AES operating mode

pub fn datatype(&mut self) -> DATATYPE_W<'_>

Bits 1:2 - Data type selection (for data in and data out to/from the cryptographic block)

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - AES enable

impl W<u32, Reg<u32, _DINR>>

pub fn aes_dinr(&mut self) -> AES_DINR_W<'_>

Bits 0:31 - Data Input Register

impl W<u32, Reg<u32, _KEYR0>>

pub fn aes_keyr0(&mut self) -> AES_KEYR0_W<'_>

Bits 0:31 - Data Output Register (LSB key [31:0])

impl W<u32, Reg<u32, _KEYR1>>

pub fn aes_keyr1(&mut self) -> AES_KEYR1_W<'_>

Bits 0:31 - AES key register (key [63:32])

impl W<u32, Reg<u32, _KEYR2>>

pub fn aes_keyr2(&mut self) -> AES_KEYR2_W<'_>

Bits 0:31 - AES key register (key [95:64])

impl W<u32, Reg<u32, _KEYR3>>

pub fn aes_keyr3(&mut self) -> AES_KEYR3_W<'_>

Bits 0:31 - AES key register (MSB key [127:96])

impl W<u32, Reg<u32, _IVR0>>

pub fn aes_ivr0(&mut self) -> AES_IVR0_W<'_>

Bits 0:31 - initialization vector register (LSB IVR [31:0])

impl W<u32, Reg<u32, _IVR1>>

pub fn aes_ivr1(&mut self) -> AES_IVR1_W<'_>

Bits 0:31 - Initialization Vector Register (IVR [63:32])

impl W<u32, Reg<u32, _IVR2>>

pub fn aes_ivr2(&mut self) -> AES_IVR2_W<'_>

Bits 0:31 - Initialization Vector Register (IVR [95:64])

impl W<u32, Reg<u32, _IVR3>>

pub fn aes_ivr3(&mut self) -> AES_IVR3_W<'_>

Bits 0:31 - Initialization Vector Register (MSB IVR [127:96])

impl W<u32, Reg<u32, _KEYR4>>

pub fn aes_keyr4(&mut self) -> AES_KEYR4_W<'_>

Bits 0:31 - AES key register (MSB key [159:128])

impl W<u32, Reg<u32, _KEYR5>>

pub fn aes_keyr5(&mut self) -> AES_KEYR5_W<'_>

Bits 0:31 - AES key register (MSB key [191:160])

impl W<u32, Reg<u32, _KEYR6>>

pub fn aes_keyr6(&mut self) -> AES_KEYR6_W<'_>

Bits 0:31 - AES key register (MSB key [223:192])

impl W<u32, Reg<u32, _KEYR7>>

pub fn aes_keyr7(&mut self) -> AES_KEYR7_W<'_>

Bits 0:31 - AES key register (MSB key [255:224])

impl W<u32, Reg<u32, _SUSP0R>>

pub fn aes_susp0r(&mut self) -> AES_SUSP0R_W<'_>

Bits 0:31 - AES suspend register 0

impl W<u32, Reg<u32, _SUSP1R>>

pub fn aes_susp1r(&mut self) -> AES_SUSP1R_W<'_>

Bits 0:31 - AES suspend register 1

impl W<u32, Reg<u32, _SUSP2R>>

pub fn aes_susp2r(&mut self) -> AES_SUSP2R_W<'_>

Bits 0:31 - AES suspend register 2

impl W<u32, Reg<u32, _SUSP3R>>

pub fn aes_susp3r(&mut self) -> AES_SUSP3R_W<'_>

Bits 0:31 - AES suspend register 3

impl W<u32, Reg<u32, _SUSP4R>>

pub fn aes_susp4r(&mut self) -> AES_SUSP4R_W<'_>

Bits 0:31 - AES suspend register 4

impl W<u32, Reg<u32, _SUSP5R>>

pub fn aes_susp5r(&mut self) -> AES_SUSP5R_W<'_>

Bits 0:31 - AES suspend register 5

impl W<u32, Reg<u32, _SUSP6R>>

pub fn aes_susp6r(&mut self) -> AES_SUSP6R_W<'_>

Bits 0:31 - AES suspend register 6

impl W<u32, Reg<u32, _SUSP7R>>

pub fn aes_susp7r(&mut self) -> AES_SUSP7R_W<'_>

Bits 0:31 - AES suspend register 7

impl W<u32, Reg<u32, _R0>>

pub fn lock(&mut self) -> LOCK_W<'_>

Bit 31 - lock indication

pub fn coreid(&mut self) -> COREID_W<'_>

Bits 8:11 - Semaphore CoreID

pub fn procid(&mut self) -> PROCID_W<'_>

Bits 0:7 - Semaphore ProcessID

impl W<u32, Reg<u32, _R1>>

pub fn lock(&mut self) -> LOCK_W<'_>

Bit 31 - lock indication

pub fn coreid(&mut self) -> COREID_W<'_>

Bits 8:11 - Semaphore CoreID

pub fn procid(&mut self) -> PROCID_W<'_>

Bits 0:7 - Semaphore ProcessID

impl W<u32, Reg<u32, _R2>>

pub fn lock(&mut self) -> LOCK_W<'_>

Bit 31 - lock indication

pub fn coreid(&mut self) -> COREID_W<'_>

Bits 8:11 - Semaphore CoreID

pub fn procid(&mut self) -> PROCID_W<'_>

Bits 0:7 - Semaphore ProcessID

impl W<u32, Reg<u32, _R3>>

pub fn lock(&mut self) -> LOCK_W<'_>

Bit 31 - lock indication

pub fn coreid(&mut self) -> COREID_W<'_>

Bits 8:11 - Semaphore CoreID

pub fn procid(&mut self) -> PROCID_W<'_>

Bits 0:7 - Semaphore ProcessID

impl W<u32, Reg<u32, _R4>>

pub fn lock(&mut self) -> LOCK_W<'_>

Bit 31 - lock indication

pub fn coreid(&mut self) -> COREID_W<'_>

Bits 8:11 - Semaphore CoreID

pub fn procid(&mut self) -> PROCID_W<'_>

Bits 0:7 - Semaphore ProcessID

impl W<u32, Reg<u32, _R5>>

pub fn lock(&mut self) -> LOCK_W<'_>

Bit 31 - lock indication

pub fn coreid(&mut self) -> COREID_W<'_>

Bits 8:11 - Semaphore CoreID

pub fn procid(&mut self) -> PROCID_W<'_>

Bits 0:7 - Semaphore ProcessID

impl W<u32, Reg<u32, _R6>>

pub fn lock(&mut self) -> LOCK_W<'_>

Bit 31 - lock indication

pub fn coreid(&mut self) -> COREID_W<'_>

Bits 8:11 - Semaphore CoreID

pub fn procid(&mut self) -> PROCID_W<'_>

Bits 0:7 - Semaphore ProcessID

impl W<u32, Reg<u32, _R7>>

pub fn lock(&mut self) -> LOCK_W<'_>

Bit 31 - lock indication

pub fn coreid(&mut self) -> COREID_W<'_>

Bits 8:11 - Semaphore CoreID

pub fn procid(&mut self) -> PROCID_W<'_>

Bits 0:7 - Semaphore ProcessID

impl W<u32, Reg<u32, _R8>>

pub fn lock(&mut self) -> LOCK_W<'_>

Bit 31 - lock indication

pub fn coreid(&mut self) -> COREID_W<'_>

Bits 8:11 - Semaphore CoreID

pub fn procid(&mut self) -> PROCID_W<'_>

Bits 0:7 - Semaphore ProcessID

impl W<u32, Reg<u32, _R9>>

pub fn lock(&mut self) -> LOCK_W<'_>

Bit 31 - lock indication

pub fn coreid(&mut self) -> COREID_W<'_>

Bits 8:11 - Semaphore CoreID

pub fn procid(&mut self) -> PROCID_W<'_>

Bits 0:7 - Semaphore ProcessID

impl W<u32, Reg<u32, _R10>>

pub fn lock(&mut self) -> LOCK_W<'_>

Bit 31 - lock indication

pub fn coreid(&mut self) -> COREID_W<'_>

Bits 8:11 - Semaphore CoreID

pub fn procid(&mut self) -> PROCID_W<'_>

Bits 0:7 - Semaphore ProcessID

impl W<u32, Reg<u32, _R11>>

pub fn lock(&mut self) -> LOCK_W<'_>

Bit 31 - lock indication

pub fn coreid(&mut self) -> COREID_W<'_>

Bits 8:11 - Semaphore CoreID

pub fn procid(&mut self) -> PROCID_W<'_>

Bits 0:7 - Semaphore ProcessID

impl W<u32, Reg<u32, _R12>>

pub fn lock(&mut self) -> LOCK_W<'_>

Bit 31 - lock indication

pub fn coreid(&mut self) -> COREID_W<'_>

Bits 8:11 - Semaphore CoreID

pub fn procid(&mut self) -> PROCID_W<'_>

Bits 0:7 - Semaphore ProcessID

impl W<u32, Reg<u32, _R13>>

pub fn lock(&mut self) -> LOCK_W<'_>

Bit 31 - lock indication

pub fn coreid(&mut self) -> COREID_W<'_>

Bits 8:11 - Semaphore CoreID

pub fn procid(&mut self) -> PROCID_W<'_>

Bits 0:7 - Semaphore ProcessID

impl W<u32, Reg<u32, _R14>>

pub fn lock(&mut self) -> LOCK_W<'_>

Bit 31 - lock indication

pub fn coreid(&mut self) -> COREID_W<'_>

Bits 8:11 - Semaphore CoreID

pub fn procid(&mut self) -> PROCID_W<'_>

Bits 0:7 - Semaphore ProcessID

impl W<u32, Reg<u32, _R15>>

pub fn lock(&mut self) -> LOCK_W<'_>

Bit 31 - lock indication

pub fn coreid(&mut self) -> COREID_W<'_>

Bits 8:11 - Semaphore CoreID

pub fn procid(&mut self) -> PROCID_W<'_>

Bits 0:7 - Semaphore ProcessID

impl W<u32, Reg<u32, _R16>>

pub fn lock(&mut self) -> LOCK_W<'_>

Bit 31 - lock indication

pub fn coreid(&mut self) -> COREID_W<'_>

Bits 8:11 - Semaphore CoreID

pub fn procid(&mut self) -> PROCID_W<'_>

Bits 0:7 - Semaphore ProcessID

impl W<u32, Reg<u32, _R17>>

pub fn lock(&mut self) -> LOCK_W<'_>

Bit 31 - lock indication

pub fn coreid(&mut self) -> COREID_W<'_>

Bits 8:11 - Semaphore CoreID

pub fn procid(&mut self) -> PROCID_W<'_>

Bits 0:7 - Semaphore ProcessID

impl W<u32, Reg<u32, _R18>>

pub fn lock(&mut self) -> LOCK_W<'_>

Bit 31 - lock indication

pub fn coreid(&mut self) -> COREID_W<'_>

Bits 8:11 - Semaphore CoreID

pub fn procid(&mut self) -> PROCID_W<'_>

Bits 0:7 - Semaphore ProcessID

impl W<u32, Reg<u32, _R19>>

pub fn lock(&mut self) -> LOCK_W<'_>

Bit 31 - lock indication

pub fn coreid(&mut self) -> COREID_W<'_>

Bits 8:11 - Semaphore CoreID

pub fn procid(&mut self) -> PROCID_W<'_>

Bits 0:7 - Semaphore ProcessID

impl W<u32, Reg<u32, _R20>>

pub fn lock(&mut self) -> LOCK_W<'_>

Bit 31 - lock indication

pub fn coreid(&mut self) -> COREID_W<'_>

Bits 8:11 - Semaphore CoreID

pub fn procid(&mut self) -> PROCID_W<'_>

Bits 0:7 - Semaphore ProcessID

impl W<u32, Reg<u32, _R21>>

pub fn lock(&mut self) -> LOCK_W<'_>

Bit 31 - lock indication

pub fn coreid(&mut self) -> COREID_W<'_>

Bits 8:11 - Semaphore CoreID

pub fn procid(&mut self) -> PROCID_W<'_>

Bits 0:7 - Semaphore ProcessID

impl W<u32, Reg<u32, _R22>>

pub fn lock(&mut self) -> LOCK_W<'_>

Bit 31 - lock indication

pub fn coreid(&mut self) -> COREID_W<'_>

Bits 8:11 - Semaphore CoreID

pub fn procid(&mut self) -> PROCID_W<'_>

Bits 0:7 - Semaphore ProcessID

impl W<u32, Reg<u32, _R23>>

pub fn lock(&mut self) -> LOCK_W<'_>

Bit 31 - lock indication

pub fn coreid(&mut self) -> COREID_W<'_>

Bits 8:11 - Semaphore CoreID

pub fn procid(&mut self) -> PROCID_W<'_>

Bits 0:7 - Semaphore ProcessID

impl W<u32, Reg<u32, _R24>>

pub fn lock(&mut self) -> LOCK_W<'_>

Bit 31 - lock indication

pub fn coreid(&mut self) -> COREID_W<'_>

Bits 8:11 - Semaphore CoreID

pub fn procid(&mut self) -> PROCID_W<'_>

Bits 0:7 - Semaphore ProcessID

impl W<u32, Reg<u32, _R25>>

pub fn lock(&mut self) -> LOCK_W<'_>

Bit 31 - lock indication

pub fn coreid(&mut self) -> COREID_W<'_>

Bits 8:11 - Semaphore CoreID

pub fn procid(&mut self) -> PROCID_W<'_>

Bits 0:7 - Semaphore ProcessID

impl W<u32, Reg<u32, _R26>>

pub fn lock(&mut self) -> LOCK_W<'_>

Bit 31 - lock indication

pub fn coreid(&mut self) -> COREID_W<'_>

Bits 8:11 - Semaphore CoreID

pub fn procid(&mut self) -> PROCID_W<'_>

Bits 0:7 - Semaphore ProcessID

impl W<u32, Reg<u32, _R27>>

pub fn lock(&mut self) -> LOCK_W<'_>

Bit 31 - lock indication

pub fn coreid(&mut self) -> COREID_W<'_>

Bits 8:11 - Semaphore CoreID

pub fn procid(&mut self) -> PROCID_W<'_>

Bits 0:7 - Semaphore ProcessID

impl W<u32, Reg<u32, _R28>>

pub fn lock(&mut self) -> LOCK_W<'_>

Bit 31 - lock indication

pub fn coreid(&mut self) -> COREID_W<'_>

Bits 8:11 - Semaphore CoreID

pub fn procid(&mut self) -> PROCID_W<'_>

Bits 0:7 - Semaphore ProcessID

impl W<u32, Reg<u32, _R29>>

pub fn lock(&mut self) -> LOCK_W<'_>

Bit 31 - lock indication

pub fn coreid(&mut self) -> COREID_W<'_>

Bits 8:11 - Semaphore CoreID

pub fn procid(&mut self) -> PROCID_W<'_>

Bits 0:7 - Semaphore ProcessID

impl W<u32, Reg<u32, _R30>>

pub fn lock(&mut self) -> LOCK_W<'_>

Bit 31 - lock indication

pub fn coreid(&mut self) -> COREID_W<'_>

Bits 8:11 - Semaphore CoreID

pub fn procid(&mut self) -> PROCID_W<'_>

Bits 0:7 - Semaphore ProcessID

impl W<u32, Reg<u32, _R31>>

pub fn lock(&mut self) -> LOCK_W<'_>

Bit 31 - lock indication

pub fn coreid(&mut self) -> COREID_W<'_>

Bits 8:11 - Semaphore CoreID

pub fn procid(&mut self) -> PROCID_W<'_>

Bits 0:7 - Semaphore ProcessID

impl W<u32, Reg<u32, _CR>>

pub fn key(&mut self) -> KEY_W<'_>

Bits 16:31 - Semaphore clear Key

pub fn coreid(&mut self) -> COREID_W<'_>

Bits 8:11 - CoreID of semaphore to be cleared

impl W<u32, Reg<u32, _KEYR>>

pub fn key(&mut self) -> KEY_W<'_>

Bits 16:31 - Semaphore Clear Key

impl W<u32, Reg<u32, _C1IER0>>

pub fn isem(&mut self) -> ISEM_W<'_>

Bits 0:31 - CPU(n) semaphore m enable bit

impl W<u32, Reg<u32, _C1ICR>>

pub fn iscm(&mut self) -> ISCM_W<'_>

Bits 0:31 - CPU(n) semaphore m clear bit

impl W<u32, Reg<u32, _C2IER0>>

pub fn isem(&mut self) -> ISEM_W<'_>

Bits 0:31 - CPU(2) semaphore m enable bit.

impl W<u32, Reg<u32, _C2ICR>>

pub fn iscm(&mut self) -> ISCM_W<'_>

Bits 0:31 - CPU(2) semaphore m clear bit

impl W<u32, Reg<u32, _ISR>>

pub fn jqovf(&mut self) -> JQOVF_W<'_>

Bit 10 - ADC group injected contexts queue overflow flag

pub fn awd3(&mut self) -> AWD3_W<'_>

Bit 9 - ADC analog watchdog 3 flag

pub fn awd2(&mut self) -> AWD2_W<'_>

Bit 8 - ADC analog watchdog 2 flag

pub fn awd1(&mut self) -> AWD1_W<'_>

Bit 7 - ADC analog watchdog 1 flag

pub fn jeos(&mut self) -> JEOS_W<'_>

Bit 6 - ADC group injected end of sequence conversions flag

pub fn jeoc(&mut self) -> JEOC_W<'_>

Bit 5 - ADC group injected end of unitary conversion flag

pub fn ovr(&mut self) -> OVR_W<'_>

Bit 4 - ADC group regular overrun flag

pub fn eos(&mut self) -> EOS_W<'_>

Bit 3 - ADC group regular end of sequence conversions flag

pub fn eoc(&mut self) -> EOC_W<'_>

Bit 2 - ADC group regular end of unitary conversion flag

pub fn eosmp(&mut self) -> EOSMP_W<'_>

Bit 1 - ADC group regular end of sampling flag

pub fn adrdy(&mut self) -> ADRDY_W<'_>

Bit 0 - ADC ready flag

impl W<u32, Reg<u32, _IER>>

pub fn jqovfie(&mut self) -> JQOVFIE_W<'_>

Bit 10 - ADC group injected contexts queue overflow interrupt

pub fn awd3ie(&mut self) -> AWD3IE_W<'_>

Bit 9 - ADC analog watchdog 3 interrupt

pub fn awd2ie(&mut self) -> AWD2IE_W<'_>

Bit 8 - ADC analog watchdog 2 interrupt

pub fn awd1ie(&mut self) -> AWD1IE_W<'_>

Bit 7 - ADC analog watchdog 1 interrupt

pub fn jeosie(&mut self) -> JEOSIE_W<'_>

Bit 6 - ADC group injected end of sequence conversions interrupt

pub fn jeocie(&mut self) -> JEOCIE_W<'_>

Bit 5 - ADC group injected end of unitary conversion interrupt

pub fn ovrie(&mut self) -> OVRIE_W<'_>

Bit 4 - ADC group regular overrun interrupt

pub fn eosie(&mut self) -> EOSIE_W<'_>

Bit 3 - ADC group regular end of sequence conversions interrupt

pub fn eocie(&mut self) -> EOCIE_W<'_>

Bit 2 - ADC group regular end of unitary conversion interrupt

pub fn eosmpie(&mut self) -> EOSMPIE_W<'_>

Bit 1 - ADC group regular end of sampling interrupt

pub fn adrdyie(&mut self) -> ADRDYIE_W<'_>

Bit 0 - ADC ready interrupt

impl W<u32, Reg<u32, _CR>>

pub fn adcal(&mut self) -> ADCAL_W<'_>

Bit 31 - ADC calibration

pub fn adcaldif(&mut self) -> ADCALDIF_W<'_>

Bit 30 - ADC differential mode for calibration

pub fn deeppwd(&mut self) -> DEEPPWD_W<'_>

Bit 29 - ADC deep power down enable

pub fn advregen(&mut self) -> ADVREGEN_W<'_>

Bit 28 - ADC voltage regulator enable

pub fn jadstp(&mut self) -> JADSTP_W<'_>

Bit 5 - ADC group injected conversion stop

pub fn adstp(&mut self) -> ADSTP_W<'_>

Bit 4 - ADC group regular conversion stop

pub fn jadstart(&mut self) -> JADSTART_W<'_>

Bit 3 - ADC group injected conversion start

pub fn adstart(&mut self) -> ADSTART_W<'_>

Bit 2 - ADC group regular conversion start

pub fn addis(&mut self) -> ADDIS_W<'_>

Bit 1 - ADC disable

pub fn aden(&mut self) -> ADEN_W<'_>

Bit 0 - ADC enable

impl W<u32, Reg<u32, _CFGR>>

pub fn jqdis(&mut self) -> JQDIS_W<'_>

Bit 31 - ADC group injected contexts queue disable

pub fn awdch1ch(&mut self) -> AWDCH1CH_W<'_>

Bits 26:30 - ADC analog watchdog 1 monitored channel selection

pub fn jauto(&mut self) -> JAUTO_W<'_>

Bit 25 - ADC group injected automatic trigger mode

pub fn jawd1en(&mut self) -> JAWD1EN_W<'_>

Bit 24 - ADC analog watchdog 1 enable on scope ADC group injected

pub fn awd1en(&mut self) -> AWD1EN_W<'_>

Bit 23 - ADC analog watchdog 1 enable on scope ADC group regular

pub fn awd1sgl(&mut self) -> AWD1SGL_W<'_>

Bit 22 - ADC analog watchdog 1 monitoring a single channel or all channels

pub fn jqm(&mut self) -> JQM_W<'_>

Bit 21 - ADC group injected contexts queue mode

pub fn jdiscen(&mut self) -> JDISCEN_W<'_>

Bit 20 - ADC group injected sequencer discontinuous mode

pub fn discnum(&mut self) -> DISCNUM_W<'_>

Bits 17:19 - ADC group regular sequencer discontinuous number of ranks

pub fn discen(&mut self) -> DISCEN_W<'_>

Bit 16 - ADC group regular sequencer discontinuous mode

pub fn autdly(&mut self) -> AUTDLY_W<'_>

Bit 14 - ADC low power auto wait

pub fn cont(&mut self) -> CONT_W<'_>

Bit 13 - ADC group regular continuous conversion mode

pub fn ovrmod(&mut self) -> OVRMOD_W<'_>

Bit 12 - ADC group regular overrun configuration

pub fn exten(&mut self) -> EXTEN_W<'_>

Bits 10:11 - ADC group regular external trigger polarity

pub fn extsel(&mut self) -> EXTSEL_W<'_>

Bits 6:9 - ADC group regular external trigger source

pub fn align(&mut self) -> ALIGN_W<'_>

Bit 5 - ADC data alignement

pub fn res(&mut self) -> RES_W<'_>

Bits 3:4 - ADC data resolution

pub fn dmacfg(&mut self) -> DMACFG_W<'_>

Bit 1 - ADC DMA transfer configuration

pub fn dmaen(&mut self) -> DMAEN_W<'_>

Bit 0 - ADC DMA transfer enable

impl W<u32, Reg<u32, _CFGR2>>

pub fn rovsm(&mut self) -> ROVSM_W<'_>

Bit 10 - ADC oversampling mode managing interlaced conversions of ADC group regular and group injected

pub fn tovs(&mut self) -> TOVS_W<'_>

Bit 9 - ADC oversampling discontinuous mode (triggered mode) for ADC group regular

pub fn ovss(&mut self) -> OVSS_W<'_>

Bits 5:8 - ADC oversampling shift

pub fn ovsr(&mut self) -> OVSR_W<'_>

Bits 2:4 - ADC oversampling ratio

pub fn jovse(&mut self) -> JOVSE_W<'_>

Bit 1 - ADC oversampler enable on scope ADC group injected

pub fn rovse(&mut self) -> ROVSE_W<'_>

Bit 0 - ADC oversampler enable on scope ADC group regular

impl W<u32, Reg<u32, _SMPR1>>

pub fn smp9(&mut self) -> SMP9_W<'_>

Bits 27:29 - ADC channel 9 sampling time selection

pub fn smp8(&mut self) -> SMP8_W<'_>

Bits 24:26 - ADC channel 8 sampling time selection

pub fn smp7(&mut self) -> SMP7_W<'_>

Bits 21:23 - ADC channel 7 sampling time selection

pub fn smp6(&mut self) -> SMP6_W<'_>

Bits 18:20 - ADC channel 6 sampling time selection

pub fn smp5(&mut self) -> SMP5_W<'_>

Bits 15:17 - ADC channel 5 sampling time selection

pub fn smp4(&mut self) -> SMP4_W<'_>

Bits 12:14 - ADC channel 4 sampling time selection

pub fn smp3(&mut self) -> SMP3_W<'_>

Bits 9:11 - ADC channel 3 sampling time selection

pub fn smp2(&mut self) -> SMP2_W<'_>

Bits 6:8 - ADC channel 2 sampling time selection

pub fn smp1(&mut self) -> SMP1_W<'_>

Bits 3:5 - ADC channel 1 sampling time selection

impl W<u32, Reg<u32, _SMPR2>>

pub fn smp18(&mut self) -> SMP18_W<'_>

Bits 24:26 - ADC channel 18 sampling time selection

pub fn smp17(&mut self) -> SMP17_W<'_>

Bits 21:23 - ADC channel 17 sampling time selection

pub fn smp16(&mut self) -> SMP16_W<'_>

Bits 18:20 - ADC channel 16 sampling time selection

pub fn smp15(&mut self) -> SMP15_W<'_>

Bits 15:17 - ADC channel 15 sampling time selection

pub fn smp14(&mut self) -> SMP14_W<'_>

Bits 12:14 - ADC channel 14 sampling time selection

pub fn smp13(&mut self) -> SMP13_W<'_>

Bits 9:11 - ADC channel 13 sampling time selection

pub fn smp12(&mut self) -> SMP12_W<'_>

Bits 6:8 - ADC channel 12 sampling time selection

pub fn smp11(&mut self) -> SMP11_W<'_>

Bits 3:5 - ADC channel 11 sampling time selection

pub fn smp10(&mut self) -> SMP10_W<'_>

Bits 0:2 - ADC channel 10 sampling time selection

impl W<u32, Reg<u32, _TR1>>

pub fn ht1(&mut self) -> HT1_W<'_>

Bits 16:27 - ADC analog watchdog 1 threshold high

pub fn lt1(&mut self) -> LT1_W<'_>

Bits 0:11 - ADC analog watchdog 1 threshold low

impl W<u32, Reg<u32, _TR2>>

pub fn ht2(&mut self) -> HT2_W<'_>

Bits 16:23 - ADC analog watchdog 2 threshold high

pub fn lt2(&mut self) -> LT2_W<'_>

Bits 0:7 - ADC analog watchdog 2 threshold low

impl W<u32, Reg<u32, _TR3>>

pub fn ht3(&mut self) -> HT3_W<'_>

Bits 16:23 - ADC analog watchdog 3 threshold high

pub fn lt3(&mut self) -> LT3_W<'_>

Bits 0:7 - ADC analog watchdog 3 threshold low

impl W<u32, Reg<u32, _SQR1>>

pub fn sq4(&mut self) -> SQ4_W<'_>

Bits 24:28 - ADC group regular sequencer rank 4

pub fn sq3(&mut self) -> SQ3_W<'_>

Bits 18:22 - ADC group regular sequencer rank 3

pub fn sq2(&mut self) -> SQ2_W<'_>

Bits 12:16 - ADC group regular sequencer rank 2

pub fn sq1(&mut self) -> SQ1_W<'_>

Bits 6:10 - ADC group regular sequencer rank 1

pub fn l3(&mut self) -> L3_W<'_>

Bits 0:3 - L3

impl W<u32, Reg<u32, _SQR2>>

pub fn sq9(&mut self) -> SQ9_W<'_>

Bits 24:28 - ADC group regular sequencer rank 9

pub fn sq8(&mut self) -> SQ8_W<'_>

Bits 18:22 - ADC group regular sequencer rank 8

pub fn sq7(&mut self) -> SQ7_W<'_>

Bits 12:16 - ADC group regular sequencer rank 7

pub fn sq6(&mut self) -> SQ6_W<'_>

Bits 6:10 - ADC group regular sequencer rank 6

pub fn sq5(&mut self) -> SQ5_W<'_>

Bits 0:4 - ADC group regular sequencer rank 5

impl W<u32, Reg<u32, _SQR3>>

pub fn sq14(&mut self) -> SQ14_W<'_>

Bits 24:28 - ADC group regular sequencer rank 14

pub fn sq13(&mut self) -> SQ13_W<'_>

Bits 18:22 - ADC group regular sequencer rank 13

pub fn sq12(&mut self) -> SQ12_W<'_>

Bits 12:16 - ADC group regular sequencer rank 12

pub fn sq11(&mut self) -> SQ11_W<'_>

Bits 6:10 - ADC group regular sequencer rank 11

pub fn sq10(&mut self) -> SQ10_W<'_>

Bits 0:4 - ADC group regular sequencer rank 10

impl W<u32, Reg<u32, _SQR4>>

pub fn sq16(&mut self) -> SQ16_W<'_>

Bits 6:10 - ADC group regular sequencer rank 16

pub fn sq15(&mut self) -> SQ15_W<'_>

Bits 0:4 - ADC group regular sequencer rank 15

impl W<u32, Reg<u32, _DR>>

pub fn rdata_0_6(&mut self) -> RDATA_0_6_W<'_>

Bits 0:5 - Regular Data converted 0_6

impl W<u32, Reg<u32, _JSQR>>

pub fn jsq4(&mut self) -> JSQ4_W<'_>

Bits 26:30 - ADC group injected sequencer rank 4

pub fn jsq3(&mut self) -> JSQ3_W<'_>

Bits 20:24 - ADC group injected sequencer rank 3

pub fn jsq2(&mut self) -> JSQ2_W<'_>

Bits 14:18 - ADC group injected sequencer rank 2

pub fn jsq1(&mut self) -> JSQ1_W<'_>

Bits 8:12 - ADC group injected sequencer rank 1

pub fn jexten(&mut self) -> JEXTEN_W<'_>

Bits 6:7 - ADC group injected external trigger polarity

pub fn jextsel(&mut self) -> JEXTSEL_W<'_>

Bits 2:5 - ADC group injected external trigger source

pub fn jl(&mut self) -> JL_W<'_>

Bits 0:1 - ADC group injected sequencer scan length

impl W<u32, Reg<u32, _OFR1>>

pub fn offset1_en(&mut self) -> OFFSET1_EN_W<'_>

Bit 31 - ADC offset number 1 enable

pub fn offset1_ch(&mut self) -> OFFSET1_CH_W<'_>

Bits 26:30 - ADC offset number 1 channel selection

pub fn offset1(&mut self) -> OFFSET1_W<'_>

Bits 0:11 - ADC offset number 1 offset level

impl W<u32, Reg<u32, _OFR2>>

pub fn offset2_en(&mut self) -> OFFSET2_EN_W<'_>

Bit 31 - ADC offset number 2 enable

pub fn offset2_ch(&mut self) -> OFFSET2_CH_W<'_>

Bits 26:30 - ADC offset number 2 channel selection

pub fn offset2(&mut self) -> OFFSET2_W<'_>

Bits 0:11 - ADC offset number 2 offset level

impl W<u32, Reg<u32, _OFR3>>

pub fn offset3_en(&mut self) -> OFFSET3_EN_W<'_>

Bit 31 - ADC offset number 3 enable

pub fn offset3_ch(&mut self) -> OFFSET3_CH_W<'_>

Bits 26:30 - ADC offset number 3 channel selection

pub fn offset3(&mut self) -> OFFSET3_W<'_>

Bits 0:11 - ADC offset number 3 offset level

impl W<u32, Reg<u32, _OFR4>>

pub fn offset4_en(&mut self) -> OFFSET4_EN_W<'_>

Bit 31 - ADC offset number 4 enable

pub fn offset4_ch(&mut self) -> OFFSET4_CH_W<'_>

Bits 26:30 - ADC offset number 4 channel selection

pub fn offset4(&mut self) -> OFFSET4_W<'_>

Bits 0:11 - ADC offset number 4 offset level

impl W<u32, Reg<u32, _AWD2CR>>

pub fn awd2ch(&mut self) -> AWD2CH_W<'_>

Bits 0:18 - ADC analog watchdog 2 monitored channel selection

impl W<u32, Reg<u32, _AWD3CR>>

pub fn awd3ch(&mut self) -> AWD3CH_W<'_>

Bits 0:18 - ADC analog watchdog 3 monitored channel selection

impl W<u32, Reg<u32, _DIFSEL>>

pub fn difsel_1_15(&mut self) -> DIFSEL_1_15_W<'_>

Bits 1:15 - ADC channel differential or single-ended mode for channels 1 to 15

impl W<u32, Reg<u32, _CALFACT>>

pub fn calfact_d(&mut self) -> CALFACT_D_W<'_>

Bits 16:22 - ADC calibration factor in differential mode

pub fn calfact_s(&mut self) -> CALFACT_S_W<'_>

Bits 0:6 - ADC calibration factor in single-ended mode

impl W<u32, Reg<u32, _CCR>>

pub fn vbaten(&mut self) -> VBATEN_W<'_>

Bit 24 - VBAT enable

pub fn tsen(&mut self) -> TSEN_W<'_>

Bit 23 - Temperature sensor enable

pub fn vrefen(&mut self) -> VREFEN_W<'_>

Bit 22 - VREFEN

pub fn presc(&mut self) -> PRESC_W<'_>

Bits 18:21 - ADC prescaler

pub fn ckmode(&mut self) -> CKMODE_W<'_>

Bits 16:17 - ADC clock mode

impl W<u32, Reg<u32, _MODER>>

pub fn moder15(&mut self) -> MODER15_W<'_>

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn moder14(&mut self) -> MODER14_W<'_>

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn moder13(&mut self) -> MODER13_W<'_>

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn moder12(&mut self) -> MODER12_W<'_>

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn moder11(&mut self) -> MODER11_W<'_>

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn moder10(&mut self) -> MODER10_W<'_>

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn moder9(&mut self) -> MODER9_W<'_>

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn moder8(&mut self) -> MODER8_W<'_>

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn moder7(&mut self) -> MODER7_W<'_>

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn moder6(&mut self) -> MODER6_W<'_>

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn moder5(&mut self) -> MODER5_W<'_>

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn moder4(&mut self) -> MODER4_W<'_>

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn moder3(&mut self) -> MODER3_W<'_>

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn moder2(&mut self) -> MODER2_W<'_>

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn moder1(&mut self) -> MODER1_W<'_>

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn moder0(&mut self) -> MODER0_W<'_>

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _OTYPER>>

pub fn ot15(&mut self) -> OT15_W<'_>

Bit 15 - Port x configuration bits (y = 0..15)

pub fn ot14(&mut self) -> OT14_W<'_>

Bit 14 - Port x configuration bits (y = 0..15)

pub fn ot13(&mut self) -> OT13_W<'_>

Bit 13 - Port x configuration bits (y = 0..15)

pub fn ot12(&mut self) -> OT12_W<'_>

Bit 12 - Port x configuration bits (y = 0..15)

pub fn ot11(&mut self) -> OT11_W<'_>

Bit 11 - Port x configuration bits (y = 0..15)

pub fn ot10(&mut self) -> OT10_W<'_>

Bit 10 - Port x configuration bits (y = 0..15)

pub fn ot9(&mut self) -> OT9_W<'_>

Bit 9 - Port x configuration bits (y = 0..15)

pub fn ot8(&mut self) -> OT8_W<'_>

Bit 8 - Port x configuration bits (y = 0..15)

pub fn ot7(&mut self) -> OT7_W<'_>

Bit 7 - Port x configuration bits (y = 0..15)

pub fn ot6(&mut self) -> OT6_W<'_>

Bit 6 - Port x configuration bits (y = 0..15)

pub fn ot5(&mut self) -> OT5_W<'_>

Bit 5 - Port x configuration bits (y = 0..15)

pub fn ot4(&mut self) -> OT4_W<'_>

Bit 4 - Port x configuration bits (y = 0..15)

pub fn ot3(&mut self) -> OT3_W<'_>

Bit 3 - Port x configuration bits (y = 0..15)

pub fn ot2(&mut self) -> OT2_W<'_>

Bit 2 - Port x configuration bits (y = 0..15)

pub fn ot1(&mut self) -> OT1_W<'_>

Bit 1 - Port x configuration bits (y = 0..15)

pub fn ot0(&mut self) -> OT0_W<'_>

Bit 0 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _OSPEEDR>>

pub fn ospeedr15(&mut self) -> OSPEEDR15_W<'_>

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn ospeedr14(&mut self) -> OSPEEDR14_W<'_>

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn ospeedr13(&mut self) -> OSPEEDR13_W<'_>

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn ospeedr12(&mut self) -> OSPEEDR12_W<'_>

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn ospeedr11(&mut self) -> OSPEEDR11_W<'_>

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn ospeedr10(&mut self) -> OSPEEDR10_W<'_>

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn ospeedr9(&mut self) -> OSPEEDR9_W<'_>

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn ospeedr8(&mut self) -> OSPEEDR8_W<'_>

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn ospeedr7(&mut self) -> OSPEEDR7_W<'_>

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn ospeedr6(&mut self) -> OSPEEDR6_W<'_>

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn ospeedr5(&mut self) -> OSPEEDR5_W<'_>

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn ospeedr4(&mut self) -> OSPEEDR4_W<'_>

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn ospeedr3(&mut self) -> OSPEEDR3_W<'_>

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn ospeedr2(&mut self) -> OSPEEDR2_W<'_>

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn ospeedr1(&mut self) -> OSPEEDR1_W<'_>

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn ospeedr0(&mut self) -> OSPEEDR0_W<'_>

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _PUPDR>>

pub fn pupdr15(&mut self) -> PUPDR15_W<'_>

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn pupdr14(&mut self) -> PUPDR14_W<'_>

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn pupdr13(&mut self) -> PUPDR13_W<'_>

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn pupdr12(&mut self) -> PUPDR12_W<'_>

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn pupdr11(&mut self) -> PUPDR11_W<'_>

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn pupdr10(&mut self) -> PUPDR10_W<'_>

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn pupdr9(&mut self) -> PUPDR9_W<'_>

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn pupdr8(&mut self) -> PUPDR8_W<'_>

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn pupdr7(&mut self) -> PUPDR7_W<'_>

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn pupdr6(&mut self) -> PUPDR6_W<'_>

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn pupdr5(&mut self) -> PUPDR5_W<'_>

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn pupdr4(&mut self) -> PUPDR4_W<'_>

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn pupdr3(&mut self) -> PUPDR3_W<'_>

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn pupdr2(&mut self) -> PUPDR2_W<'_>

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn pupdr1(&mut self) -> PUPDR1_W<'_>

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn pupdr0(&mut self) -> PUPDR0_W<'_>

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _ODR>>

pub fn odr15(&mut self) -> ODR15_W<'_>

Bit 15 - Port output data (y = 0..15)

pub fn odr14(&mut self) -> ODR14_W<'_>

Bit 14 - Port output data (y = 0..15)

pub fn odr13(&mut self) -> ODR13_W<'_>

Bit 13 - Port output data (y = 0..15)

pub fn odr12(&mut self) -> ODR12_W<'_>

Bit 12 - Port output data (y = 0..15)

pub fn odr11(&mut self) -> ODR11_W<'_>

Bit 11 - Port output data (y = 0..15)

pub fn odr10(&mut self) -> ODR10_W<'_>

Bit 10 - Port output data (y = 0..15)

pub fn odr9(&mut self) -> ODR9_W<'_>

Bit 9 - Port output data (y = 0..15)

pub fn odr8(&mut self) -> ODR8_W<'_>

Bit 8 - Port output data (y = 0..15)

pub fn odr7(&mut self) -> ODR7_W<'_>

Bit 7 - Port output data (y = 0..15)

pub fn odr6(&mut self) -> ODR6_W<'_>

Bit 6 - Port output data (y = 0..15)

pub fn odr5(&mut self) -> ODR5_W<'_>

Bit 5 - Port output data (y = 0..15)

pub fn odr4(&mut self) -> ODR4_W<'_>

Bit 4 - Port output data (y = 0..15)

pub fn odr3(&mut self) -> ODR3_W<'_>

Bit 3 - Port output data (y = 0..15)

pub fn odr2(&mut self) -> ODR2_W<'_>

Bit 2 - Port output data (y = 0..15)

pub fn odr1(&mut self) -> ODR1_W<'_>

Bit 1 - Port output data (y = 0..15)

pub fn odr0(&mut self) -> ODR0_W<'_>

Bit 0 - Port output data (y = 0..15)

impl W<u32, Reg<u32, _BSRR>>

pub fn br15(&mut self) -> BR15_W<'_>

Bit 31 - Port x reset bit y (y = 0..15)

pub fn br14(&mut self) -> BR14_W<'_>

Bit 30 - Port x reset bit y (y = 0..15)

pub fn br13(&mut self) -> BR13_W<'_>

Bit 29 - Port x reset bit y (y = 0..15)

pub fn br12(&mut self) -> BR12_W<'_>

Bit 28 - Port x reset bit y (y = 0..15)

pub fn br11(&mut self) -> BR11_W<'_>

Bit 27 - Port x reset bit y (y = 0..15)

pub fn br10(&mut self) -> BR10_W<'_>

Bit 26 - Port x reset bit y (y = 0..15)

pub fn br9(&mut self) -> BR9_W<'_>

Bit 25 - Port x reset bit y (y = 0..15)

pub fn br8(&mut self) -> BR8_W<'_>

Bit 24 - Port x reset bit y (y = 0..15)

pub fn br7(&mut self) -> BR7_W<'_>

Bit 23 - Port x reset bit y (y = 0..15)

pub fn br6(&mut self) -> BR6_W<'_>

Bit 22 - Port x reset bit y (y = 0..15)

pub fn br5(&mut self) -> BR5_W<'_>

Bit 21 - Port x reset bit y (y = 0..15)

pub fn br4(&mut self) -> BR4_W<'_>

Bit 20 - Port x reset bit y (y = 0..15)

pub fn br3(&mut self) -> BR3_W<'_>

Bit 19 - Port x reset bit y (y = 0..15)

pub fn br2(&mut self) -> BR2_W<'_>

Bit 18 - Port x reset bit y (y = 0..15)

pub fn br1(&mut self) -> BR1_W<'_>

Bit 17 - Port x reset bit y (y = 0..15)

pub fn br0(&mut self) -> BR0_W<'_>

Bit 16 - Port x set bit y (y= 0..15)

pub fn bs15(&mut self) -> BS15_W<'_>

Bit 15 - Port x set bit y (y= 0..15)

pub fn bs14(&mut self) -> BS14_W<'_>

Bit 14 - Port x set bit y (y= 0..15)

pub fn bs13(&mut self) -> BS13_W<'_>

Bit 13 - Port x set bit y (y= 0..15)

pub fn bs12(&mut self) -> BS12_W<'_>

Bit 12 - Port x set bit y (y= 0..15)

pub fn bs11(&mut self) -> BS11_W<'_>

Bit 11 - Port x set bit y (y= 0..15)

pub fn bs10(&mut self) -> BS10_W<'_>

Bit 10 - Port x set bit y (y= 0..15)

pub fn bs9(&mut self) -> BS9_W<'_>

Bit 9 - Port x set bit y (y= 0..15)

pub fn bs8(&mut self) -> BS8_W<'_>

Bit 8 - Port x set bit y (y= 0..15)

pub fn bs7(&mut self) -> BS7_W<'_>

Bit 7 - Port x set bit y (y= 0..15)

pub fn bs6(&mut self) -> BS6_W<'_>

Bit 6 - Port x set bit y (y= 0..15)

pub fn bs5(&mut self) -> BS5_W<'_>

Bit 5 - Port x set bit y (y= 0..15)

pub fn bs4(&mut self) -> BS4_W<'_>

Bit 4 - Port x set bit y (y= 0..15)

pub fn bs3(&mut self) -> BS3_W<'_>

Bit 3 - Port x set bit y (y= 0..15)

pub fn bs2(&mut self) -> BS2_W<'_>

Bit 2 - Port x set bit y (y= 0..15)

pub fn bs1(&mut self) -> BS1_W<'_>

Bit 1 - Port x set bit y (y= 0..15)

pub fn bs0(&mut self) -> BS0_W<'_>

Bit 0 - Port x set bit y (y= 0..15)

impl W<u32, Reg<u32, _LCKR>>

pub fn lckk(&mut self) -> LCKK_W<'_>

Bit 16 - Port x lock bit y (y= 0..15)

pub fn lck15(&mut self) -> LCK15_W<'_>

Bit 15 - Port x lock bit y (y= 0..15)

pub fn lck14(&mut self) -> LCK14_W<'_>

Bit 14 - Port x lock bit y (y= 0..15)

pub fn lck13(&mut self) -> LCK13_W<'_>

Bit 13 - Port x lock bit y (y= 0..15)

pub fn lck12(&mut self) -> LCK12_W<'_>

Bit 12 - Port x lock bit y (y= 0..15)

pub fn lck11(&mut self) -> LCK11_W<'_>

Bit 11 - Port x lock bit y (y= 0..15)

pub fn lck10(&mut self) -> LCK10_W<'_>

Bit 10 - Port x lock bit y (y= 0..15)

pub fn lck9(&mut self) -> LCK9_W<'_>

Bit 9 - Port x lock bit y (y= 0..15)

pub fn lck8(&mut self) -> LCK8_W<'_>

Bit 8 - Port x lock bit y (y= 0..15)

pub fn lck7(&mut self) -> LCK7_W<'_>

Bit 7 - Port x lock bit y (y= 0..15)

pub fn lck6(&mut self) -> LCK6_W<'_>

Bit 6 - Port x lock bit y (y= 0..15)

pub fn lck5(&mut self) -> LCK5_W<'_>

Bit 5 - Port x lock bit y (y= 0..15)

pub fn lck4(&mut self) -> LCK4_W<'_>

Bit 4 - Port x lock bit y (y= 0..15)

pub fn lck3(&mut self) -> LCK3_W<'_>

Bit 3 - Port x lock bit y (y= 0..15)

pub fn lck2(&mut self) -> LCK2_W<'_>

Bit 2 - Port x lock bit y (y= 0..15)

pub fn lck1(&mut self) -> LCK1_W<'_>

Bit 1 - Port x lock bit y (y= 0..15)

pub fn lck0(&mut self) -> LCK0_W<'_>

Bit 0 - Port x lock bit y (y= 0..15)

impl W<u32, Reg<u32, _AFRL>>

pub fn afsel7(&mut self) -> AFSEL7_W<'_>

Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel6(&mut self) -> AFSEL6_W<'_>

Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel5(&mut self) -> AFSEL5_W<'_>

Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel4(&mut self) -> AFSEL4_W<'_>

Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel3(&mut self) -> AFSEL3_W<'_>

Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel2(&mut self) -> AFSEL2_W<'_>

Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel1(&mut self) -> AFSEL1_W<'_>

Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel0(&mut self) -> AFSEL0_W<'_>

Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)

impl W<u32, Reg<u32, _AFRH>>

pub fn afsel15(&mut self) -> AFSEL15_W<'_>

Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel14(&mut self) -> AFSEL14_W<'_>

Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel13(&mut self) -> AFSEL13_W<'_>

Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel12(&mut self) -> AFSEL12_W<'_>

Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel11(&mut self) -> AFSEL11_W<'_>

Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel10(&mut self) -> AFSEL10_W<'_>

Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel9(&mut self) -> AFSEL9_W<'_>

Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel8(&mut self) -> AFSEL8_W<'_>

Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)

impl W<u32, Reg<u32, _BRR>>

pub fn br0(&mut self) -> BR0_W<'_>

Bit 0 - Port Reset bit

pub fn br1(&mut self) -> BR1_W<'_>

Bit 1 - Port Reset bit

pub fn br2(&mut self) -> BR2_W<'_>

Bit 2 - Port Reset bit

pub fn br3(&mut self) -> BR3_W<'_>

Bit 3 - Port Reset bit

pub fn br4(&mut self) -> BR4_W<'_>

Bit 4 - Port Reset bit

pub fn br5(&mut self) -> BR5_W<'_>

Bit 5 - Port Reset bit

pub fn br6(&mut self) -> BR6_W<'_>

Bit 6 - Port Reset bit

pub fn br7(&mut self) -> BR7_W<'_>

Bit 7 - Port Reset bit

pub fn br8(&mut self) -> BR8_W<'_>

Bit 8 - Port Reset bit

pub fn br9(&mut self) -> BR9_W<'_>

Bit 9 - Port Reset bit

pub fn br10(&mut self) -> BR10_W<'_>

Bit 10 - Port Reset bit

pub fn br11(&mut self) -> BR11_W<'_>

Bit 11 - Port Reset bit

pub fn br12(&mut self) -> BR12_W<'_>

Bit 12 - Port Reset bit

pub fn br13(&mut self) -> BR13_W<'_>

Bit 13 - Port Reset bit

pub fn br14(&mut self) -> BR14_W<'_>

Bit 14 - Port Reset bit

pub fn br15(&mut self) -> BR15_W<'_>

Bit 15 - Port Reset bit

impl W<u32, Reg<u32, _MODER>>

pub fn moder15(&mut self) -> MODER15_W<'_>

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn moder14(&mut self) -> MODER14_W<'_>

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn moder13(&mut self) -> MODER13_W<'_>

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn moder12(&mut self) -> MODER12_W<'_>

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn moder11(&mut self) -> MODER11_W<'_>

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn moder10(&mut self) -> MODER10_W<'_>

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn moder9(&mut self) -> MODER9_W<'_>

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn moder8(&mut self) -> MODER8_W<'_>

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn moder7(&mut self) -> MODER7_W<'_>

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn moder6(&mut self) -> MODER6_W<'_>

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn moder5(&mut self) -> MODER5_W<'_>

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn moder4(&mut self) -> MODER4_W<'_>

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn moder3(&mut self) -> MODER3_W<'_>

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn moder2(&mut self) -> MODER2_W<'_>

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn moder1(&mut self) -> MODER1_W<'_>

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn moder0(&mut self) -> MODER0_W<'_>

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _OTYPER>>

pub fn ot15(&mut self) -> OT15_W<'_>

Bit 15 - Port x configuration bits (y = 0..15)

pub fn ot14(&mut self) -> OT14_W<'_>

Bit 14 - Port x configuration bits (y = 0..15)

pub fn ot13(&mut self) -> OT13_W<'_>

Bit 13 - Port x configuration bits (y = 0..15)

pub fn ot12(&mut self) -> OT12_W<'_>

Bit 12 - Port x configuration bits (y = 0..15)

pub fn ot11(&mut self) -> OT11_W<'_>

Bit 11 - Port x configuration bits (y = 0..15)

pub fn ot10(&mut self) -> OT10_W<'_>

Bit 10 - Port x configuration bits (y = 0..15)

pub fn ot9(&mut self) -> OT9_W<'_>

Bit 9 - Port x configuration bits (y = 0..15)

pub fn ot8(&mut self) -> OT8_W<'_>

Bit 8 - Port x configuration bits (y = 0..15)

pub fn ot7(&mut self) -> OT7_W<'_>

Bit 7 - Port x configuration bits (y = 0..15)

pub fn ot6(&mut self) -> OT6_W<'_>

Bit 6 - Port x configuration bits (y = 0..15)

pub fn ot5(&mut self) -> OT5_W<'_>

Bit 5 - Port x configuration bits (y = 0..15)

pub fn ot4(&mut self) -> OT4_W<'_>

Bit 4 - Port x configuration bits (y = 0..15)

pub fn ot3(&mut self) -> OT3_W<'_>

Bit 3 - Port x configuration bits (y = 0..15)

pub fn ot2(&mut self) -> OT2_W<'_>

Bit 2 - Port x configuration bits (y = 0..15)

pub fn ot1(&mut self) -> OT1_W<'_>

Bit 1 - Port x configuration bits (y = 0..15)

pub fn ot0(&mut self) -> OT0_W<'_>

Bit 0 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _OSPEEDR>>

pub fn ospeedr15(&mut self) -> OSPEEDR15_W<'_>

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn ospeedr14(&mut self) -> OSPEEDR14_W<'_>

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn ospeedr13(&mut self) -> OSPEEDR13_W<'_>

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn ospeedr12(&mut self) -> OSPEEDR12_W<'_>

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn ospeedr11(&mut self) -> OSPEEDR11_W<'_>

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn ospeedr10(&mut self) -> OSPEEDR10_W<'_>

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn ospeedr9(&mut self) -> OSPEEDR9_W<'_>

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn ospeedr8(&mut self) -> OSPEEDR8_W<'_>

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn ospeedr7(&mut self) -> OSPEEDR7_W<'_>

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn ospeedr6(&mut self) -> OSPEEDR6_W<'_>

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn ospeedr5(&mut self) -> OSPEEDR5_W<'_>

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn ospeedr4(&mut self) -> OSPEEDR4_W<'_>

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn ospeedr3(&mut self) -> OSPEEDR3_W<'_>

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn ospeedr2(&mut self) -> OSPEEDR2_W<'_>

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn ospeedr1(&mut self) -> OSPEEDR1_W<'_>

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn ospeedr0(&mut self) -> OSPEEDR0_W<'_>

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _PUPDR>>

pub fn pupdr15(&mut self) -> PUPDR15_W<'_>

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn pupdr14(&mut self) -> PUPDR14_W<'_>

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn pupdr13(&mut self) -> PUPDR13_W<'_>

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn pupdr12(&mut self) -> PUPDR12_W<'_>

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn pupdr11(&mut self) -> PUPDR11_W<'_>

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn pupdr10(&mut self) -> PUPDR10_W<'_>

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn pupdr9(&mut self) -> PUPDR9_W<'_>

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn pupdr8(&mut self) -> PUPDR8_W<'_>

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn pupdr7(&mut self) -> PUPDR7_W<'_>

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn pupdr6(&mut self) -> PUPDR6_W<'_>

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn pupdr5(&mut self) -> PUPDR5_W<'_>

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn pupdr4(&mut self) -> PUPDR4_W<'_>

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn pupdr3(&mut self) -> PUPDR3_W<'_>

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn pupdr2(&mut self) -> PUPDR2_W<'_>

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn pupdr1(&mut self) -> PUPDR1_W<'_>

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn pupdr0(&mut self) -> PUPDR0_W<'_>

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _ODR>>

pub fn odr15(&mut self) -> ODR15_W<'_>

Bit 15 - Port output data (y = 0..15)

pub fn odr14(&mut self) -> ODR14_W<'_>

Bit 14 - Port output data (y = 0..15)

pub fn odr13(&mut self) -> ODR13_W<'_>

Bit 13 - Port output data (y = 0..15)

pub fn odr12(&mut self) -> ODR12_W<'_>

Bit 12 - Port output data (y = 0..15)

pub fn odr11(&mut self) -> ODR11_W<'_>

Bit 11 - Port output data (y = 0..15)

pub fn odr10(&mut self) -> ODR10_W<'_>

Bit 10 - Port output data (y = 0..15)

pub fn odr9(&mut self) -> ODR9_W<'_>

Bit 9 - Port output data (y = 0..15)

pub fn odr8(&mut self) -> ODR8_W<'_>

Bit 8 - Port output data (y = 0..15)

pub fn odr7(&mut self) -> ODR7_W<'_>

Bit 7 - Port output data (y = 0..15)

pub fn odr6(&mut self) -> ODR6_W<'_>

Bit 6 - Port output data (y = 0..15)

pub fn odr5(&mut self) -> ODR5_W<'_>

Bit 5 - Port output data (y = 0..15)

pub fn odr4(&mut self) -> ODR4_W<'_>

Bit 4 - Port output data (y = 0..15)

pub fn odr3(&mut self) -> ODR3_W<'_>

Bit 3 - Port output data (y = 0..15)

pub fn odr2(&mut self) -> ODR2_W<'_>

Bit 2 - Port output data (y = 0..15)

pub fn odr1(&mut self) -> ODR1_W<'_>

Bit 1 - Port output data (y = 0..15)

pub fn odr0(&mut self) -> ODR0_W<'_>

Bit 0 - Port output data (y = 0..15)

impl W<u32, Reg<u32, _BSRR>>

pub fn br15(&mut self) -> BR15_W<'_>

Bit 31 - Port x reset bit y (y = 0..15)

pub fn br14(&mut self) -> BR14_W<'_>

Bit 30 - Port x reset bit y (y = 0..15)

pub fn br13(&mut self) -> BR13_W<'_>

Bit 29 - Port x reset bit y (y = 0..15)

pub fn br12(&mut self) -> BR12_W<'_>

Bit 28 - Port x reset bit y (y = 0..15)

pub fn br11(&mut self) -> BR11_W<'_>

Bit 27 - Port x reset bit y (y = 0..15)

pub fn br10(&mut self) -> BR10_W<'_>

Bit 26 - Port x reset bit y (y = 0..15)

pub fn br9(&mut self) -> BR9_W<'_>

Bit 25 - Port x reset bit y (y = 0..15)

pub fn br8(&mut self) -> BR8_W<'_>

Bit 24 - Port x reset bit y (y = 0..15)

pub fn br7(&mut self) -> BR7_W<'_>

Bit 23 - Port x reset bit y (y = 0..15)

pub fn br6(&mut self) -> BR6_W<'_>

Bit 22 - Port x reset bit y (y = 0..15)

pub fn br5(&mut self) -> BR5_W<'_>

Bit 21 - Port x reset bit y (y = 0..15)

pub fn br4(&mut self) -> BR4_W<'_>

Bit 20 - Port x reset bit y (y = 0..15)

pub fn br3(&mut self) -> BR3_W<'_>

Bit 19 - Port x reset bit y (y = 0..15)

pub fn br2(&mut self) -> BR2_W<'_>

Bit 18 - Port x reset bit y (y = 0..15)

pub fn br1(&mut self) -> BR1_W<'_>

Bit 17 - Port x reset bit y (y = 0..15)

pub fn br0(&mut self) -> BR0_W<'_>

Bit 16 - Port x set bit y (y= 0..15)

pub fn bs15(&mut self) -> BS15_W<'_>

Bit 15 - Port x set bit y (y= 0..15)

pub fn bs14(&mut self) -> BS14_W<'_>

Bit 14 - Port x set bit y (y= 0..15)

pub fn bs13(&mut self) -> BS13_W<'_>

Bit 13 - Port x set bit y (y= 0..15)

pub fn bs12(&mut self) -> BS12_W<'_>

Bit 12 - Port x set bit y (y= 0..15)

pub fn bs11(&mut self) -> BS11_W<'_>

Bit 11 - Port x set bit y (y= 0..15)

pub fn bs10(&mut self) -> BS10_W<'_>

Bit 10 - Port x set bit y (y= 0..15)

pub fn bs9(&mut self) -> BS9_W<'_>

Bit 9 - Port x set bit y (y= 0..15)

pub fn bs8(&mut self) -> BS8_W<'_>

Bit 8 - Port x set bit y (y= 0..15)

pub fn bs7(&mut self) -> BS7_W<'_>

Bit 7 - Port x set bit y (y= 0..15)

pub fn bs6(&mut self) -> BS6_W<'_>

Bit 6 - Port x set bit y (y= 0..15)

pub fn bs5(&mut self) -> BS5_W<'_>

Bit 5 - Port x set bit y (y= 0..15)

pub fn bs4(&mut self) -> BS4_W<'_>

Bit 4 - Port x set bit y (y= 0..15)

pub fn bs3(&mut self) -> BS3_W<'_>

Bit 3 - Port x set bit y (y= 0..15)

pub fn bs2(&mut self) -> BS2_W<'_>

Bit 2 - Port x set bit y (y= 0..15)

pub fn bs1(&mut self) -> BS1_W<'_>

Bit 1 - Port x set bit y (y= 0..15)

pub fn bs0(&mut self) -> BS0_W<'_>

Bit 0 - Port x set bit y (y= 0..15)

impl W<u32, Reg<u32, _LCKR>>

pub fn lckk(&mut self) -> LCKK_W<'_>

Bit 16 - Port x lock bit y (y= 0..15)

pub fn lck15(&mut self) -> LCK15_W<'_>

Bit 15 - Port x lock bit y (y= 0..15)

pub fn lck14(&mut self) -> LCK14_W<'_>

Bit 14 - Port x lock bit y (y= 0..15)

pub fn lck13(&mut self) -> LCK13_W<'_>

Bit 13 - Port x lock bit y (y= 0..15)

pub fn lck12(&mut self) -> LCK12_W<'_>

Bit 12 - Port x lock bit y (y= 0..15)

pub fn lck11(&mut self) -> LCK11_W<'_>

Bit 11 - Port x lock bit y (y= 0..15)

pub fn lck10(&mut self) -> LCK10_W<'_>

Bit 10 - Port x lock bit y (y= 0..15)

pub fn lck9(&mut self) -> LCK9_W<'_>

Bit 9 - Port x lock bit y (y= 0..15)

pub fn lck8(&mut self) -> LCK8_W<'_>

Bit 8 - Port x lock bit y (y= 0..15)

pub fn lck7(&mut self) -> LCK7_W<'_>

Bit 7 - Port x lock bit y (y= 0..15)

pub fn lck6(&mut self) -> LCK6_W<'_>

Bit 6 - Port x lock bit y (y= 0..15)

pub fn lck5(&mut self) -> LCK5_W<'_>

Bit 5 - Port x lock bit y (y= 0..15)

pub fn lck4(&mut self) -> LCK4_W<'_>

Bit 4 - Port x lock bit y (y= 0..15)

pub fn lck3(&mut self) -> LCK3_W<'_>

Bit 3 - Port x lock bit y (y= 0..15)

pub fn lck2(&mut self) -> LCK2_W<'_>

Bit 2 - Port x lock bit y (y= 0..15)

pub fn lck1(&mut self) -> LCK1_W<'_>

Bit 1 - Port x lock bit y (y= 0..15)

pub fn lck0(&mut self) -> LCK0_W<'_>

Bit 0 - Port x lock bit y (y= 0..15)

impl W<u32, Reg<u32, _AFRL>>

pub fn afsel7(&mut self) -> AFSEL7_W<'_>

Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel6(&mut self) -> AFSEL6_W<'_>

Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel5(&mut self) -> AFSEL5_W<'_>

Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel4(&mut self) -> AFSEL4_W<'_>

Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel3(&mut self) -> AFSEL3_W<'_>

Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel2(&mut self) -> AFSEL2_W<'_>

Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel1(&mut self) -> AFSEL1_W<'_>

Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel0(&mut self) -> AFSEL0_W<'_>

Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)

impl W<u32, Reg<u32, _AFRH>>

pub fn afsel15(&mut self) -> AFSEL15_W<'_>

Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel14(&mut self) -> AFSEL14_W<'_>

Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel13(&mut self) -> AFSEL13_W<'_>

Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel12(&mut self) -> AFSEL12_W<'_>

Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel11(&mut self) -> AFSEL11_W<'_>

Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel10(&mut self) -> AFSEL10_W<'_>

Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel9(&mut self) -> AFSEL9_W<'_>

Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel8(&mut self) -> AFSEL8_W<'_>

Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)

impl W<u32, Reg<u32, _BRR>>

pub fn br0(&mut self) -> BR0_W<'_>

Bit 0 - Port Reset bit

pub fn br1(&mut self) -> BR1_W<'_>

Bit 1 - Port Reset bit

pub fn br2(&mut self) -> BR2_W<'_>

Bit 2 - Port Reset bit

pub fn br3(&mut self) -> BR3_W<'_>

Bit 3 - Port Reset bit

pub fn br4(&mut self) -> BR4_W<'_>

Bit 4 - Port Reset bit

pub fn br5(&mut self) -> BR5_W<'_>

Bit 5 - Port Reset bit

pub fn br6(&mut self) -> BR6_W<'_>

Bit 6 - Port Reset bit

pub fn br7(&mut self) -> BR7_W<'_>

Bit 7 - Port Reset bit

pub fn br8(&mut self) -> BR8_W<'_>

Bit 8 - Port Reset bit

pub fn br9(&mut self) -> BR9_W<'_>

Bit 9 - Port Reset bit

pub fn br10(&mut self) -> BR10_W<'_>

Bit 10 - Port Reset bit

pub fn br11(&mut self) -> BR11_W<'_>

Bit 11 - Port Reset bit

pub fn br12(&mut self) -> BR12_W<'_>

Bit 12 - Port Reset bit

pub fn br13(&mut self) -> BR13_W<'_>

Bit 13 - Port Reset bit

pub fn br14(&mut self) -> BR14_W<'_>

Bit 14 - Port Reset bit

pub fn br15(&mut self) -> BR15_W<'_>

Bit 15 - Port Reset bit

impl W<u32, Reg<u32, _MODER>>

pub fn moder15(&mut self) -> MODER15_W<'_>

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn moder14(&mut self) -> MODER14_W<'_>

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn moder13(&mut self) -> MODER13_W<'_>

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn moder12(&mut self) -> MODER12_W<'_>

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn moder11(&mut self) -> MODER11_W<'_>

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn moder10(&mut self) -> MODER10_W<'_>

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn moder9(&mut self) -> MODER9_W<'_>

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn moder8(&mut self) -> MODER8_W<'_>

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn moder7(&mut self) -> MODER7_W<'_>

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn moder6(&mut self) -> MODER6_W<'_>

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn moder5(&mut self) -> MODER5_W<'_>

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn moder4(&mut self) -> MODER4_W<'_>

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn moder3(&mut self) -> MODER3_W<'_>

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn moder2(&mut self) -> MODER2_W<'_>

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn moder1(&mut self) -> MODER1_W<'_>

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn moder0(&mut self) -> MODER0_W<'_>

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _OTYPER>>

pub fn ot15(&mut self) -> OT15_W<'_>

Bit 15 - Port x configuration bits (y = 0..15)

pub fn ot14(&mut self) -> OT14_W<'_>

Bit 14 - Port x configuration bits (y = 0..15)

pub fn ot13(&mut self) -> OT13_W<'_>

Bit 13 - Port x configuration bits (y = 0..15)

pub fn ot12(&mut self) -> OT12_W<'_>

Bit 12 - Port x configuration bits (y = 0..15)

pub fn ot11(&mut self) -> OT11_W<'_>

Bit 11 - Port x configuration bits (y = 0..15)

pub fn ot10(&mut self) -> OT10_W<'_>

Bit 10 - Port x configuration bits (y = 0..15)

pub fn ot9(&mut self) -> OT9_W<'_>

Bit 9 - Port x configuration bits (y = 0..15)

pub fn ot8(&mut self) -> OT8_W<'_>

Bit 8 - Port x configuration bits (y = 0..15)

pub fn ot7(&mut self) -> OT7_W<'_>

Bit 7 - Port x configuration bits (y = 0..15)

pub fn ot6(&mut self) -> OT6_W<'_>

Bit 6 - Port x configuration bits (y = 0..15)

pub fn ot5(&mut self) -> OT5_W<'_>

Bit 5 - Port x configuration bits (y = 0..15)

pub fn ot4(&mut self) -> OT4_W<'_>

Bit 4 - Port x configuration bits (y = 0..15)

pub fn ot3(&mut self) -> OT3_W<'_>

Bit 3 - Port x configuration bits (y = 0..15)

pub fn ot2(&mut self) -> OT2_W<'_>

Bit 2 - Port x configuration bits (y = 0..15)

pub fn ot1(&mut self) -> OT1_W<'_>

Bit 1 - Port x configuration bits (y = 0..15)

pub fn ot0(&mut self) -> OT0_W<'_>

Bit 0 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _OSPEEDR>>

pub fn ospeedr15(&mut self) -> OSPEEDR15_W<'_>

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn ospeedr14(&mut self) -> OSPEEDR14_W<'_>

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn ospeedr13(&mut self) -> OSPEEDR13_W<'_>

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn ospeedr12(&mut self) -> OSPEEDR12_W<'_>

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn ospeedr11(&mut self) -> OSPEEDR11_W<'_>

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn ospeedr10(&mut self) -> OSPEEDR10_W<'_>

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn ospeedr9(&mut self) -> OSPEEDR9_W<'_>

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn ospeedr8(&mut self) -> OSPEEDR8_W<'_>

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn ospeedr7(&mut self) -> OSPEEDR7_W<'_>

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn ospeedr6(&mut self) -> OSPEEDR6_W<'_>

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn ospeedr5(&mut self) -> OSPEEDR5_W<'_>

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn ospeedr4(&mut self) -> OSPEEDR4_W<'_>

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn ospeedr3(&mut self) -> OSPEEDR3_W<'_>

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn ospeedr2(&mut self) -> OSPEEDR2_W<'_>

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn ospeedr1(&mut self) -> OSPEEDR1_W<'_>

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn ospeedr0(&mut self) -> OSPEEDR0_W<'_>

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _PUPDR>>

pub fn pupdr15(&mut self) -> PUPDR15_W<'_>

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn pupdr14(&mut self) -> PUPDR14_W<'_>

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn pupdr13(&mut self) -> PUPDR13_W<'_>

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn pupdr12(&mut self) -> PUPDR12_W<'_>

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn pupdr11(&mut self) -> PUPDR11_W<'_>

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn pupdr10(&mut self) -> PUPDR10_W<'_>

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn pupdr9(&mut self) -> PUPDR9_W<'_>

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn pupdr8(&mut self) -> PUPDR8_W<'_>

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn pupdr7(&mut self) -> PUPDR7_W<'_>

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn pupdr6(&mut self) -> PUPDR6_W<'_>

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn pupdr5(&mut self) -> PUPDR5_W<'_>

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn pupdr4(&mut self) -> PUPDR4_W<'_>

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn pupdr3(&mut self) -> PUPDR3_W<'_>

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn pupdr2(&mut self) -> PUPDR2_W<'_>

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn pupdr1(&mut self) -> PUPDR1_W<'_>

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn pupdr0(&mut self) -> PUPDR0_W<'_>

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _ODR>>

pub fn odr15(&mut self) -> ODR15_W<'_>

Bit 15 - Port output data (y = 0..15)

pub fn odr14(&mut self) -> ODR14_W<'_>

Bit 14 - Port output data (y = 0..15)

pub fn odr13(&mut self) -> ODR13_W<'_>

Bit 13 - Port output data (y = 0..15)

pub fn odr12(&mut self) -> ODR12_W<'_>

Bit 12 - Port output data (y = 0..15)

pub fn odr11(&mut self) -> ODR11_W<'_>

Bit 11 - Port output data (y = 0..15)

pub fn odr10(&mut self) -> ODR10_W<'_>

Bit 10 - Port output data (y = 0..15)

pub fn odr9(&mut self) -> ODR9_W<'_>

Bit 9 - Port output data (y = 0..15)

pub fn odr8(&mut self) -> ODR8_W<'_>

Bit 8 - Port output data (y = 0..15)

pub fn odr7(&mut self) -> ODR7_W<'_>

Bit 7 - Port output data (y = 0..15)

pub fn odr6(&mut self) -> ODR6_W<'_>

Bit 6 - Port output data (y = 0..15)

pub fn odr5(&mut self) -> ODR5_W<'_>

Bit 5 - Port output data (y = 0..15)

pub fn odr4(&mut self) -> ODR4_W<'_>

Bit 4 - Port output data (y = 0..15)

pub fn odr3(&mut self) -> ODR3_W<'_>

Bit 3 - Port output data (y = 0..15)

pub fn odr2(&mut self) -> ODR2_W<'_>

Bit 2 - Port output data (y = 0..15)

pub fn odr1(&mut self) -> ODR1_W<'_>

Bit 1 - Port output data (y = 0..15)

pub fn odr0(&mut self) -> ODR0_W<'_>

Bit 0 - Port output data (y = 0..15)

impl W<u32, Reg<u32, _BSRR>>

pub fn br15(&mut self) -> BR15_W<'_>

Bit 31 - Port x reset bit y (y = 0..15)

pub fn br14(&mut self) -> BR14_W<'_>

Bit 30 - Port x reset bit y (y = 0..15)

pub fn br13(&mut self) -> BR13_W<'_>

Bit 29 - Port x reset bit y (y = 0..15)

pub fn br12(&mut self) -> BR12_W<'_>

Bit 28 - Port x reset bit y (y = 0..15)

pub fn br11(&mut self) -> BR11_W<'_>

Bit 27 - Port x reset bit y (y = 0..15)

pub fn br10(&mut self) -> BR10_W<'_>

Bit 26 - Port x reset bit y (y = 0..15)

pub fn br9(&mut self) -> BR9_W<'_>

Bit 25 - Port x reset bit y (y = 0..15)

pub fn br8(&mut self) -> BR8_W<'_>

Bit 24 - Port x reset bit y (y = 0..15)

pub fn br7(&mut self) -> BR7_W<'_>

Bit 23 - Port x reset bit y (y = 0..15)

pub fn br6(&mut self) -> BR6_W<'_>

Bit 22 - Port x reset bit y (y = 0..15)

pub fn br5(&mut self) -> BR5_W<'_>

Bit 21 - Port x reset bit y (y = 0..15)

pub fn br4(&mut self) -> BR4_W<'_>

Bit 20 - Port x reset bit y (y = 0..15)

pub fn br3(&mut self) -> BR3_W<'_>

Bit 19 - Port x reset bit y (y = 0..15)

pub fn br2(&mut self) -> BR2_W<'_>

Bit 18 - Port x reset bit y (y = 0..15)

pub fn br1(&mut self) -> BR1_W<'_>

Bit 17 - Port x reset bit y (y = 0..15)

pub fn br0(&mut self) -> BR0_W<'_>

Bit 16 - Port x set bit y (y= 0..15)

pub fn bs15(&mut self) -> BS15_W<'_>

Bit 15 - Port x set bit y (y= 0..15)

pub fn bs14(&mut self) -> BS14_W<'_>

Bit 14 - Port x set bit y (y= 0..15)

pub fn bs13(&mut self) -> BS13_W<'_>

Bit 13 - Port x set bit y (y= 0..15)

pub fn bs12(&mut self) -> BS12_W<'_>

Bit 12 - Port x set bit y (y= 0..15)

pub fn bs11(&mut self) -> BS11_W<'_>

Bit 11 - Port x set bit y (y= 0..15)

pub fn bs10(&mut self) -> BS10_W<'_>

Bit 10 - Port x set bit y (y= 0..15)

pub fn bs9(&mut self) -> BS9_W<'_>

Bit 9 - Port x set bit y (y= 0..15)

pub fn bs8(&mut self) -> BS8_W<'_>

Bit 8 - Port x set bit y (y= 0..15)

pub fn bs7(&mut self) -> BS7_W<'_>

Bit 7 - Port x set bit y (y= 0..15)

pub fn bs6(&mut self) -> BS6_W<'_>

Bit 6 - Port x set bit y (y= 0..15)

pub fn bs5(&mut self) -> BS5_W<'_>

Bit 5 - Port x set bit y (y= 0..15)

pub fn bs4(&mut self) -> BS4_W<'_>

Bit 4 - Port x set bit y (y= 0..15)

pub fn bs3(&mut self) -> BS3_W<'_>

Bit 3 - Port x set bit y (y= 0..15)

pub fn bs2(&mut self) -> BS2_W<'_>

Bit 2 - Port x set bit y (y= 0..15)

pub fn bs1(&mut self) -> BS1_W<'_>

Bit 1 - Port x set bit y (y= 0..15)

pub fn bs0(&mut self) -> BS0_W<'_>

Bit 0 - Port x set bit y (y= 0..15)

impl W<u32, Reg<u32, _LCKR>>

pub fn lckk(&mut self) -> LCKK_W<'_>

Bit 16 - Port x lock bit y (y= 0..15)

pub fn lck15(&mut self) -> LCK15_W<'_>

Bit 15 - Port x lock bit y (y= 0..15)

pub fn lck14(&mut self) -> LCK14_W<'_>

Bit 14 - Port x lock bit y (y= 0..15)

pub fn lck13(&mut self) -> LCK13_W<'_>

Bit 13 - Port x lock bit y (y= 0..15)

pub fn lck12(&mut self) -> LCK12_W<'_>

Bit 12 - Port x lock bit y (y= 0..15)

pub fn lck11(&mut self) -> LCK11_W<'_>

Bit 11 - Port x lock bit y (y= 0..15)

pub fn lck10(&mut self) -> LCK10_W<'_>

Bit 10 - Port x lock bit y (y= 0..15)

pub fn lck9(&mut self) -> LCK9_W<'_>

Bit 9 - Port x lock bit y (y= 0..15)

pub fn lck8(&mut self) -> LCK8_W<'_>

Bit 8 - Port x lock bit y (y= 0..15)

pub fn lck7(&mut self) -> LCK7_W<'_>

Bit 7 - Port x lock bit y (y= 0..15)

pub fn lck6(&mut self) -> LCK6_W<'_>

Bit 6 - Port x lock bit y (y= 0..15)

pub fn lck5(&mut self) -> LCK5_W<'_>

Bit 5 - Port x lock bit y (y= 0..15)

pub fn lck4(&mut self) -> LCK4_W<'_>

Bit 4 - Port x lock bit y (y= 0..15)

pub fn lck3(&mut self) -> LCK3_W<'_>

Bit 3 - Port x lock bit y (y= 0..15)

pub fn lck2(&mut self) -> LCK2_W<'_>

Bit 2 - Port x lock bit y (y= 0..15)

pub fn lck1(&mut self) -> LCK1_W<'_>

Bit 1 - Port x lock bit y (y= 0..15)

pub fn lck0(&mut self) -> LCK0_W<'_>

Bit 0 - Port x lock bit y (y= 0..15)

impl W<u32, Reg<u32, _AFRL>>

pub fn afsel7(&mut self) -> AFSEL7_W<'_>

Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel6(&mut self) -> AFSEL6_W<'_>

Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel5(&mut self) -> AFSEL5_W<'_>

Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel4(&mut self) -> AFSEL4_W<'_>

Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel3(&mut self) -> AFSEL3_W<'_>

Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel2(&mut self) -> AFSEL2_W<'_>

Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel1(&mut self) -> AFSEL1_W<'_>

Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel0(&mut self) -> AFSEL0_W<'_>

Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)

impl W<u32, Reg<u32, _AFRH>>

pub fn afsel15(&mut self) -> AFSEL15_W<'_>

Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel14(&mut self) -> AFSEL14_W<'_>

Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel13(&mut self) -> AFSEL13_W<'_>

Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel12(&mut self) -> AFSEL12_W<'_>

Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel11(&mut self) -> AFSEL11_W<'_>

Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel10(&mut self) -> AFSEL10_W<'_>

Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel9(&mut self) -> AFSEL9_W<'_>

Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel8(&mut self) -> AFSEL8_W<'_>

Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)

impl W<u32, Reg<u32, _BRR>>

pub fn br0(&mut self) -> BR0_W<'_>

Bit 0 - Port Reset bit

pub fn br1(&mut self) -> BR1_W<'_>

Bit 1 - Port Reset bit

pub fn br2(&mut self) -> BR2_W<'_>

Bit 2 - Port Reset bit

pub fn br3(&mut self) -> BR3_W<'_>

Bit 3 - Port Reset bit

pub fn br4(&mut self) -> BR4_W<'_>

Bit 4 - Port Reset bit

pub fn br5(&mut self) -> BR5_W<'_>

Bit 5 - Port Reset bit

pub fn br6(&mut self) -> BR6_W<'_>

Bit 6 - Port Reset bit

pub fn br7(&mut self) -> BR7_W<'_>

Bit 7 - Port Reset bit

pub fn br8(&mut self) -> BR8_W<'_>

Bit 8 - Port Reset bit

pub fn br9(&mut self) -> BR9_W<'_>

Bit 9 - Port Reset bit

pub fn br10(&mut self) -> BR10_W<'_>

Bit 10 - Port Reset bit

pub fn br11(&mut self) -> BR11_W<'_>

Bit 11 - Port Reset bit

pub fn br12(&mut self) -> BR12_W<'_>

Bit 12 - Port Reset bit

pub fn br13(&mut self) -> BR13_W<'_>

Bit 13 - Port Reset bit

pub fn br14(&mut self) -> BR14_W<'_>

Bit 14 - Port Reset bit

pub fn br15(&mut self) -> BR15_W<'_>

Bit 15 - Port Reset bit

impl W<u32, Reg<u32, _MODER>>

pub fn moder4(&mut self) -> MODER4_W<'_>

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn moder3(&mut self) -> MODER3_W<'_>

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn moder2(&mut self) -> MODER2_W<'_>

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn moder1(&mut self) -> MODER1_W<'_>

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn moder0(&mut self) -> MODER0_W<'_>

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _OTYPER>>

pub fn ot4(&mut self) -> OT4_W<'_>

Bit 4 - Port x configuration bits (y = 0..15)

pub fn ot3(&mut self) -> OT3_W<'_>

Bit 3 - Port x configuration bits (y = 0..15)

pub fn ot2(&mut self) -> OT2_W<'_>

Bit 2 - Port x configuration bits (y = 0..15)

pub fn ot1(&mut self) -> OT1_W<'_>

Bit 1 - Port x configuration bits (y = 0..15)

pub fn ot0(&mut self) -> OT0_W<'_>

Bit 0 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _OSPEEDR>>

pub fn ospeedr4(&mut self) -> OSPEEDR4_W<'_>

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn ospeedr3(&mut self) -> OSPEEDR3_W<'_>

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn ospeedr2(&mut self) -> OSPEEDR2_W<'_>

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn ospeedr1(&mut self) -> OSPEEDR1_W<'_>

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn ospeedr0(&mut self) -> OSPEEDR0_W<'_>

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _PUPDR>>

pub fn pupdr4(&mut self) -> PUPDR4_W<'_>

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn pupdr3(&mut self) -> PUPDR3_W<'_>

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn pupdr2(&mut self) -> PUPDR2_W<'_>

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn pupdr1(&mut self) -> PUPDR1_W<'_>

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn pupdr0(&mut self) -> PUPDR0_W<'_>

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _ODR>>

pub fn odr4(&mut self) -> ODR4_W<'_>

Bit 4 - Port output data (y = 0..15)

pub fn odr3(&mut self) -> ODR3_W<'_>

Bit 3 - Port output data (y = 0..15)

pub fn odr2(&mut self) -> ODR2_W<'_>

Bit 2 - Port output data (y = 0..15)

pub fn odr1(&mut self) -> ODR1_W<'_>

Bit 1 - Port output data (y = 0..15)

pub fn odr0(&mut self) -> ODR0_W<'_>

Bit 0 - Port output data (y = 0..15)

impl W<u32, Reg<u32, _BSRR>>

pub fn br4(&mut self) -> BR4_W<'_>

Bit 20 - Port x reset bit y (y = 0..15)

pub fn br3(&mut self) -> BR3_W<'_>

Bit 19 - Port x reset bit y (y = 0..15)

pub fn br2(&mut self) -> BR2_W<'_>

Bit 18 - Port x reset bit y (y = 0..15)

pub fn br1(&mut self) -> BR1_W<'_>

Bit 17 - Port x reset bit y (y = 0..15)

pub fn br0(&mut self) -> BR0_W<'_>

Bit 16 - Port x set bit y (y= 0..15)

pub fn bs4(&mut self) -> BS4_W<'_>

Bit 4 - Port x set bit y (y= 0..15)

pub fn bs3(&mut self) -> BS3_W<'_>

Bit 3 - Port x set bit y (y= 0..15)

pub fn bs2(&mut self) -> BS2_W<'_>

Bit 2 - Port x set bit y (y= 0..15)

pub fn bs1(&mut self) -> BS1_W<'_>

Bit 1 - Port x set bit y (y= 0..15)

pub fn bs0(&mut self) -> BS0_W<'_>

Bit 0 - Port x set bit y (y= 0..15)

impl W<u32, Reg<u32, _LCKR>>

pub fn lckk(&mut self) -> LCKK_W<'_>

Bit 16 - Port x lock bit y (y= 0..15)

pub fn lck4(&mut self) -> LCK4_W<'_>

Bit 4 - Port x lock bit y (y= 0..15)

pub fn lck3(&mut self) -> LCK3_W<'_>

Bit 3 - Port x lock bit y (y= 0..15)

pub fn lck2(&mut self) -> LCK2_W<'_>

Bit 2 - Port x lock bit y (y= 0..15)

pub fn lck1(&mut self) -> LCK1_W<'_>

Bit 1 - Port x lock bit y (y= 0..15)

pub fn lck0(&mut self) -> LCK0_W<'_>

Bit 0 - Port x lock bit y (y= 0..15)

impl W<u32, Reg<u32, _AFRL>>

pub fn afsel4(&mut self) -> AFSEL4_W<'_>

Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel3(&mut self) -> AFSEL3_W<'_>

Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel2(&mut self) -> AFSEL2_W<'_>

Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel1(&mut self) -> AFSEL1_W<'_>

Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel0(&mut self) -> AFSEL0_W<'_>

Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)

impl W<u32, Reg<u32, _AFRH>>

pub fn afsel15(&mut self) -> AFSEL15_W<'_>

Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel14(&mut self) -> AFSEL14_W<'_>

Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel13(&mut self) -> AFSEL13_W<'_>

Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel12(&mut self) -> AFSEL12_W<'_>

Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel11(&mut self) -> AFSEL11_W<'_>

Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel10(&mut self) -> AFSEL10_W<'_>

Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel9(&mut self) -> AFSEL9_W<'_>

Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel8(&mut self) -> AFSEL8_W<'_>

Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)

impl W<u32, Reg<u32, _BRR>>

pub fn br0(&mut self) -> BR0_W<'_>

Bit 0 - Port Reset bit

pub fn br1(&mut self) -> BR1_W<'_>

Bit 1 - Port Reset bit

pub fn br2(&mut self) -> BR2_W<'_>

Bit 2 - Port Reset bit

pub fn br3(&mut self) -> BR3_W<'_>

Bit 3 - Port Reset bit

pub fn br4(&mut self) -> BR4_W<'_>

Bit 4 - Port Reset bit

impl W<u32, Reg<u32, _MODER>>

pub fn moder3(&mut self) -> MODER3_W<'_>

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn moder1(&mut self) -> MODER1_W<'_>

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn moder0(&mut self) -> MODER0_W<'_>

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _OTYPER>>

pub fn ot3(&mut self) -> OT3_W<'_>

Bit 3 - Port x configuration bits (y = 0..15)

pub fn ot1(&mut self) -> OT1_W<'_>

Bit 1 - Port x configuration bits (y = 0..15)

pub fn ot0(&mut self) -> OT0_W<'_>

Bit 0 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _OSPEEDR>>

pub fn ospeedr3(&mut self) -> OSPEEDR3_W<'_>

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn ospeedr1(&mut self) -> OSPEEDR1_W<'_>

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn ospeedr0(&mut self) -> OSPEEDR0_W<'_>

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _PUPDR>>

pub fn pupdr3(&mut self) -> PUPDR3_W<'_>

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn pupdr1(&mut self) -> PUPDR1_W<'_>

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn pupdr0(&mut self) -> PUPDR0_W<'_>

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _ODR>>

pub fn odr3(&mut self) -> ODR3_W<'_>

Bit 3 - Port output data (y = 0..15)

pub fn odr1(&mut self) -> ODR1_W<'_>

Bit 1 - Port output data (y = 0..15)

pub fn odr0(&mut self) -> ODR0_W<'_>

Bit 0 - Port output data (y = 0..15)

impl W<u32, Reg<u32, _BSRR>>

pub fn br3(&mut self) -> BR3_W<'_>

Bit 19 - Port x reset bit y (y = 0..15)

pub fn br1(&mut self) -> BR1_W<'_>

Bit 17 - Port x reset bit y (y = 0..15)

pub fn br0(&mut self) -> BR0_W<'_>

Bit 16 - Port x set bit y (y= 0..15)

pub fn bs3(&mut self) -> BS3_W<'_>

Bit 3 - Port x set bit y (y= 0..15)

pub fn bs1(&mut self) -> BS1_W<'_>

Bit 1 - Port x set bit y (y= 0..15)

pub fn bs0(&mut self) -> BS0_W<'_>

Bit 0 - Port x set bit y (y= 0..15)

impl W<u32, Reg<u32, _LCKR>>

pub fn lckk(&mut self) -> LCKK_W<'_>

Bit 16 - Port x lock bit y (y= 0..15)

pub fn lck3(&mut self) -> LCK3_W<'_>

Bit 3 - Port x lock bit y (y= 0..15)

pub fn lck1(&mut self) -> LCK1_W<'_>

Bit 1 - Port x lock bit y (y= 0..15)

pub fn lck0(&mut self) -> LCK0_W<'_>

Bit 0 - Port x lock bit y (y= 0..15)

impl W<u32, Reg<u32, _AFRL>>

pub fn afsel3(&mut self) -> AFSEL3_W<'_>

Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel1(&mut self) -> AFSEL1_W<'_>

Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel0(&mut self) -> AFSEL0_W<'_>

Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)

impl W<u32, Reg<u32, _AFRH>>

pub fn afsel15(&mut self) -> AFSEL15_W<'_>

Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel14(&mut self) -> AFSEL14_W<'_>

Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel13(&mut self) -> AFSEL13_W<'_>

Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel12(&mut self) -> AFSEL12_W<'_>

Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel11(&mut self) -> AFSEL11_W<'_>

Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel10(&mut self) -> AFSEL10_W<'_>

Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel9(&mut self) -> AFSEL9_W<'_>

Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel8(&mut self) -> AFSEL8_W<'_>

Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)

impl W<u32, Reg<u32, _BRR>>

pub fn br0(&mut self) -> BR0_W<'_>

Bit 0 - Port Reset bit

pub fn br1(&mut self) -> BR1_W<'_>

Bit 1 - Port Reset bit

pub fn br3(&mut self) -> BR3_W<'_>

Bit 3 - Port Reset bit

impl W<u32, Reg<u32, _CR1>>

pub fn mcken(&mut self) -> MCKEN_W<'_>

Bit 27 - Master clock generation enable

pub fn osr(&mut self) -> OSR_W<'_>

Bit 26 - Oversampling ratio for master clock

pub fn mckdiv(&mut self) -> MCKDIV_W<'_>

Bits 20:25 - Master clock divider

pub fn nodiv(&mut self) -> NODIV_W<'_>

Bit 19 - No divider

pub fn dmaen(&mut self) -> DMAEN_W<'_>

Bit 17 - DMA enable

pub fn saien(&mut self) -> SAIEN_W<'_>

Bit 16 - Audio block B enable

pub fn outdriv(&mut self) -> OUTDRIV_W<'_>

Bit 13 - Output drive

pub fn mono(&mut self) -> MONO_W<'_>

Bit 12 - Mono mode

pub fn syncen(&mut self) -> SYNCEN_W<'_>

Bits 10:11 - Synchronization enable

pub fn ckstr(&mut self) -> CKSTR_W<'_>

Bit 9 - Clock strobing edge

pub fn lsbfirst(&mut self) -> LSBFIRST_W<'_>

Bit 8 - Least significant bit first

pub fn ds(&mut self) -> DS_W<'_>

Bits 5:7 - Data size

pub fn prtcfg(&mut self) -> PRTCFG_W<'_>

Bits 2:3 - Protocol configuration

pub fn mode(&mut self) -> MODE_W<'_>

Bits 0:1 - Audio block mode

impl W<u32, Reg<u32, _CR2>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 14:15 - Companding mode

pub fn cpl(&mut self) -> CPL_W<'_>

Bit 13 - Complement bit

pub fn mutecn(&mut self) -> MUTECN_W<'_>

Bits 7:12 - Mute counter

pub fn muteval(&mut self) -> MUTEVAL_W<'_>

Bit 6 - Mute value

pub fn mute(&mut self) -> MUTE_W<'_>

Bit 5 - Mute

pub fn tris(&mut self) -> TRIS_W<'_>

Bit 4 - Tristate management on data line

pub fn fflush(&mut self) -> FFLUSH_W<'_>

Bit 3 - FIFO flush

pub fn fth(&mut self) -> FTH_W<'_>

Bits 0:2 - FIFO threshold

impl W<u32, Reg<u32, _FRCR>>

pub fn fsoff(&mut self) -> FSOFF_W<'_>

Bit 18 - Frame synchronization offset

pub fn fspol(&mut self) -> FSPOL_W<'_>

Bit 17 - Frame synchronization polarity

pub fn fsdef(&mut self) -> FSDEF_W<'_>

Bit 16 - Frame synchronization definition

pub fn fsall(&mut self) -> FSALL_W<'_>

Bits 8:14 - Frame synchronization active level length

pub fn frl(&mut self) -> FRL_W<'_>

Bits 0:7 - Frame length

impl W<u32, Reg<u32, _SLOTR>>

pub fn sloten(&mut self) -> SLOTEN_W<'_>

Bits 16:31 - Slot enable

pub fn nbslot(&mut self) -> NBSLOT_W<'_>

Bits 8:11 - Number of slots in an audio frame

pub fn slotsz(&mut self) -> SLOTSZ_W<'_>

Bits 6:7 - Slot size

pub fn fboff(&mut self) -> FBOFF_W<'_>

Bits 0:4 - First bit offset

impl W<u32, Reg<u32, _IM>>

pub fn lfsdetie(&mut self) -> LFSDETIE_W<'_>

Bit 6 - Late frame synchronization detection interrupt enable

pub fn afsdetie(&mut self) -> AFSDETIE_W<'_>

Bit 5 - Anticipated frame synchronization detection interrupt enable

pub fn cnrdyie(&mut self) -> CNRDYIE_W<'_>

Bit 4 - Codec not ready interrupt enable

pub fn freqie(&mut self) -> FREQIE_W<'_>

Bit 3 - FIFO request interrupt enable

pub fn wckcfgie(&mut self) -> WCKCFGIE_W<'_>

Bit 2 - Wrong clock configuration interrupt enable

pub fn mutedetie(&mut self) -> MUTEDETIE_W<'_>

Bit 1 - Mute detection interrupt enable

pub fn ovrudrie(&mut self) -> OVRUDRIE_W<'_>

Bit 0 - Overrun/underrun interrupt enable

impl W<u32, Reg<u32, _CLRFR>>

pub fn clfsdet(&mut self) -> CLFSDET_W<'_>

Bit 6 - Clear late frame synchronization detection flag

pub fn cafsdet(&mut self) -> CAFSDET_W<'_>

Bit 5 - Clear anticipated frame synchronization detection flag

pub fn ccnrdy(&mut self) -> CCNRDY_W<'_>

Bit 4 - Clear codec not ready flag

pub fn cwckcfg(&mut self) -> CWCKCFG_W<'_>

Bit 2 - Clear wrong clock configuration flag

pub fn cmutedet(&mut self) -> CMUTEDET_W<'_>

Bit 1 - Mute detection flag

pub fn covrudr(&mut self) -> COVRUDR_W<'_>

Bit 0 - Clear overrun / underrun

impl W<u32, Reg<u32, _DR>>

pub fn data(&mut self) -> DATA_W<'_>

Bits 0:31 - Data

impl W<u32, Reg<u32, _GCR>>

pub fn syncout(&mut self) -> SYNCOUT_W<'_>

Bits 4:5 - Synchronization outputs

pub fn syncin(&mut self) -> SYNCIN_W<'_>

Bits 0:1 - Synchronization inputs

impl W<u32, Reg<u32, _PDMCR>>

pub fn cken4(&mut self) -> CKEN4_W<'_>

Bit 11 - Clock enable of bitstream clock number 4

pub fn cken3(&mut self) -> CKEN3_W<'_>

Bit 10 - Clock enable of bitstream clock number 3

pub fn cken2(&mut self) -> CKEN2_W<'_>

Bit 9 - Clock enable of bitstream clock number 2

pub fn cken1(&mut self) -> CKEN1_W<'_>

Bit 8 - Clock enable of bitstream clock number 1

pub fn micnbr(&mut self) -> MICNBR_W<'_>

Bits 4:5 - Number of microphones

pub fn pdmen(&mut self) -> PDMEN_W<'_>

Bit 0 - PDM enable

impl W<u32, Reg<u32, _PDMDLY>>

pub fn dlym4r(&mut self) -> DLYM4R_W<'_>

Bits 28:30 - Delay line for second microphone of pair 4

pub fn dlym4l(&mut self) -> DLYM4L_W<'_>

Bits 24:26 - Delay line for first microphone of pair 4

pub fn dlym3r(&mut self) -> DLYM3R_W<'_>

Bits 20:22 - Delay line for second microphone of pair 3

pub fn dlym3l(&mut self) -> DLYM3L_W<'_>

Bits 16:18 - Delay line for first microphone of pair 3

pub fn dlym2r(&mut self) -> DLYM2R_W<'_>

Bits 12:14 - Delay line for second microphone of pair 2

pub fn dlym2l(&mut self) -> DLYM2L_W<'_>

Bits 8:10 - Delay line for first microphone of pair 2

pub fn dlym1r(&mut self) -> DLYM1R_W<'_>

Bits 4:6 - Delay line for second microphone of pair 1

pub fn dlym1l(&mut self) -> DLYM1L_W<'_>

Bits 0:2 - Delay line for first microphone of pair 1

impl W<u32, Reg<u32, _CR1>>

pub fn uifremap(&mut self) -> UIFREMAP_W<'_>

Bit 11 - UIF status bit remapping

pub fn ckd(&mut self) -> CKD_W<'_>

Bits 8:9 - Clock division

pub fn arpe(&mut self) -> ARPE_W<'_>

Bit 7 - Auto-reload preload enable

pub fn cms(&mut self) -> CMS_W<'_>

Bits 5:6 - Center-aligned mode selection

pub fn dir(&mut self) -> DIR_W<'_>

Bit 4 - Direction

pub fn opm(&mut self) -> OPM_W<'_>

Bit 3 - One-pulse mode

pub fn urs(&mut self) -> URS_W<'_>

Bit 2 - Update request source

pub fn udis(&mut self) -> UDIS_W<'_>

Bit 1 - Update disable

pub fn cen(&mut self) -> CEN_W<'_>

Bit 0 - Counter enable

impl W<u32, Reg<u32, _CR2>>

pub fn ti1s(&mut self) -> TI1S_W<'_>

Bit 7 - TI1 selection

pub fn mms(&mut self) -> MMS_W<'_>

Bits 4:6 - Master mode selection

pub fn ccds(&mut self) -> CCDS_W<'_>

Bit 3 - Capture/compare DMA selection

impl W<u32, Reg<u32, _SMCR>>

pub fn sms_3(&mut self) -> SMS_3_W<'_>

Bit 16 - Slave mode selection - bit 3

pub fn etp(&mut self) -> ETP_W<'_>

Bit 15 - External trigger polarity

pub fn ece(&mut self) -> ECE_W<'_>

Bit 14 - External clock enable

pub fn etps(&mut self) -> ETPS_W<'_>

Bits 12:13 - External trigger prescaler

pub fn etf(&mut self) -> ETF_W<'_>

Bits 8:11 - External trigger filter

pub fn msm(&mut self) -> MSM_W<'_>

Bit 7 - Master/Slave mode

pub fn ts(&mut self) -> TS_W<'_>

Bits 4:6 - Trigger selection

pub fn occs(&mut self) -> OCCS_W<'_>

Bit 3 - OCREF clear selection

pub fn sms(&mut self) -> SMS_W<'_>

Bits 0:2 - Slave mode selection

impl W<u32, Reg<u32, _DIER>>

pub fn cc4de(&mut self) -> CC4DE_W<'_>

Bit 12 - Capture/Compare 4 DMA request enable

pub fn cc3de(&mut self) -> CC3DE_W<'_>

Bit 11 - Capture/Compare 3 DMA request enable

pub fn cc2de(&mut self) -> CC2DE_W<'_>

Bit 10 - Capture/Compare 2 DMA request enable

pub fn cc1de(&mut self) -> CC1DE_W<'_>

Bit 9 - Capture/Compare 1 DMA request enable

pub fn ude(&mut self) -> UDE_W<'_>

Bit 8 - Update DMA request enable

pub fn tie(&mut self) -> TIE_W<'_>

Bit 6 - Trigger interrupt enable

pub fn cc4ie(&mut self) -> CC4IE_W<'_>

Bit 4 - Capture/Compare 4 interrupt enable

pub fn cc3ie(&mut self) -> CC3IE_W<'_>

Bit 3 - Capture/Compare 3 interrupt enable

pub fn cc2ie(&mut self) -> CC2IE_W<'_>

Bit 2 - Capture/Compare 2 interrupt enable

pub fn cc1ie(&mut self) -> CC1IE_W<'_>

Bit 1 - Capture/Compare 1 interrupt enable

pub fn uie(&mut self) -> UIE_W<'_>

Bit 0 - Update interrupt enable

impl W<u32, Reg<u32, _SR>>

pub fn cc4of(&mut self) -> CC4OF_W<'_>

Bit 12 - Capture/Compare 4 overcapture flag

pub fn cc3of(&mut self) -> CC3OF_W<'_>

Bit 11 - Capture/Compare 3 overcapture flag

pub fn cc2of(&mut self) -> CC2OF_W<'_>

Bit 10 - Capture/compare 2 overcapture flag

pub fn cc1of(&mut self) -> CC1OF_W<'_>

Bit 9 - Capture/Compare 1 overcapture flag

pub fn tif(&mut self) -> TIF_W<'_>

Bit 6 - Trigger interrupt flag

pub fn cc4if(&mut self) -> CC4IF_W<'_>

Bit 4 - Capture/Compare 4 interrupt flag

pub fn cc3if(&mut self) -> CC3IF_W<'_>

Bit 3 - Capture/Compare 3 interrupt flag

pub fn cc2if(&mut self) -> CC2IF_W<'_>

Bit 2 - Capture/Compare 2 interrupt flag

pub fn cc1if(&mut self) -> CC1IF_W<'_>

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&mut self) -> UIF_W<'_>

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>

pub fn tg(&mut self) -> TG_W<'_>

Bit 6 - Trigger generation

pub fn cc4g(&mut self) -> CC4G_W<'_>

Bit 4 - Capture/compare 4 generation

pub fn cc3g(&mut self) -> CC3G_W<'_>

Bit 3 - Capture/compare 3 generation

pub fn cc2g(&mut self) -> CC2G_W<'_>

Bit 2 - Capture/compare 2 generation

pub fn cc1g(&mut self) -> CC1G_W<'_>

Bit 1 - Capture/compare 1 generation

pub fn ug(&mut self) -> UG_W<'_>

Bit 0 - Update generation

impl W<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn oc2m_3(&mut self) -> OC2M_3_W<'_>

Bit 24 - Output Compare 2 mode - bit 3

pub fn oc1m_3(&mut self) -> OC1M_3_W<'_>

Bit 16 - Output Compare 1 mode - bit 3

pub fn oc2ce(&mut self) -> OC2CE_W<'_>

Bit 15 - Output compare 2 clear enable

pub fn oc2m(&mut self) -> OC2M_W<'_>

Bits 12:14 - Output compare 2 mode

pub fn oc2pe(&mut self) -> OC2PE_W<'_>

Bit 11 - Output compare 2 preload enable

pub fn oc2fe(&mut self) -> OC2FE_W<'_>

Bit 10 - Output compare 2 fast enable

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/Compare 2 selection

pub fn oc1ce(&mut self) -> OC1CE_W<'_>

Bit 7 - Output compare 1 clear enable

pub fn oc1m(&mut self) -> OC1M_W<'_>

Bits 4:6 - Output compare 1 mode

pub fn oc1pe(&mut self) -> OC1PE_W<'_>

Bit 3 - Output compare 1 preload enable

pub fn oc1fe(&mut self) -> OC1FE_W<'_>

Bit 2 - Output compare 1 fast enable

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR1_INPUT>>

pub fn ic2f(&mut self) -> IC2F_W<'_>

Bits 12:15 - Input capture 2 filter

pub fn ic2psc(&mut self) -> IC2PSC_W<'_>

Bits 10:11 - Input capture 2 prescaler

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/compare 2 selection

pub fn ic1f(&mut self) -> IC1F_W<'_>

Bits 4:7 - Input capture 1 filter

pub fn ic1psc(&mut self) -> IC1PSC_W<'_>

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR2_OUTPUT>>

pub fn oc4m_3(&mut self) -> OC4M_3_W<'_>

Bit 24 - Output Compare 4 mode - bit 3

pub fn oc3m_3(&mut self) -> OC3M_3_W<'_>

Bit 16 - Output Compare 3 mode - bit 3

pub fn oc4ce(&mut self) -> OC4CE_W<'_>

Bit 15 - Output compare 4 clear enable

pub fn oc4m(&mut self) -> OC4M_W<'_>

Bits 12:14 - Output compare 4 mode

pub fn oc4pe(&mut self) -> OC4PE_W<'_>

Bit 11 - Output compare 4 preload enable

pub fn oc4fe(&mut self) -> OC4FE_W<'_>

Bit 10 - Output compare 4 fast enable

pub fn cc4s(&mut self) -> CC4S_W<'_>

Bits 8:9 - Capture/Compare 4 selection

pub fn oc3ce(&mut self) -> OC3CE_W<'_>

Bit 7 - Output compare 3 clear enable

pub fn oc3m(&mut self) -> OC3M_W<'_>

Bits 4:6 - Output compare 3 mode

pub fn oc3pe(&mut self) -> OC3PE_W<'_>

Bit 3 - Output compare 3 preload enable

pub fn oc3fe(&mut self) -> OC3FE_W<'_>

Bit 2 - Output compare 3 fast enable

pub fn cc3s(&mut self) -> CC3S_W<'_>

Bits 0:1 - Capture/Compare 3 selection

impl W<u32, Reg<u32, _CCMR2_INPUT>>

pub fn ic4f(&mut self) -> IC4F_W<'_>

Bits 12:15 - Input capture 4 filter

pub fn ic4psc(&mut self) -> IC4PSC_W<'_>

Bits 10:11 - Input capture 4 prescaler

pub fn cc4s(&mut self) -> CC4S_W<'_>

Bits 8:9 - Capture/Compare 4 selection

pub fn ic3f(&mut self) -> IC3F_W<'_>

Bits 4:7 - Input capture 3 filter

pub fn ic3psc(&mut self) -> IC3PSC_W<'_>

Bits 2:3 - Input capture 3 prescaler

pub fn cc3s(&mut self) -> CC3S_W<'_>

Bits 0:1 - Capture/Compare 3 selection

impl W<u32, Reg<u32, _CCER>>

pub fn cc4np(&mut self) -> CC4NP_W<'_>

Bit 15 - Capture/Compare 4 output Polarity

pub fn cc4p(&mut self) -> CC4P_W<'_>

Bit 13 - Capture/Compare 3 output Polarity

pub fn cc4e(&mut self) -> CC4E_W<'_>

Bit 12 - Capture/Compare 4 output enable

pub fn cc3np(&mut self) -> CC3NP_W<'_>

Bit 11 - Capture/Compare 3 output Polarity

pub fn cc3p(&mut self) -> CC3P_W<'_>

Bit 9 - Capture/Compare 3 output Polarity

pub fn cc3e(&mut self) -> CC3E_W<'_>

Bit 8 - Capture/Compare 3 output enable

pub fn cc2np(&mut self) -> CC2NP_W<'_>

Bit 7 - Capture/Compare 2 output Polarity

pub fn cc2p(&mut self) -> CC2P_W<'_>

Bit 5 - Capture/Compare 2 output Polarity

pub fn cc2e(&mut self) -> CC2E_W<'_>

Bit 4 - Capture/Compare 2 output enable

pub fn cc1np(&mut self) -> CC1NP_W<'_>

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc1p(&mut self) -> CC1P_W<'_>

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1e(&mut self) -> CC1E_W<'_>

Bit 0 - Capture/Compare 1 output enable

impl W<u32, Reg<u32, _CNT>>

pub fn cnt_h(&mut self) -> CNT_H_W<'_>

Bits 16:30 - High counter value (TIM2 only)

pub fn cnt_l(&mut self) -> CNT_L_W<'_>

Bits 0:15 - Low counter value

impl W<u32, Reg<u32, _PSC>>

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>

pub fn arr_h(&mut self) -> ARR_H_W<'_>

Bits 16:31 - High Auto-reload value (TIM2 only)

pub fn arr_l(&mut self) -> ARR_L_W<'_>

Bits 0:15 - Low Auto-reload value

impl W<u32, Reg<u32, _CCR1>>

pub fn ccr1_h(&mut self) -> CCR1_H_W<'_>

Bits 16:31 - High Capture/Compare 1 value (TIM2 only)

pub fn ccr1_l(&mut self) -> CCR1_L_W<'_>

Bits 0:15 - Low Capture/Compare 1 value

impl W<u32, Reg<u32, _CCR2>>

pub fn ccr2_h(&mut self) -> CCR2_H_W<'_>

Bits 16:31 - High Capture/Compare 2 value (TIM2 only)

pub fn ccr2_l(&mut self) -> CCR2_L_W<'_>

Bits 0:15 - Low Capture/Compare 2 value

impl W<u32, Reg<u32, _CCR3>>

pub fn ccr3_h(&mut self) -> CCR3_H_W<'_>

Bits 16:31 - High Capture/Compare value (TIM2 only)

pub fn ccr3_l(&mut self) -> CCR3_L_W<'_>

Bits 0:15 - Low Capture/Compare value

impl W<u32, Reg<u32, _CCR4>>

pub fn ccr4_h(&mut self) -> CCR4_H_W<'_>

Bits 16:31 - High Capture/Compare value (TIM2 only)

pub fn ccr4_l(&mut self) -> CCR4_L_W<'_>

Bits 0:15 - Low Capture/Compare value

impl W<u32, Reg<u32, _DCR>>

pub fn dbl(&mut self) -> DBL_W<'_>

Bits 8:12 - DMA burst length

pub fn dba(&mut self) -> DBA_W<'_>

Bits 0:4 - DMA base address

impl W<u32, Reg<u32, _DMAR>>

pub fn dmab(&mut self) -> DMAB_W<'_>

Bits 0:15 - DMA register for burst accesses

impl W<u32, Reg<u32, _OR>>

pub fn ti4_rmp(&mut self) -> TI4_RMP_W<'_>

Bits 2:3 - Input capture 4 remap

pub fn etr_rmp(&mut self) -> ETR_RMP_W<'_>

Bit 1 - External trigger remap

pub fn itr_rmp(&mut self) -> ITR_RMP_W<'_>

Bit 0 - Internal trigger remap

impl W<u32, Reg<u32, _AF>>

pub fn etrsel(&mut self) -> ETRSEL_W<'_>

Bits 14:16 - External trigger source selection

impl W<u32, Reg<u32, _CR1>>

pub fn bkine(&mut self) -> BKINE_W<'_>

Bit 0 - BRK BKIN input enable

pub fn bkcmp1e(&mut self) -> BKCMP1E_W<'_>

Bit 1 - BRK COMP1 enable

pub fn bkcmp2e(&mut self) -> BKCMP2E_W<'_>

Bit 2 - BRK COMP2 enable

pub fn bkinp(&mut self) -> BKINP_W<'_>

Bit 9 - BRK BKIN input polarity

pub fn bkcmp1p(&mut self) -> BKCMP1P_W<'_>

Bit 10 - BRK COMP1 input polarity

pub fn bkcmp2p(&mut self) -> BKCMP2P_W<'_>

Bit 11 - BRK COMP2 input polarit

impl W<u32, Reg<u32, _CR2>>

pub fn ois1n(&mut self) -> OIS1N_W<'_>

Bit 9 - Output Idle state 1

pub fn ois1(&mut self) -> OIS1_W<'_>

Bit 8 - Output Idle state 1

pub fn ccds(&mut self) -> CCDS_W<'_>

Bit 3 - Capture/compare DMA selection

pub fn ccus(&mut self) -> CCUS_W<'_>

Bit 2 - Capture/compare control update selection

pub fn ccpc(&mut self) -> CCPC_W<'_>

Bit 0 - Capture/compare preloaded control

impl W<u32, Reg<u32, _DIER>>

pub fn bkine(&mut self) -> BKINE_W<'_>

Bit 0 - BRK BKIN input enable

pub fn bkcmp1e(&mut self) -> BKCMP1E_W<'_>

Bit 1 - BRK COMP1 enable

pub fn bkcmp2e(&mut self) -> BKCMP2E_W<'_>

Bit 2 - BRK COMP2 enable

pub fn bkinp(&mut self) -> BKINP_W<'_>

Bit 9 - BRK BKIN input polarity

pub fn bkcmp1p(&mut self) -> BKCMP1P_W<'_>

Bit 10 - BRK COMP1 input polarity

pub fn bkcmp2p(&mut self) -> BKCMP2P_W<'_>

Bit 11 - BRK COMP2 input polarit

impl W<u32, Reg<u32, _SR>>

pub fn cc1of(&mut self) -> CC1OF_W<'_>

Bit 9 - Capture/Compare 1 overcapture flag

pub fn bif(&mut self) -> BIF_W<'_>

Bit 7 - Break interrupt flag

pub fn tif(&mut self) -> TIF_W<'_>

Bit 6 - Trigger interrupt flag

pub fn comif(&mut self) -> COMIF_W<'_>

Bit 5 - COM interrupt flag

pub fn cc1if(&mut self) -> CC1IF_W<'_>

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&mut self) -> UIF_W<'_>

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>

pub fn bg(&mut self) -> BG_W<'_>

Bit 7 - Break generation

pub fn tg(&mut self) -> TG_W<'_>

Bit 6 - Trigger generation

pub fn comg(&mut self) -> COMG_W<'_>

Bit 5 - Capture/Compare control update generation

pub fn cc1g(&mut self) -> CC1G_W<'_>

Bit 1 - Capture/compare 1 generation

pub fn ug(&mut self) -> UG_W<'_>

Bit 0 - Update generation

impl W<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn oc1m_2(&mut self) -> OC1M_2_W<'_>

Bit 16 - Output Compare 1 mode

pub fn oc1m(&mut self) -> OC1M_W<'_>

Bits 4:6 - Output Compare 1 mode

pub fn oc1pe(&mut self) -> OC1PE_W<'_>

Bit 3 - Output Compare 1 preload enable

pub fn oc1fe(&mut self) -> OC1FE_W<'_>

Bit 2 - Output Compare 1 fast enable

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR1_INPUT>>

pub fn ic1f(&mut self) -> IC1F_W<'_>

Bits 4:7 - Input capture 1 filter

pub fn ic1psc(&mut self) -> IC1PSC_W<'_>

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCER>>

pub fn cc1np(&mut self) -> CC1NP_W<'_>

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc1ne(&mut self) -> CC1NE_W<'_>

Bit 2 - Capture/Compare 1 complementary output enable

pub fn cc1p(&mut self) -> CC1P_W<'_>

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1e(&mut self) -> CC1E_W<'_>

Bit 0 - Capture/Compare 1 output enable

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:15 - counter value

impl W<u32, Reg<u32, _PSC>>

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>

pub fn arr(&mut self) -> ARR_W<'_>

Bits 0:15 - Auto-reload value

impl W<u32, Reg<u32, _RCR>>

pub fn rep(&mut self) -> REP_W<'_>

Bits 0:7 - Repetition counter value

impl W<u32, Reg<u32, _CCR1>>

pub fn ccr1(&mut self) -> CCR1_W<'_>

Bits 0:15 - Capture/Compare 1 value

impl W<u32, Reg<u32, _BDTR>>

pub fn dtg(&mut self) -> DTG_W<'_>

Bits 0:7 - Dead-time generator setup

pub fn lock(&mut self) -> LOCK_W<'_>

Bits 8:9 - Lock configuration

pub fn ossi(&mut self) -> OSSI_W<'_>

Bit 10 - Off-state selection for Idle mode

pub fn ossr(&mut self) -> OSSR_W<'_>

Bit 11 - Off-state selection for Run mode

pub fn bke(&mut self) -> BKE_W<'_>

Bit 12 - Break enable

pub fn bkp(&mut self) -> BKP_W<'_>

Bit 13 - Break polarity

pub fn aoe(&mut self) -> AOE_W<'_>

Bit 14 - Automatic output enable

pub fn moe(&mut self) -> MOE_W<'_>

Bit 15 - Main output enable

pub fn bkf(&mut self) -> BKF_W<'_>

Bits 16:19 - Break filter

impl W<u32, Reg<u32, _DCR>>

pub fn dbl(&mut self) -> DBL_W<'_>

Bits 8:12 - DMA burst length

pub fn dba(&mut self) -> DBA_W<'_>

Bits 0:4 - DMA base address

impl W<u32, Reg<u32, _DMAR>>

pub fn dmab(&mut self) -> DMAB_W<'_>

Bits 0:15 - DMA register for burst accesses

impl W<u32, Reg<u32, _OR>>

pub fn ti1_rmp(&mut self) -> TI1_RMP_W<'_>

Bits 0:1 - Input capture 1 remap

impl W<u32, Reg<u32, _AF1>>

pub fn bkine(&mut self) -> BKINE_W<'_>

Bit 0 - BRK BKIN input enable

pub fn bkcmp1e(&mut self) -> BKCMP1E_W<'_>

Bit 1 - BRK COMP1 enable

pub fn bkcmp2e(&mut self) -> BKCMP2E_W<'_>

Bit 2 - BRK COMP2 enable

pub fn bkinp(&mut self) -> BKINP_W<'_>

Bit 9 - BRK BKIN input polarity

pub fn bkcmp1p(&mut self) -> BKCMP1P_W<'_>

Bit 10 - BRK COMP1 input polarity

pub fn bkcmp2p(&mut self) -> BKCMP2P_W<'_>

Bit 11 - BRK COMP2 input polarit

impl W<u32, Reg<u32, _CR1>>

pub fn cen(&mut self) -> CEN_W<'_>

Bit 0 - Counter enable

pub fn udis(&mut self) -> UDIS_W<'_>

Bit 1 - Update disable

pub fn urs(&mut self) -> URS_W<'_>

Bit 2 - Update request source

pub fn opm(&mut self) -> OPM_W<'_>

Bit 3 - One-pulse mode

pub fn arpe(&mut self) -> ARPE_W<'_>

Bit 7 - Auto-reload preload enable

pub fn ckd(&mut self) -> CKD_W<'_>

Bits 8:9 - Clock division

pub fn uifremap(&mut self) -> UIFREMAP_W<'_>

Bit 11 - UIF status bit remapping

impl W<u32, Reg<u32, _CR2>>

pub fn ois1n(&mut self) -> OIS1N_W<'_>

Bit 9 - Output Idle state 1

pub fn ois1(&mut self) -> OIS1_W<'_>

Bit 8 - Output Idle state 1

pub fn ccds(&mut self) -> CCDS_W<'_>

Bit 3 - Capture/compare DMA selection

pub fn ccus(&mut self) -> CCUS_W<'_>

Bit 2 - Capture/compare control update selection

pub fn ccpc(&mut self) -> CCPC_W<'_>

Bit 0 - Capture/compare preloaded control

impl W<u32, Reg<u32, _DIER>>

pub fn bkine(&mut self) -> BKINE_W<'_>

Bit 0 - BRK BKIN input enable

pub fn bkcmp1e(&mut self) -> BKCMP1E_W<'_>

Bit 1 - BRK COMP1 enable

pub fn bkcmp2e(&mut self) -> BKCMP2E_W<'_>

Bit 2 - BRK COMP2 enable

pub fn bkinp(&mut self) -> BKINP_W<'_>

Bit 9 - BRK BKIN input polarity

pub fn bkcmp1p(&mut self) -> BKCMP1P_W<'_>

Bit 10 - BRK COMP1 input polarity

pub fn bkcmp2p(&mut self) -> BKCMP2P_W<'_>

Bit 11 - BRK COMP2 input polarit

impl W<u32, Reg<u32, _SR>>

pub fn cc1of(&mut self) -> CC1OF_W<'_>

Bit 9 - Capture/Compare 1 overcapture flag

pub fn bif(&mut self) -> BIF_W<'_>

Bit 7 - Break interrupt flag

pub fn tif(&mut self) -> TIF_W<'_>

Bit 6 - Trigger interrupt flag

pub fn comif(&mut self) -> COMIF_W<'_>

Bit 5 - COM interrupt flag

pub fn cc1if(&mut self) -> CC1IF_W<'_>

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&mut self) -> UIF_W<'_>

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>

pub fn bg(&mut self) -> BG_W<'_>

Bit 7 - Break generation

pub fn tg(&mut self) -> TG_W<'_>

Bit 6 - Trigger generation

pub fn comg(&mut self) -> COMG_W<'_>

Bit 5 - Capture/Compare control update generation

pub fn cc1g(&mut self) -> CC1G_W<'_>

Bit 1 - Capture/compare 1 generation

pub fn ug(&mut self) -> UG_W<'_>

Bit 0 - Update generation

impl W<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn oc1m_2(&mut self) -> OC1M_2_W<'_>

Bit 16 - Output Compare 1 mode

pub fn oc1m(&mut self) -> OC1M_W<'_>

Bits 4:6 - Output Compare 1 mode

pub fn oc1pe(&mut self) -> OC1PE_W<'_>

Bit 3 - Output Compare 1 preload enable

pub fn oc1fe(&mut self) -> OC1FE_W<'_>

Bit 2 - Output Compare 1 fast enable

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR1_INPUT>>

pub fn ic1f(&mut self) -> IC1F_W<'_>

Bits 4:7 - Input capture 1 filter

pub fn ic1psc(&mut self) -> IC1PSC_W<'_>

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCER>>

pub fn cc1np(&mut self) -> CC1NP_W<'_>

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc1ne(&mut self) -> CC1NE_W<'_>

Bit 2 - Capture/Compare 1 complementary output enable

pub fn cc1p(&mut self) -> CC1P_W<'_>

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1e(&mut self) -> CC1E_W<'_>

Bit 0 - Capture/Compare 1 output enable

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:15 - counter value

impl W<u32, Reg<u32, _PSC>>

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>

pub fn arr(&mut self) -> ARR_W<'_>

Bits 0:15 - Auto-reload value

impl W<u32, Reg<u32, _RCR>>

pub fn rep(&mut self) -> REP_W<'_>

Bits 0:7 - Repetition counter value

impl W<u32, Reg<u32, _CCR1>>

pub fn ccr1(&mut self) -> CCR1_W<'_>

Bits 0:15 - Capture/Compare 1 value

impl W<u32, Reg<u32, _BDTR>>

pub fn dtg(&mut self) -> DTG_W<'_>

Bits 0:7 - Dead-time generator setup

pub fn lock(&mut self) -> LOCK_W<'_>

Bits 8:9 - Lock configuration

pub fn ossi(&mut self) -> OSSI_W<'_>

Bit 10 - Off-state selection for Idle mode

pub fn ossr(&mut self) -> OSSR_W<'_>

Bit 11 - Off-state selection for Run mode

pub fn bke(&mut self) -> BKE_W<'_>

Bit 12 - Break enable

pub fn bkp(&mut self) -> BKP_W<'_>

Bit 13 - Break polarity

pub fn aoe(&mut self) -> AOE_W<'_>

Bit 14 - Automatic output enable

pub fn moe(&mut self) -> MOE_W<'_>

Bit 15 - Main output enable

pub fn bkf(&mut self) -> BKF_W<'_>

Bits 16:19 - Break filter

impl W<u32, Reg<u32, _DCR>>

pub fn dbl(&mut self) -> DBL_W<'_>

Bits 8:12 - DMA burst length

pub fn dba(&mut self) -> DBA_W<'_>

Bits 0:4 - DMA base address

impl W<u32, Reg<u32, _DMAR>>

pub fn dmab(&mut self) -> DMAB_W<'_>

Bits 0:15 - DMA register for burst accesses

impl W<u32, Reg<u32, _OR>>

pub fn ti1_rmp(&mut self) -> TI1_RMP_W<'_>

Bits 0:1 - Input capture 1 remap

impl W<u32, Reg<u32, _AF1>>

pub fn bkine(&mut self) -> BKINE_W<'_>

Bit 0 - BRK BKIN input enable

pub fn bkcmp1e(&mut self) -> BKCMP1E_W<'_>

Bit 1 - BRK COMP1 enable

pub fn bkcmp2e(&mut self) -> BKCMP2E_W<'_>

Bit 2 - BRK COMP2 enable

pub fn bkinp(&mut self) -> BKINP_W<'_>

Bit 9 - BRK BKIN input polarity

pub fn bkcmp1p(&mut self) -> BKCMP1P_W<'_>

Bit 10 - BRK COMP1 input polarity

pub fn bkcmp2p(&mut self) -> BKCMP2P_W<'_>

Bit 11 - BRK COMP2 input polarit

impl W<u32, Reg<u32, _CR1>>

pub fn cen(&mut self) -> CEN_W<'_>

Bit 0 - Counter enable

pub fn opm(&mut self) -> OPM_W<'_>

Bit 3 - One-pulse mode

pub fn udis(&mut self) -> UDIS_W<'_>

Bit 1 - Update disable

pub fn urs(&mut self) -> URS_W<'_>

Bit 2 - Update request source

pub fn dir(&mut self) -> DIR_W<'_>

Bit 4 - Direction

pub fn cms(&mut self) -> CMS_W<'_>

Bits 5:6 - Center-aligned mode selection

pub fn arpe(&mut self) -> ARPE_W<'_>

Bit 7 - Auto-reload preload enable

pub fn ckd(&mut self) -> CKD_W<'_>

Bits 8:9 - Clock division

pub fn uifremap(&mut self) -> UIFREMAP_W<'_>

Bit 11 - UIF status bit remapping

impl W<u32, Reg<u32, _CR2>>

pub fn mms2(&mut self) -> MMS2_W<'_>

Bits 20:23 - Master mode selection 2

pub fn ois6(&mut self) -> OIS6_W<'_>

Bit 18 - Output Idle state 6 (OC6 output)

pub fn ois5(&mut self) -> OIS5_W<'_>

Bit 16 - Output Idle state 5 (OC5 output)

pub fn ois4(&mut self) -> OIS4_W<'_>

Bit 14 - Output Idle state 4

pub fn ois3n(&mut self) -> OIS3N_W<'_>

Bit 13 - Output Idle state 3

pub fn ois3(&mut self) -> OIS3_W<'_>

Bit 12 - Output Idle state 3

pub fn ois2n(&mut self) -> OIS2N_W<'_>

Bit 11 - Output Idle state 2

pub fn ois2(&mut self) -> OIS2_W<'_>

Bit 10 - Output Idle state 2

pub fn ois1n(&mut self) -> OIS1N_W<'_>

Bit 9 - Output Idle state 1

pub fn ois1(&mut self) -> OIS1_W<'_>

Bit 8 - Output Idle state 1

pub fn ti1s(&mut self) -> TI1S_W<'_>

Bit 7 - TI1 selection

pub fn mms(&mut self) -> MMS_W<'_>

Bits 4:6 - Master mode selection

pub fn ccds(&mut self) -> CCDS_W<'_>

Bit 3 - Capture/compare DMA selection

pub fn ccus(&mut self) -> CCUS_W<'_>

Bit 2 - Capture/compare control update selection

pub fn ccpc(&mut self) -> CCPC_W<'_>

Bit 0 - Capture/compare preloaded control

impl W<u32, Reg<u32, _SMCR>>

pub fn sms(&mut self) -> SMS_W<'_>

Bits 0:2 - Slave mode selection

pub fn occs(&mut self) -> OCCS_W<'_>

Bit 3 - OCREF clear selection

pub fn ts(&mut self) -> TS_W<'_>

Bits 4:6 - Trigger selection

pub fn msm(&mut self) -> MSM_W<'_>

Bit 7 - Master/Slave mode

pub fn etf(&mut self) -> ETF_W<'_>

Bits 8:11 - External trigger filter

pub fn etps(&mut self) -> ETPS_W<'_>

Bits 12:13 - External trigger prescaler

pub fn ece(&mut self) -> ECE_W<'_>

Bit 14 - External clock enable

pub fn etp(&mut self) -> ETP_W<'_>

Bit 15 - External trigger polarity

pub fn sms_3(&mut self) -> SMS_3_W<'_>

Bit 16 - Slave mode selection - bit 3

impl W<u32, Reg<u32, _DIER>>

pub fn uie(&mut self) -> UIE_W<'_>

Bit 0 - Update interrupt enable

pub fn cc1ie(&mut self) -> CC1IE_W<'_>

Bit 1 - Capture/Compare 1 interrupt enable

pub fn cc2ie(&mut self) -> CC2IE_W<'_>

Bit 2 - Capture/Compare 2 interrupt enable

pub fn cc3ie(&mut self) -> CC3IE_W<'_>

Bit 3 - Capture/Compare 3 interrupt enable

pub fn cc4ie(&mut self) -> CC4IE_W<'_>

Bit 4 - Capture/Compare 4 interrupt enable

pub fn comie(&mut self) -> COMIE_W<'_>

Bit 5 - COM interrupt enable

pub fn tie(&mut self) -> TIE_W<'_>

Bit 6 - Trigger interrupt enable

pub fn bie(&mut self) -> BIE_W<'_>

Bit 7 - Break interrupt enable

pub fn ude(&mut self) -> UDE_W<'_>

Bit 8 - Update DMA request enable

pub fn cc1de(&mut self) -> CC1DE_W<'_>

Bit 9 - Capture/Compare 1 DMA request enable

pub fn cc2de(&mut self) -> CC2DE_W<'_>

Bit 10 - Capture/Compare 2 DMA request enable

pub fn cc3de(&mut self) -> CC3DE_W<'_>

Bit 11 - Capture/Compare 3 DMA request enable

pub fn cc4de(&mut self) -> CC4DE_W<'_>

Bit 12 - Capture/Compare 4 DMA request enable

pub fn comde(&mut self) -> COMDE_W<'_>

Bit 13 - COM DMA request enable

pub fn tde(&mut self) -> TDE_W<'_>

Bit 14 - Trigger DMA request enable

impl W<u32, Reg<u32, _SR>>

pub fn uif(&mut self) -> UIF_W<'_>

Bit 0 - Update interrupt flag

pub fn cc1if(&mut self) -> CC1IF_W<'_>

Bit 1 - Capture/compare 1 interrupt flag

pub fn cc2if(&mut self) -> CC2IF_W<'_>

Bit 2 - Capture/Compare 2 interrupt flag

pub fn cc3if(&mut self) -> CC3IF_W<'_>

Bit 3 - Capture/Compare 3 interrupt flag

pub fn cc4if(&mut self) -> CC4IF_W<'_>

Bit 4 - Capture/Compare 4 interrupt flag

pub fn comif(&mut self) -> COMIF_W<'_>

Bit 5 - COM interrupt flag

pub fn tif(&mut self) -> TIF_W<'_>

Bit 6 - Trigger interrupt flag

pub fn bif(&mut self) -> BIF_W<'_>

Bit 7 - Break interrupt flag

pub fn b2if(&mut self) -> B2IF_W<'_>

Bit 8 - Break 2 interrupt flag

pub fn cc1of(&mut self) -> CC1OF_W<'_>

Bit 9 - Capture/Compare 1 overcapture flag

pub fn cc2of(&mut self) -> CC2OF_W<'_>

Bit 10 - Capture/compare 2 overcapture flag

pub fn cc3of(&mut self) -> CC3OF_W<'_>

Bit 11 - Capture/Compare 3 overcapture flag

pub fn cc4of(&mut self) -> CC4OF_W<'_>

Bit 12 - Capture/Compare 4 overcapture flag

pub fn sbif(&mut self) -> SBIF_W<'_>

Bit 13 - System Break interrupt flag

pub fn cc5if(&mut self) -> CC5IF_W<'_>

Bit 16 - Compare 5 interrupt flag

pub fn cc6if(&mut self) -> CC6IF_W<'_>

Bit 17 - Compare 6 interrupt flag

impl W<u32, Reg<u32, _EGR>>

pub fn ug(&mut self) -> UG_W<'_>

Bit 0 - Update generation

pub fn cc1g(&mut self) -> CC1G_W<'_>

Bit 1 - Capture/compare 1 generation

pub fn cc2g(&mut self) -> CC2G_W<'_>

Bit 2 - Capture/compare 2 generation

pub fn cc3g(&mut self) -> CC3G_W<'_>

Bit 3 - Capture/compare 3 generation

pub fn cc4g(&mut self) -> CC4G_W<'_>

Bit 4 - Capture/compare 4 generation

pub fn comg(&mut self) -> COMG_W<'_>

Bit 5 - Capture/Compare control update generation

pub fn tg(&mut self) -> TG_W<'_>

Bit 6 - Trigger generation

pub fn bg(&mut self) -> BG_W<'_>

Bit 7 - Break generation

pub fn b2g(&mut self) -> B2G_W<'_>

Bit 8 - Break 2 generation

impl W<u32, Reg<u32, _CCMR1_INPUT>>

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

pub fn ic1psc(&mut self) -> IC1PSC_W<'_>

Bits 2:3 - Input capture 1 prescaler

pub fn c1f(&mut self) -> C1F_W<'_>

Bits 4:7 - Input capture 1 filter

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - capture/Compare 2 selection

pub fn ic2psc(&mut self) -> IC2PSC_W<'_>

Bits 10:11 - Input capture 2 prescaler

pub fn ic2f(&mut self) -> IC2F_W<'_>

Bits 12:15 - Input capture 2 filter

impl W<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

pub fn oc1fe(&mut self) -> OC1FE_W<'_>

Bit 2 - Output Compare 1 fast enable

pub fn oc1pe(&mut self) -> OC1PE_W<'_>

Bit 3 - Output Compare 1 preload enable

pub fn oc1m(&mut self) -> OC1M_W<'_>

Bits 4:6 - Output Compare 1 mode

pub fn oc1ce(&mut self) -> OC1CE_W<'_>

Bit 7 - Output Compare 1 clear enable

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/Compare 2 selection

pub fn oc2fe(&mut self) -> OC2FE_W<'_>

Bit 10 - Output Compare 2 fast enable

pub fn oc2pe(&mut self) -> OC2PE_W<'_>

Bit 11 - Output Compare 2 preload enable

pub fn oc2m(&mut self) -> OC2M_W<'_>

Bits 12:14 - Output Compare 2 mode

pub fn oc2ce(&mut self) -> OC2CE_W<'_>

Bit 15 - Output Compare 2 clear enable

pub fn oc1m_3(&mut self) -> OC1M_3_W<'_>

Bit 16 - Output Compare 1 mode - bit 3

pub fn oc2m_3(&mut self) -> OC2M_3_W<'_>

Bit 24 - Output Compare 2 mode - bit 3

impl W<u32, Reg<u32, _CCMR2_OUTPUT>>

pub fn cc3s(&mut self) -> CC3S_W<'_>

Bits 0:1 - Capture/Compare 3 selection

pub fn oc3fe(&mut self) -> OC3FE_W<'_>

Bit 2 - Output compare 3 fast enable

pub fn oc3pe(&mut self) -> OC3PE_W<'_>

Bit 3 - Output compare 3 preload enable

pub fn oc3m(&mut self) -> OC3M_W<'_>

Bits 4:6 - Output compare 3 mode

pub fn oc3ce(&mut self) -> OC3CE_W<'_>

Bit 7 - Output compare 3 clear enable

pub fn cc4s(&mut self) -> CC4S_W<'_>

Bits 8:9 - Capture/Compare 4 selection

pub fn oc4fe(&mut self) -> OC4FE_W<'_>

Bit 10 - Output compare 4 fast enable

pub fn oc4pe(&mut self) -> OC4PE_W<'_>

Bit 11 - Output compare 4 preload enable

pub fn oc4m(&mut self) -> OC4M_W<'_>

Bits 12:14 - Output compare 4 mode

pub fn oc4ce(&mut self) -> OC4CE_W<'_>

Bit 15 - Output compare 4 clear enable

pub fn oc3m_3(&mut self) -> OC3M_3_W<'_>

Bit 16 - Output Compare 3 mode - bit 3

pub fn oc4m_3(&mut self) -> OC4M_3_W<'_>

Bit 24 - Output Compare 4 mode - bit 3

impl W<u32, Reg<u32, _CCMR2_INPUT>>

pub fn cc3s(&mut self) -> CC3S_W<'_>

Bits 0:1 - Capture/Compare 3 selection

pub fn c3psc(&mut self) -> C3PSC_W<'_>

Bits 2:3 - Input capture 3 prescaler

pub fn ic3f(&mut self) -> IC3F_W<'_>

Bits 4:7 - Input capture 3 filter

pub fn cc4s(&mut self) -> CC4S_W<'_>

Bits 8:9 - Capture/Compare 4 selection

pub fn ic4psc(&mut self) -> IC4PSC_W<'_>

Bits 10:11 - Input capture 4 prescaler

pub fn ic4f(&mut self) -> IC4F_W<'_>

Bits 12:15 - Input capture 4 filter

impl W<u32, Reg<u32, _CCER>>

pub fn cc1e(&mut self) -> CC1E_W<'_>

Bit 0 - Capture/Compare 1 output enable

pub fn cc1p(&mut self) -> CC1P_W<'_>

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1ne(&mut self) -> CC1NE_W<'_>

Bit 2 - Capture/Compare 1 complementary output enable

pub fn cc1np(&mut self) -> CC1NP_W<'_>

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc2e(&mut self) -> CC2E_W<'_>

Bit 4 - Capture/Compare 2 output enable

pub fn cc2p(&mut self) -> CC2P_W<'_>

Bit 5 - Capture/Compare 2 output Polarity

pub fn cc2ne(&mut self) -> CC2NE_W<'_>

Bit 6 - Capture/Compare 2 complementary output enable

pub fn cc2np(&mut self) -> CC2NP_W<'_>

Bit 7 - Capture/Compare 2 output Polarity

pub fn cc3e(&mut self) -> CC3E_W<'_>

Bit 8 - Capture/Compare 3 output enable

pub fn cc3p(&mut self) -> CC3P_W<'_>

Bit 9 - Capture/Compare 3 output Polarity

pub fn cc3ne(&mut self) -> CC3NE_W<'_>

Bit 10 - Capture/Compare 3 complementary output enable

pub fn cc3np(&mut self) -> CC3NP_W<'_>

Bit 11 - Capture/Compare 3 output Polarity

pub fn cc4e(&mut self) -> CC4E_W<'_>

Bit 12 - Capture/Compare 4 output enable

pub fn cc4p(&mut self) -> CC4P_W<'_>

Bit 13 - Capture/Compare 3 output Polarity

pub fn cc4np(&mut self) -> CC4NP_W<'_>

Bit 15 - Capture/Compare 4 complementary output polarity

pub fn cc5e(&mut self) -> CC5E_W<'_>

Bit 16 - Capture/Compare 5 output enable

pub fn cc5p(&mut self) -> CC5P_W<'_>

Bit 17 - Capture/Compare 5 output polarity

pub fn cc6e(&mut self) -> CC6E_W<'_>

Bit 20 - Capture/Compare 6 output enable

pub fn cc6p(&mut self) -> CC6P_W<'_>

Bit 21 - Capture/Compare 6 output polarity

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:15 - counter value

impl W<u32, Reg<u32, _PSC>>

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>

pub fn arr(&mut self) -> ARR_W<'_>

Bits 0:15 - Auto-reload value

impl W<u32, Reg<u32, _RCR>>

pub fn rep(&mut self) -> REP_W<'_>

Bits 0:15 - Repetition counter value

impl W<u32, Reg<u32, _CCR1>>

pub fn ccr1(&mut self) -> CCR1_W<'_>

Bits 0:15 - Capture/Compare 1 value

impl W<u32, Reg<u32, _CCR2>>

pub fn ccr2(&mut self) -> CCR2_W<'_>

Bits 0:15 - Capture/Compare 2 value

impl W<u32, Reg<u32, _CCR3>>

pub fn ccr3(&mut self) -> CCR3_W<'_>

Bits 0:15 - Capture/Compare value

impl W<u32, Reg<u32, _CCR4>>

pub fn ccr4(&mut self) -> CCR4_W<'_>

Bits 0:15 - Capture/Compare value

impl W<u32, Reg<u32, _BDTR>>

pub fn dtg(&mut self) -> DTG_W<'_>

Bits 0:7 - Dead-time generator setup

pub fn lock(&mut self) -> LOCK_W<'_>

Bits 8:9 - Lock configuration

pub fn ossi(&mut self) -> OSSI_W<'_>

Bit 10 - Off-state selection for Idle mode

pub fn ossr(&mut self) -> OSSR_W<'_>

Bit 11 - Off-state selection for Run mode

pub fn bke(&mut self) -> BKE_W<'_>

Bit 12 - Break enable

pub fn bkp(&mut self) -> BKP_W<'_>

Bit 13 - Break polarity

pub fn aoe(&mut self) -> AOE_W<'_>

Bit 14 - Automatic output enable

pub fn moe(&mut self) -> MOE_W<'_>

Bit 15 - Main output enable

pub fn bkf(&mut self) -> BKF_W<'_>

Bits 16:19 - Break filter

pub fn bk2f(&mut self) -> BK2F_W<'_>

Bits 20:23 - Break 2 filter

pub fn bk2e(&mut self) -> BK2E_W<'_>

Bit 24 - Break 2 enable

pub fn bk2p(&mut self) -> BK2P_W<'_>

Bit 25 - Break 2 polarity

impl W<u32, Reg<u32, _DCR>>

pub fn dbl(&mut self) -> DBL_W<'_>

Bits 8:12 - DMA burst length

pub fn dba(&mut self) -> DBA_W<'_>

Bits 0:4 - DMA base address

impl W<u32, Reg<u32, _DMAR>>

pub fn dmab(&mut self) -> DMAB_W<'_>

Bits 0:15 - DMA register for burst accesses

impl W<u32, Reg<u32, _OR>>

pub fn tim1_etr_adc1_rmp(&mut self) -> TIM1_ETR_ADC1_RMP_W<'_>

Bits 0:1 - TIM1_ETR_ADC1 remapping capability

pub fn ti1_rmp(&mut self) -> TI1_RMP_W<'_>

Bit 4 - Input Capture 1 remap

impl W<u32, Reg<u32, _CCMR3_OUTPUT>>

pub fn oc6m_bit3(&mut self) -> OC6M_BIT3_W<'_>

Bit 24 - Output Compare 6 mode bit 3

pub fn oc5m_bit3(&mut self) -> OC5M_BIT3_W<'_>

Bit 16 - Output Compare 5 mode bit 3

pub fn oc6ce(&mut self) -> OC6CE_W<'_>

Bit 15 - Output compare 6 clear enable

pub fn oc6m(&mut self) -> OC6M_W<'_>

Bits 12:14 - Output compare 6 mode

pub fn oc6pe(&mut self) -> OC6PE_W<'_>

Bit 11 - Output compare 6 preload enable

pub fn oc6fe(&mut self) -> OC6FE_W<'_>

Bit 10 - Output compare 6 fast enable

pub fn oc5ce(&mut self) -> OC5CE_W<'_>

Bit 7 - Output compare 5 clear enable

pub fn oc5m(&mut self) -> OC5M_W<'_>

Bits 4:6 - Output compare 5 mode

pub fn oc5pe(&mut self) -> OC5PE_W<'_>

Bit 3 - Output compare 5 preload enable

pub fn oc5fe(&mut self) -> OC5FE_W<'_>

Bit 2 - Output compare 5 fast enable

impl W<u32, Reg<u32, _CCR5>>

pub fn ccr5(&mut self) -> CCR5_W<'_>

Bits 0:15 - Capture/Compare value

pub fn gc5c1(&mut self) -> GC5C1_W<'_>

Bit 29 - Group Channel 5 and Channel 1

pub fn gc5c2(&mut self) -> GC5C2_W<'_>

Bit 30 - Group Channel 5 and Channel 2

pub fn gc5c3(&mut self) -> GC5C3_W<'_>

Bit 31 - Group Channel 5 and Channel 3

impl W<u32, Reg<u32, _CCR6>>

pub fn ccr6(&mut self) -> CCR6_W<'_>

Bits 0:15 - Capture/Compare value

impl W<u32, Reg<u32, _AF1>>

pub fn bkine(&mut self) -> BKINE_W<'_>

Bit 0 - BRK BKIN input enable

pub fn bkcmp1e(&mut self) -> BKCMP1E_W<'_>

Bit 1 - BRK COMP1 enable

pub fn bkcmp2e(&mut self) -> BKCMP2E_W<'_>

Bit 2 - BRK COMP2 enable

pub fn bkinp(&mut self) -> BKINP_W<'_>

Bit 9 - BRK BKIN input polarity

pub fn bkcmp1p(&mut self) -> BKCMP1P_W<'_>

Bit 10 - BRK COMP1 input polarity

pub fn bkcmp2p(&mut self) -> BKCMP2P_W<'_>

Bit 11 - BRK COMP2 input polarity

pub fn etrsel(&mut self) -> ETRSEL_W<'_>

Bits 14:16 - ETR source selection

impl W<u32, Reg<u32, _AF2>>

pub fn bk2ine(&mut self) -> BK2INE_W<'_>

Bit 0 - BRK2 BKIN input enable

pub fn bk2cmp1e(&mut self) -> BK2CMP1E_W<'_>

Bit 1 - BRK2 COMP1 enable

pub fn bk2cmp2e(&mut self) -> BK2CMP2E_W<'_>

Bit 2 - BRK2 COMP2 enable

pub fn bk2dfbk0e(&mut self) -> BK2DFBK0E_W<'_>

Bit 8 - BRK2 DFSDM_BREAK0 enable

pub fn bk2inp(&mut self) -> BK2INP_W<'_>

Bit 9 - BRK2 BKIN input polarity

pub fn bk2cmp1p(&mut self) -> BK2CMP1P_W<'_>

Bit 10 - BRK2 COMP1 input polarity

pub fn bk2cmp2p(&mut self) -> BK2CMP2P_W<'_>

Bit 11 - BRK2 COMP2 input polarity

impl W<u32, Reg<u32, _ICR>>

pub fn downcf(&mut self) -> DOWNCF_W<'_>

Bit 6 - Direction change to down Clear Flag

pub fn upcf(&mut self) -> UPCF_W<'_>

Bit 5 - Direction change to UP Clear Flag

pub fn arrokcf(&mut self) -> ARROKCF_W<'_>

Bit 4 - Autoreload register update OK Clear Flag

pub fn cmpokcf(&mut self) -> CMPOKCF_W<'_>

Bit 3 - Compare register update OK Clear Flag

pub fn exttrigcf(&mut self) -> EXTTRIGCF_W<'_>

Bit 2 - External trigger valid edge Clear Flag

pub fn arrmcf(&mut self) -> ARRMCF_W<'_>

Bit 1 - Autoreload match Clear Flag

pub fn cmpmcf(&mut self) -> CMPMCF_W<'_>

Bit 0 - compare match Clear Flag

impl W<u32, Reg<u32, _IER>>

pub fn downie(&mut self) -> DOWNIE_W<'_>

Bit 6 - Direction change to down Interrupt Enable

pub fn upie(&mut self) -> UPIE_W<'_>

Bit 5 - Direction change to UP Interrupt Enable

pub fn arrokie(&mut self) -> ARROKIE_W<'_>

Bit 4 - Autoreload register update OK Interrupt Enable

pub fn cmpokie(&mut self) -> CMPOKIE_W<'_>

Bit 3 - Compare register update OK Interrupt Enable

pub fn exttrigie(&mut self) -> EXTTRIGIE_W<'_>

Bit 2 - External trigger valid edge Interrupt Enable

pub fn arrmie(&mut self) -> ARRMIE_W<'_>

Bit 1 - Autoreload match Interrupt Enable

pub fn cmpmie(&mut self) -> CMPMIE_W<'_>

Bit 0 - Compare match Interrupt Enable

impl W<u32, Reg<u32, _CFGR>>

pub fn enc(&mut self) -> ENC_W<'_>

Bit 24 - Encoder mode enable

pub fn countmode(&mut self) -> COUNTMODE_W<'_>

Bit 23 - counter mode enabled

pub fn preload(&mut self) -> PRELOAD_W<'_>

Bit 22 - Registers update mode

pub fn wavpol(&mut self) -> WAVPOL_W<'_>

Bit 21 - Waveform shape polarity

pub fn wave(&mut self) -> WAVE_W<'_>

Bit 20 - Waveform shape

pub fn timout(&mut self) -> TIMOUT_W<'_>

Bit 19 - Timeout enable

pub fn trigen(&mut self) -> TRIGEN_W<'_>

Bits 17:18 - Trigger enable and polarity

pub fn trigsel(&mut self) -> TRIGSEL_W<'_>

Bits 13:15 - Trigger selector

pub fn presc(&mut self) -> PRESC_W<'_>

Bits 9:11 - Clock prescaler

pub fn trgflt(&mut self) -> TRGFLT_W<'_>

Bits 6:7 - Configurable digital filter for trigger

pub fn ckflt(&mut self) -> CKFLT_W<'_>

Bits 3:4 - Configurable digital filter for external clock

pub fn ckpol(&mut self) -> CKPOL_W<'_>

Bits 1:2 - Clock Polarity

pub fn cksel(&mut self) -> CKSEL_W<'_>

Bit 0 - Clock selector

impl W<u32, Reg<u32, _CR>>

pub fn rstare(&mut self) -> RSTARE_W<'_>

Bit 4 - Reset after read enable

pub fn countrst(&mut self) -> COUNTRST_W<'_>

Bit 3 - Counter reset

pub fn cntstrt(&mut self) -> CNTSTRT_W<'_>

Bit 2 - Timer start in continuous mode

pub fn sngstrt(&mut self) -> SNGSTRT_W<'_>

Bit 1 - LPTIM start in single mode

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 0 - LPTIM Enable

impl W<u32, Reg<u32, _CMP>>

pub fn cmp(&mut self) -> CMP_W<'_>

Bits 0:15 - Compare value

impl W<u32, Reg<u32, _ARR>>

pub fn arr(&mut self) -> ARR_W<'_>

Bits 0:15 - Auto reload value

impl W<u32, Reg<u32, _OR>>

pub fn or1(&mut self) -> OR1_W<'_>

Bit 0 - Option register bit 1

pub fn or2(&mut self) -> OR2_W<'_>

Bit 1 - Option register bit 2

impl W<u32, Reg<u32, _CR1>>

pub fn rxffie(&mut self) -> RXFFIE_W<'_>

Bit 31 - RXFIFO Full interrupt enable

pub fn txfeie(&mut self) -> TXFEIE_W<'_>

Bit 30 - TXFIFO empty interrupt enable

pub fn fifoen(&mut self) -> FIFOEN_W<'_>

Bit 29 - FIFO mode enable

pub fn m1(&mut self) -> M1_W<'_>

Bit 28 - Word length

pub fn eobie(&mut self) -> EOBIE_W<'_>

Bit 27 - End of Block interrupt enable

pub fn rtoie(&mut self) -> RTOIE_W<'_>

Bit 26 - Receiver timeout interrupt enable

pub fn deat4(&mut self) -> DEAT4_W<'_>

Bit 25 - Driver Enable assertion time

pub fn deat3(&mut self) -> DEAT3_W<'_>

Bit 24 - DEAT3

pub fn deat2(&mut self) -> DEAT2_W<'_>

Bit 23 - DEAT2

pub fn deat1(&mut self) -> DEAT1_W<'_>

Bit 22 - DEAT1

pub fn deat0(&mut self) -> DEAT0_W<'_>

Bit 21 - DEAT0

pub fn dedt4(&mut self) -> DEDT4_W<'_>

Bit 20 - Driver Enable de-assertion time

pub fn dedt3(&mut self) -> DEDT3_W<'_>

Bit 19 - DEDT3

pub fn dedt2(&mut self) -> DEDT2_W<'_>

Bit 18 - DEDT2

pub fn dedt1(&mut self) -> DEDT1_W<'_>

Bit 17 - DEDT1

pub fn dedt0(&mut self) -> DEDT0_W<'_>

Bit 16 - DEDT0

pub fn over8(&mut self) -> OVER8_W<'_>

Bit 15 - Oversampling mode

pub fn cmie(&mut self) -> CMIE_W<'_>

Bit 14 - Character match interrupt enable

pub fn mme(&mut self) -> MME_W<'_>

Bit 13 - Mute mode enable

pub fn m0(&mut self) -> M0_W<'_>

Bit 12 - Word length

pub fn wake(&mut self) -> WAKE_W<'_>

Bit 11 - Receiver wakeup method

pub fn pce(&mut self) -> PCE_W<'_>

Bit 10 - Parity control enable

pub fn ps(&mut self) -> PS_W<'_>

Bit 9 - Parity selection

pub fn peie(&mut self) -> PEIE_W<'_>

Bit 8 - PE interrupt enable

pub fn txeie(&mut self) -> TXEIE_W<'_>

Bit 7 - interrupt enable

pub fn tcie(&mut self) -> TCIE_W<'_>

Bit 6 - Transmission complete interrupt enable

pub fn rxneie(&mut self) -> RXNEIE_W<'_>

Bit 5 - RXNE interrupt enable

pub fn idleie(&mut self) -> IDLEIE_W<'_>

Bit 4 - IDLE interrupt enable

pub fn te(&mut self) -> TE_W<'_>

Bit 3 - Transmitter enable

pub fn re(&mut self) -> RE_W<'_>

Bit 2 - Receiver enable

pub fn uesm(&mut self) -> UESM_W<'_>

Bit 1 - USART enable in Stop mode

pub fn ue(&mut self) -> UE_W<'_>

Bit 0 - USART enable

impl W<u32, Reg<u32, _CR2>>

pub fn add4_7(&mut self) -> ADD4_7_W<'_>

Bits 28:31 - Address of the USART node

pub fn add0_3(&mut self) -> ADD0_3_W<'_>

Bits 24:27 - Address of the USART node

pub fn rtoen(&mut self) -> RTOEN_W<'_>

Bit 23 - Receiver timeout enable

pub fn abrmod1(&mut self) -> ABRMOD1_W<'_>

Bit 22 - Auto baud rate mode

pub fn abrmod0(&mut self) -> ABRMOD0_W<'_>

Bit 21 - ABRMOD0

pub fn abren(&mut self) -> ABREN_W<'_>

Bit 20 - Auto baud rate enable

pub fn msbfirst(&mut self) -> MSBFIRST_W<'_>

Bit 19 - Most significant bit first

pub fn tainv(&mut self) -> TAINV_W<'_>

Bit 18 - Binary data inversion

pub fn txinv(&mut self) -> TXINV_W<'_>

Bit 17 - TX pin active level inversion

pub fn rxinv(&mut self) -> RXINV_W<'_>

Bit 16 - RX pin active level inversion

pub fn swap(&mut self) -> SWAP_W<'_>

Bit 15 - Swap TX/RX pins

pub fn linen(&mut self) -> LINEN_W<'_>

Bit 14 - LIN mode enable

pub fn stop(&mut self) -> STOP_W<'_>

Bits 12:13 - STOP bits

pub fn clken(&mut self) -> CLKEN_W<'_>

Bit 11 - Clock enable

pub fn cpol(&mut self) -> CPOL_W<'_>

Bit 10 - Clock polarity

pub fn cpha(&mut self) -> CPHA_W<'_>

Bit 9 - Clock phase

pub fn lbcl(&mut self) -> LBCL_W<'_>

Bit 8 - Last bit clock pulse

pub fn lbdie(&mut self) -> LBDIE_W<'_>

Bit 6 - LIN break detection interrupt enable

pub fn lbdl(&mut self) -> LBDL_W<'_>

Bit 5 - LIN break detection length

pub fn addm7(&mut self) -> ADDM7_W<'_>

Bit 4 - 7-bit Address Detection/4-bit Address Detection

pub fn dis_nss(&mut self) -> DIS_NSS_W<'_>

Bit 3 - When the DSI_NSS bit is set, the NSS pin input will be ignored

pub fn slven(&mut self) -> SLVEN_W<'_>

Bit 0 - Synchronous Slave mode enable

impl W<u32, Reg<u32, _CR3>>

pub fn txftcfg(&mut self) -> TXFTCFG_W<'_>

Bits 29:31 - TXFIFO threshold configuration

pub fn rxftie(&mut self) -> RXFTIE_W<'_>

Bit 28 - RXFIFO threshold interrupt enable

pub fn rxftcfg(&mut self) -> RXFTCFG_W<'_>

Bits 25:27 - Receive FIFO threshold configuration

pub fn tcbgtie(&mut self) -> TCBGTIE_W<'_>

Bit 24 - Tr Complete before guard time, interrupt enable

pub fn txftie(&mut self) -> TXFTIE_W<'_>

Bit 23 - threshold interrupt enable

pub fn wufie(&mut self) -> WUFIE_W<'_>

Bit 22 - Wakeup from Stop mode interrupt enable

pub fn wus(&mut self) -> WUS_W<'_>

Bits 20:21 - Wakeup from Stop mode interrupt flag selection

pub fn scarcnt(&mut self) -> SCARCNT_W<'_>

Bits 17:19 - Smartcard auto-retry count

pub fn dep(&mut self) -> DEP_W<'_>

Bit 15 - Driver enable polarity selection

pub fn dem(&mut self) -> DEM_W<'_>

Bit 14 - Driver enable mode

pub fn ddre(&mut self) -> DDRE_W<'_>

Bit 13 - DMA Disable on Reception Error

pub fn ovrdis(&mut self) -> OVRDIS_W<'_>

Bit 12 - Overrun Disable

pub fn onebit(&mut self) -> ONEBIT_W<'_>

Bit 11 - One sample bit method enable

pub fn ctsie(&mut self) -> CTSIE_W<'_>

Bit 10 - CTS interrupt enable

pub fn ctse(&mut self) -> CTSE_W<'_>

Bit 9 - CTS enable

pub fn rtse(&mut self) -> RTSE_W<'_>

Bit 8 - RTS enable

pub fn dmat(&mut self) -> DMAT_W<'_>

Bit 7 - DMA enable transmitter

pub fn dmar(&mut self) -> DMAR_W<'_>

Bit 6 - DMA enable receiver

pub fn scen(&mut self) -> SCEN_W<'_>

Bit 5 - Smartcard mode enable

pub fn nack(&mut self) -> NACK_W<'_>

Bit 4 - Smartcard NACK enable

pub fn hdsel(&mut self) -> HDSEL_W<'_>

Bit 3 - Half-duplex selection

pub fn irlp(&mut self) -> IRLP_W<'_>

Bit 2 - Ir low-power

pub fn iren(&mut self) -> IREN_W<'_>

Bit 1 - Ir mode enable

pub fn eie(&mut self) -> EIE_W<'_>

Bit 0 - Error interrupt enable

impl W<u32, Reg<u32, _BRR>>

pub fn brr(&mut self) -> BRR_W<'_>

Bits 0:15 - BRR_4_15

impl W<u32, Reg<u32, _GTPR>>

pub fn gt(&mut self) -> GT_W<'_>

Bits 8:15 - Guard time value

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:7 - Prescaler value

impl W<u32, Reg<u32, _RTOR>>

pub fn blen(&mut self) -> BLEN_W<'_>

Bits 24:31 - Block Length

pub fn rto(&mut self) -> RTO_W<'_>

Bits 0:23 - Receiver timeout value

impl W<u32, Reg<u32, _RQR>>

pub fn txfrq(&mut self) -> TXFRQ_W<'_>

Bit 4 - Transmit data flush request

pub fn rxfrq(&mut self) -> RXFRQ_W<'_>

Bit 3 - Receive data flush request

pub fn mmrq(&mut self) -> MMRQ_W<'_>

Bit 2 - Mute mode request

pub fn sbkrq(&mut self) -> SBKRQ_W<'_>

Bit 1 - Send break request

pub fn abrrq(&mut self) -> ABRRQ_W<'_>

Bit 0 - Auto baud rate request

impl W<u32, Reg<u32, _ICR>>

pub fn wucf(&mut self) -> WUCF_W<'_>

Bit 20 - Wakeup from Stop mode clear flag

pub fn cmcf(&mut self) -> CMCF_W<'_>

Bit 17 - Character match clear flag

pub fn udrcf(&mut self) -> UDRCF_W<'_>

Bit 13 - SPI slave underrun clear flag

pub fn eobcf(&mut self) -> EOBCF_W<'_>

Bit 12 - End of block clear flag

pub fn rtocf(&mut self) -> RTOCF_W<'_>

Bit 11 - Receiver timeout clear flag

pub fn ctscf(&mut self) -> CTSCF_W<'_>

Bit 9 - CTS clear flag

pub fn lbdcf(&mut self) -> LBDCF_W<'_>

Bit 8 - LIN break detection clear flag

pub fn tcbgtcf(&mut self) -> TCBGTCF_W<'_>

Bit 7 - Transmission complete before Guard time clear flag

pub fn tccf(&mut self) -> TCCF_W<'_>

Bit 6 - Transmission complete clear flag

pub fn txfecf(&mut self) -> TXFECF_W<'_>

Bit 5 - TXFIFO empty clear flag

pub fn idlecf(&mut self) -> IDLECF_W<'_>

Bit 4 - Idle line detected clear flag

pub fn orecf(&mut self) -> ORECF_W<'_>

Bit 3 - Overrun error clear flag

pub fn ncf(&mut self) -> NCF_W<'_>

Bit 2 - Noise detected clear flag

pub fn fecf(&mut self) -> FECF_W<'_>

Bit 1 - Framing error clear flag

pub fn pecf(&mut self) -> PECF_W<'_>

Bit 0 - Parity error clear flag

impl W<u32, Reg<u32, _TDR>>

pub fn tdr(&mut self) -> TDR_W<'_>

Bits 0:8 - Transmit data value

impl W<u32, Reg<u32, _PRESC>>

pub fn prescaler(&mut self) -> PRESCALER_W<'_>

Bits 0:3 - Clock prescaler

impl W<u32, Reg<u32, _CR1>>

pub fn bidimode(&mut self) -> BIDIMODE_W<'_>

Bit 15 - Bidirectional data mode enable

pub fn bidioe(&mut self) -> BIDIOE_W<'_>

Bit 14 - Output enable in bidirectional mode

pub fn crcen(&mut self) -> CRCEN_W<'_>

Bit 13 - Hardware CRC calculation enable

pub fn crcnext(&mut self) -> CRCNEXT_W<'_>

Bit 12 - CRC transfer next

pub fn dff(&mut self) -> DFF_W<'_>

Bit 11 - Data frame format

pub fn rxonly(&mut self) -> RXONLY_W<'_>

Bit 10 - Receive only

pub fn ssm(&mut self) -> SSM_W<'_>

Bit 9 - Software slave management

pub fn ssi(&mut self) -> SSI_W<'_>

Bit 8 - Internal slave select

pub fn lsbfirst(&mut self) -> LSBFIRST_W<'_>

Bit 7 - Frame format

pub fn spe(&mut self) -> SPE_W<'_>

Bit 6 - SPI enable

pub fn br(&mut self) -> BR_W<'_>

Bits 3:5 - Baud rate control

pub fn mstr(&mut self) -> MSTR_W<'_>

Bit 2 - Master selection

pub fn cpol(&mut self) -> CPOL_W<'_>

Bit 1 - Clock polarity

pub fn cpha(&mut self) -> CPHA_W<'_>

Bit 0 - Clock phase

impl W<u32, Reg<u32, _CR2>>

pub fn rxdmaen(&mut self) -> RXDMAEN_W<'_>

Bit 0 - Rx buffer DMA enable

pub fn txdmaen(&mut self) -> TXDMAEN_W<'_>

Bit 1 - Tx buffer DMA enable

pub fn ssoe(&mut self) -> SSOE_W<'_>

Bit 2 - SS output enable

pub fn nssp(&mut self) -> NSSP_W<'_>

Bit 3 - NSS pulse management

pub fn frf(&mut self) -> FRF_W<'_>

Bit 4 - Frame format

pub fn errie(&mut self) -> ERRIE_W<'_>

Bit 5 - Error interrupt enable

pub fn rxneie(&mut self) -> RXNEIE_W<'_>

Bit 6 - RX buffer not empty interrupt enable

pub fn txeie(&mut self) -> TXEIE_W<'_>

Bit 7 - Tx buffer empty interrupt enable

pub fn ds(&mut self) -> DS_W<'_>

Bits 8:11 - Data size

pub fn frxth(&mut self) -> FRXTH_W<'_>

Bit 12 - FIFO reception threshold

pub fn ldma_rx(&mut self) -> LDMA_RX_W<'_>

Bit 13 - Last DMA transfer for reception

pub fn ldma_tx(&mut self) -> LDMA_TX_W<'_>

Bit 14 - Last DMA transfer for transmission

impl W<u32, Reg<u32, _SR>>

pub fn crcerr(&mut self) -> CRCERR_W<'_>

Bit 4 - CRC error flag

impl W<u32, Reg<u32, _DR>>

pub fn dr(&mut self) -> DR_W<'_>

Bits 0:15 - Data register

impl W<u32, Reg<u32, _CRCPR>>

pub fn crcpoly(&mut self) -> CRCPOLY_W<'_>

Bits 0:15 - CRC polynomial register

impl W<u32, Reg<u32, _CSR>>

pub fn envr(&mut self) -> ENVR_W<'_>

Bit 0 - Voltage reference buffer enable

pub fn hiz(&mut self) -> HIZ_W<'_>

Bit 1 - High impedance mode

pub fn vrs(&mut self) -> VRS_W<'_>

Bit 2 - Voltage reference scale

impl W<u32, Reg<u32, _CCR>>

pub fn trim(&mut self) -> TRIM_W<'_>

Bits 0:5 - Trimming code

impl W<u32, Reg<u32, _TR>>

pub fn pm(&mut self) -> PM_W<'_>

Bit 22 - AM/PM notation

pub fn ht(&mut self) -> HT_W<'_>

Bits 20:21 - Hour tens in BCD format

pub fn hu(&mut self) -> HU_W<'_>

Bits 16:19 - Hour units in BCD format

pub fn mnt(&mut self) -> MNT_W<'_>

Bits 12:14 - Minute tens in BCD format

pub fn mnu(&mut self) -> MNU_W<'_>

Bits 8:11 - Minute units in BCD format

pub fn st(&mut self) -> ST_W<'_>

Bits 4:6 - Second tens in BCD format

pub fn su(&mut self) -> SU_W<'_>

Bits 0:3 - Second units in BCD format

impl W<u32, Reg<u32, _DR>>

pub fn yt(&mut self) -> YT_W<'_>

Bits 20:23 - Year tens in BCD format

pub fn yu(&mut self) -> YU_W<'_>

Bits 16:19 - Year units in BCD format

pub fn wdu(&mut self) -> WDU_W<'_>

Bits 13:15 - Week day units

pub fn mt(&mut self) -> MT_W<'_>

Bit 12 - Month tens in BCD format

pub fn mu(&mut self) -> MU_W<'_>

Bits 8:11 - Month units in BCD format

pub fn dt(&mut self) -> DT_W<'_>

Bits 4:5 - Date tens in BCD format

pub fn du(&mut self) -> DU_W<'_>

Bits 0:3 - Date units in BCD format

impl W<u32, Reg<u32, _CR>>

pub fn wucksel(&mut self) -> WUCKSEL_W<'_>

Bits 0:2 - Wakeup clock selection

pub fn tsedge(&mut self) -> TSEDGE_W<'_>

Bit 3 - Time-stamp event active edge

pub fn refckon(&mut self) -> REFCKON_W<'_>

Bit 4 - Reference clock detection enable (50 or 60 Hz)

pub fn bypshad(&mut self) -> BYPSHAD_W<'_>

Bit 5 - Bypass the shadow registers

pub fn fmt(&mut self) -> FMT_W<'_>

Bit 6 - Hour format

pub fn alrae(&mut self) -> ALRAE_W<'_>

Bit 8 - Alarm A enable

pub fn alrbe(&mut self) -> ALRBE_W<'_>

Bit 9 - Alarm B enable

pub fn wute(&mut self) -> WUTE_W<'_>

Bit 10 - Wakeup timer enable

pub fn tse(&mut self) -> TSE_W<'_>

Bit 11 - Time stamp enable

pub fn alraie(&mut self) -> ALRAIE_W<'_>

Bit 12 - Alarm A interrupt enable

pub fn alrbie(&mut self) -> ALRBIE_W<'_>

Bit 13 - Alarm B interrupt enable

pub fn wutie(&mut self) -> WUTIE_W<'_>

Bit 14 - Wakeup timer interrupt enable

pub fn tsie(&mut self) -> TSIE_W<'_>

Bit 15 - Time-stamp interrupt enable

pub fn add1h(&mut self) -> ADD1H_W<'_>

Bit 16 - Add 1 hour (summer time change)

pub fn sub1h(&mut self) -> SUB1H_W<'_>

Bit 17 - Subtract 1 hour (winter time change)

pub fn bkp(&mut self) -> BKP_W<'_>

Bit 18 - Backup

pub fn cosel(&mut self) -> COSEL_W<'_>

Bit 19 - Calibration output selection

pub fn pol(&mut self) -> POL_W<'_>

Bit 20 - Output polarity

pub fn osel(&mut self) -> OSEL_W<'_>

Bits 21:22 - Output selection

pub fn coe(&mut self) -> COE_W<'_>

Bit 23 - Calibration output enable

pub fn itse(&mut self) -> ITSE_W<'_>

Bit 24 - timestamp on internal event enable

impl W<u32, Reg<u32, _ISR>>

pub fn shpf(&mut self) -> SHPF_W<'_>

Bit 3 - Shift operation pending

pub fn rsf(&mut self) -> RSF_W<'_>

Bit 5 - Registers synchronization flag

pub fn init(&mut self) -> INIT_W<'_>

Bit 7 - Initialization mode

pub fn alraf(&mut self) -> ALRAF_W<'_>

Bit 8 - Alarm A flag

pub fn alrbf(&mut self) -> ALRBF_W<'_>

Bit 9 - Alarm B flag

pub fn wutf(&mut self) -> WUTF_W<'_>

Bit 10 - Wakeup timer flag

pub fn tsf(&mut self) -> TSF_W<'_>

Bit 11 - Time-stamp flag

pub fn tsovf(&mut self) -> TSOVF_W<'_>

Bit 12 - Time-stamp overflow flag

pub fn tamp1f(&mut self) -> TAMP1F_W<'_>

Bit 13 - Tamper detection flag

pub fn tamp2f(&mut self) -> TAMP2F_W<'_>

Bit 14 - RTC_TAMP2 detection flag

pub fn tamp3f(&mut self) -> TAMP3F_W<'_>

Bit 15 - RTC_TAMP3 detection flag

pub fn itsf(&mut self) -> ITSF_W<'_>

Bit 17 - INTERNAL TIME-STAMP FLAG

impl W<u32, Reg<u32, _PRER>>

pub fn prediv_a(&mut self) -> PREDIV_A_W<'_>

Bits 16:22 - Asynchronous prescaler factor

pub fn prediv_s(&mut self) -> PREDIV_S_W<'_>

Bits 0:14 - Synchronous prescaler factor

impl W<u32, Reg<u32, _WUTR>>

pub fn wut(&mut self) -> WUT_W<'_>

Bits 0:15 - Wakeup auto-reload value bits

impl W<u32, Reg<u32, _ALRMAR>>

pub fn msk4(&mut self) -> MSK4_W<'_>

Bit 31 - Alarm A date mask

pub fn wdsel(&mut self) -> WDSEL_W<'_>

Bit 30 - Week day selection

pub fn dt(&mut self) -> DT_W<'_>

Bits 28:29 - Date tens in BCD format

pub fn du(&mut self) -> DU_W<'_>

Bits 24:27 - Date units or day in BCD format

pub fn msk3(&mut self) -> MSK3_W<'_>

Bit 23 - Alarm A hours mask

pub fn pm(&mut self) -> PM_W<'_>

Bit 22 - AM/PM notation

pub fn ht(&mut self) -> HT_W<'_>

Bits 20:21 - Hour tens in BCD format

pub fn hu(&mut self) -> HU_W<'_>

Bits 16:19 - Hour units in BCD format

pub fn msk2(&mut self) -> MSK2_W<'_>

Bit 15 - Alarm A minutes mask

pub fn mnt(&mut self) -> MNT_W<'_>

Bits 12:14 - Minute tens in BCD format

pub fn mnu(&mut self) -> MNU_W<'_>

Bits 8:11 - Minute units in BCD format

pub fn msk1(&mut self) -> MSK1_W<'_>

Bit 7 - Alarm A seconds mask

pub fn st(&mut self) -> ST_W<'_>

Bits 4:6 - Second tens in BCD format

pub fn su(&mut self) -> SU_W<'_>

Bits 0:3 - Second units in BCD format

impl W<u32, Reg<u32, _ALRMBR>>

pub fn msk4(&mut self) -> MSK4_W<'_>

Bit 31 - Alarm B date mask

pub fn wdsel(&mut self) -> WDSEL_W<'_>

Bit 30 - Week day selection

pub fn dt(&mut self) -> DT_W<'_>

Bits 28:29 - Date tens in BCD format

pub fn du(&mut self) -> DU_W<'_>

Bits 24:27 - Date units or day in BCD format

pub fn msk3(&mut self) -> MSK3_W<'_>

Bit 23 - Alarm B hours mask

pub fn pm(&mut self) -> PM_W<'_>

Bit 22 - AM/PM notation

pub fn ht(&mut self) -> HT_W<'_>

Bits 20:21 - Hour tens in BCD format

pub fn hu(&mut self) -> HU_W<'_>

Bits 16:19 - Hour units in BCD format

pub fn msk2(&mut self) -> MSK2_W<'_>

Bit 15 - Alarm B minutes mask

pub fn mnt(&mut self) -> MNT_W<'_>

Bits 12:14 - Minute tens in BCD format

pub fn mnu(&mut self) -> MNU_W<'_>

Bits 8:11 - Minute units in BCD format

pub fn msk1(&mut self) -> MSK1_W<'_>

Bit 7 - Alarm B seconds mask

pub fn st(&mut self) -> ST_W<'_>

Bits 4:6 - Second tens in BCD format

pub fn su(&mut self) -> SU_W<'_>

Bits 0:3 - Second units in BCD format

impl W<u32, Reg<u32, _WPR>>

pub fn key(&mut self) -> KEY_W<'_>

Bits 0:7 - Write protection key

impl W<u32, Reg<u32, _SHIFTR>>

pub fn add1s(&mut self) -> ADD1S_W<'_>

Bit 31 - Add one second

pub fn subfs(&mut self) -> SUBFS_W<'_>

Bits 0:14 - Subtract a fraction of a second

impl W<u32, Reg<u32, _CALR>>

pub fn calp(&mut self) -> CALP_W<'_>

Bit 15 - Increase frequency of RTC by 488.5 ppm

pub fn calw8(&mut self) -> CALW8_W<'_>

Bit 14 - Use an 8-second calibration cycle period

pub fn calw16(&mut self) -> CALW16_W<'_>

Bit 13 - Use a 16-second calibration cycle period

pub fn calm(&mut self) -> CALM_W<'_>

Bits 0:8 - Calibration minus

impl W<u32, Reg<u32, _TAMPCR>>

pub fn tamp1e(&mut self) -> TAMP1E_W<'_>

Bit 0 - Tamper 1 detection enable

pub fn tamp1trg(&mut self) -> TAMP1TRG_W<'_>

Bit 1 - Active level for tamper 1

pub fn tampie(&mut self) -> TAMPIE_W<'_>

Bit 2 - Tamper interrupt enable

pub fn tamp2e(&mut self) -> TAMP2E_W<'_>

Bit 3 - Tamper 2 detection enable

pub fn tamp2trg(&mut self) -> TAMP2TRG_W<'_>

Bit 4 - Active level for tamper 2

pub fn tamp3e(&mut self) -> TAMP3E_W<'_>

Bit 5 - Tamper 3 detection enable

pub fn tamp3trg(&mut self) -> TAMP3TRG_W<'_>

Bit 6 - Active level for tamper 3

pub fn tampts(&mut self) -> TAMPTS_W<'_>

Bit 7 - Activate timestamp on tamper detection event

pub fn tampfreq(&mut self) -> TAMPFREQ_W<'_>

Bits 8:10 - Tamper sampling frequency

pub fn tampflt(&mut self) -> TAMPFLT_W<'_>

Bits 11:12 - Tamper filter count

pub fn tampprch(&mut self) -> TAMPPRCH_W<'_>

Bits 13:14 - Tamper precharge duration

pub fn tamppudis(&mut self) -> TAMPPUDIS_W<'_>

Bit 15 - TAMPER pull-up disable

pub fn tamp1ie(&mut self) -> TAMP1IE_W<'_>

Bit 16 - Tamper 1 interrupt enable

pub fn tamp1noerase(&mut self) -> TAMP1NOERASE_W<'_>

Bit 17 - Tamper 1 no erase

pub fn tamp1mf(&mut self) -> TAMP1MF_W<'_>

Bit 18 - Tamper 1 mask flag

pub fn tamp2ie(&mut self) -> TAMP2IE_W<'_>

Bit 19 - Tamper 2 interrupt enable

pub fn tamp2noerase(&mut self) -> TAMP2NOERASE_W<'_>

Bit 20 - Tamper 2 no erase

pub fn tamp2mf(&mut self) -> TAMP2MF_W<'_>

Bit 21 - Tamper 2 mask flag

pub fn tamp3ie(&mut self) -> TAMP3IE_W<'_>

Bit 22 - Tamper 3 interrupt enable

pub fn tamp3noerase(&mut self) -> TAMP3NOERASE_W<'_>

Bit 23 - Tamper 3 no erase

pub fn tamp3mf(&mut self) -> TAMP3MF_W<'_>

Bit 24 - Tamper 3 mask flag

impl W<u32, Reg<u32, _ALRMASSR>>

pub fn maskss(&mut self) -> MASKSS_W<'_>

Bits 24:27 - Mask the most-significant bits starting at this bit

pub fn ss(&mut self) -> SS_W<'_>

Bits 0:14 - Sub seconds value

impl W<u32, Reg<u32, _ALRMBSSR>>

pub fn maskss(&mut self) -> MASKSS_W<'_>

Bits 24:27 - Mask the most-significant bits starting at this bit

pub fn ss(&mut self) -> SS_W<'_>

Bits 0:14 - Sub seconds value

impl W<u32, Reg<u32, _OR>>

pub fn rtc_alarm_type(&mut self) -> RTC_ALARM_TYPE_W<'_>

Bit 0 - RTC_ALARM on PC13 output type

pub fn rtc_out_rmp(&mut self) -> RTC_OUT_RMP_W<'_>

Bit 1 - RTC_OUT remap

impl W<u32, Reg<u32, _BKP0R>>

pub fn bkp(&mut self) -> BKP_W<'_>

Bits 0:31 - BKP

impl W<u32, Reg<u32, _BKP1R>>

pub fn bkp(&mut self) -> BKP_W<'_>

Bits 0:31 - BKP

impl W<u32, Reg<u32, _BKP2R>>

pub fn bkp(&mut self) -> BKP_W<'_>

Bits 0:31 - BKP

impl W<u32, Reg<u32, _BKP3R>>

pub fn bkp(&mut self) -> BKP_W<'_>

Bits 0:31 - BKP

impl W<u32, Reg<u32, _BKP4R>>

pub fn bkp(&mut self) -> BKP_W<'_>

Bits 0:31 - BKP

impl W<u32, Reg<u32, _BKP5R>>

pub fn bkp(&mut self) -> BKP_W<'_>

Bits 0:31 - BKP

impl W<u32, Reg<u32, _BKP6R>>

pub fn bkp(&mut self) -> BKP_W<'_>

Bits 0:31 - BKP

impl W<u32, Reg<u32, _BKP7R>>

pub fn bkp(&mut self) -> BKP_W<'_>

Bits 0:31 - BKP

impl W<u32, Reg<u32, _BKP8R>>

pub fn bkp(&mut self) -> BKP_W<'_>

Bits 0:31 - BKP

impl W<u32, Reg<u32, _BKP9R>>

pub fn bkp(&mut self) -> BKP_W<'_>

Bits 0:31 - BKP

impl W<u32, Reg<u32, _BKP10R>>

pub fn bkp(&mut self) -> BKP_W<'_>

Bits 0:31 - BKP

impl W<u32, Reg<u32, _BKP11R>>

pub fn bkp(&mut self) -> BKP_W<'_>

Bits 0:31 - BKP

impl W<u32, Reg<u32, _BKP12R>>

pub fn bkp(&mut self) -> BKP_W<'_>

Bits 0:31 - BKP

impl W<u32, Reg<u32, _BKP13R>>

pub fn bkp(&mut self) -> BKP_W<'_>

Bits 0:31 - BKP

impl W<u32, Reg<u32, _BKP14R>>

pub fn bkp(&mut self) -> BKP_W<'_>

Bits 0:31 - BKP

impl W<u32, Reg<u32, _BKP15R>>

pub fn bkp(&mut self) -> BKP_W<'_>

Bits 0:31 - BKP

impl W<u32, Reg<u32, _BKP16R>>

pub fn bkp(&mut self) -> BKP_W<'_>

Bits 0:31 - BKP

impl W<u32, Reg<u32, _BKP17R>>

pub fn bkp(&mut self) -> BKP_W<'_>

Bits 0:31 - BKP

impl W<u32, Reg<u32, _BKP18R>>

pub fn bkp(&mut self) -> BKP_W<'_>

Bits 0:31 - BKP

impl W<u32, Reg<u32, _BKP19R>>

pub fn bkp(&mut self) -> BKP_W<'_>

Bits 0:31 - BKP

impl W<u32, Reg<u32, _CR>>

pub fn dbg_sleep(&mut self) -> DBG_SLEEP_W<'_>

Bit 0 - Debug Sleep Mode

pub fn dbg_stop(&mut self) -> DBG_STOP_W<'_>

Bit 1 - Debug Stop Mode

pub fn dbg_standby(&mut self) -> DBG_STANDBY_W<'_>

Bit 2 - Debug Standby Mode

pub fn trace_ioen(&mut self) -> TRACE_IOEN_W<'_>

Bit 5 - Trace port and clock enable

pub fn trgoen(&mut self) -> TRGOEN_W<'_>

Bit 28 - External trigger output enable

impl W<u32, Reg<u32, _APB1FZR1>>

pub fn dbg_timer2_stop(&mut self) -> DBG_TIMER2_STOP_W<'_>

Bit 0 - Debug Timer 2 stopped when Core is halted

pub fn dbg_rtc_stop(&mut self) -> DBG_RTC_STOP_W<'_>

Bit 10 - RTC counter stopped when core is halted

pub fn dbg_wwdg_stop(&mut self) -> DBG_WWDG_STOP_W<'_>

Bit 11 - WWDG counter stopped when core is halted

pub fn dbg_iwdg_stop(&mut self) -> DBG_IWDG_STOP_W<'_>

Bit 12 - IWDG counter stopped when core is halted

pub fn dbg_i2c1_stop(&mut self) -> DBG_I2C1_STOP_W<'_>

Bit 21 - Debug I2C1 SMBUS timeout stopped when Core is halted

pub fn dbg_i2c3_stop(&mut self) -> DBG_I2C3_STOP_W<'_>

Bit 23 - Debug I2C3 SMBUS timeout stopped when core is halted

pub fn dbg_lptim1_stop(&mut self) -> DBG_LPTIM1_STOP_W<'_>

Bit 31 - Debug LPTIM1 stopped when Core is halted

impl W<u32, Reg<u32, _C2AP_B1FZR1>>

pub fn dbg_lptim2_stop(&mut self) -> DBG_LPTIM2_STOP_W<'_>

Bit 0 - LPTIM2 counter stopped when core is halted

pub fn dbg_rtc_stop(&mut self) -> DBG_RTC_STOP_W<'_>

Bit 10 - RTC counter stopped when core is halted

pub fn dbg_iwdg_stop(&mut self) -> DBG_IWDG_STOP_W<'_>

Bit 12 - IWDG stopped when core is halted

pub fn dbg_i2c1_stop(&mut self) -> DBG_I2C1_STOP_W<'_>

Bit 21 - I2C1 SMBUS timeout stopped when core is halted

pub fn dbg_i2c3_stop(&mut self) -> DBG_I2C3_STOP_W<'_>

Bit 23 - I2C3 SMBUS timeout stopped when core is halted

pub fn dbg_lptim1_stop(&mut self) -> DBG_LPTIM1_STOP_W<'_>

Bit 31 - LPTIM1 counter stopped when core is halted

impl W<u32, Reg<u32, _APB1FZR2>>

pub fn dbg_lptim2_stop(&mut self) -> DBG_LPTIM2_STOP_W<'_>

Bit 5 - LPTIM2 counter stopped when core is halted

impl W<u32, Reg<u32, _C2APB1FZR2>>

pub fn dbg_lptim2_stop(&mut self) -> DBG_LPTIM2_STOP_W<'_>

Bit 5 - LPTIM2 counter stopped when core is halted

impl W<u32, Reg<u32, _APB2FZR>>

pub fn dbg_tim1_stop(&mut self) -> DBG_TIM1_STOP_W<'_>

Bit 11 - TIM1 counter stopped when core is halted

pub fn dbg_tim16_stop(&mut self) -> DBG_TIM16_STOP_W<'_>

Bit 17 - TIM16 counter stopped when core is halted

pub fn dbg_tim17_stop(&mut self) -> DBG_TIM17_STOP_W<'_>

Bit 18 - TIM17 counter stopped when core is halted

impl W<u32, Reg<u32, _C2APB2FZR>>

pub fn dbg_tim1_stop(&mut self) -> DBG_TIM1_STOP_W<'_>

Bit 11 - TIM1 counter stopped when core is halted

pub fn dbg_tim16_stop(&mut self) -> DBG_TIM16_STOP_W<'_>

Bit 17 - TIM16 counter stopped when core is halted

pub fn dbg_tim17_stop(&mut self) -> DBG_TIM17_STOP_W<'_>

Bit 18 - TIM17 counter stopped when core is halted

impl W<u32, Reg<u32, _CR>>

pub fn addrerrie(&mut self) -> ADDRERRIE_W<'_>

Bit 20 - Address error interrupt enable

pub fn ramerrie(&mut self) -> RAMERRIE_W<'_>

Bit 19 - RAM error interrupt enable

pub fn procendie(&mut self) -> PROCENDIE_W<'_>

Bit 17 - End of operation interrupt enable

pub fn mode(&mut self) -> MODE_W<'_>

Bits 8:13 - PKA Operation Mode

pub fn seclvl(&mut self) -> SECLVL_W<'_>

Bit 2 - Security Enable

pub fn start(&mut self) -> START_W<'_>

Bit 1 - Start the operation

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - Peripheral Enable

impl W<u32, Reg<u32, _CLRFR>>

pub fn addrerrfc(&mut self) -> ADDRERRFC_W<'_>

Bit 20 - Clear Address error flag

pub fn ramerrfc(&mut self) -> RAMERRFC_W<'_>

Bit 19 - Clear RAM error flag

pub fn procendfc(&mut self) -> PROCENDFC_W<'_>

Bit 17 - Clear PKA End of Operation flag

impl W<u32, Reg<u32, _C1CR>>

pub fn txfie(&mut self) -> TXFIE_W<'_>

Bit 16 - processor 1 Transmit channel free interrupt enable

pub fn rxoie(&mut self) -> RXOIE_W<'_>

Bit 0 - processor 1 Receive channel occupied interrupt enable

impl W<u32, Reg<u32, _C1MR>>

pub fn ch6fm(&mut self) -> CH6FM_W<'_>

Bit 21 - processor 1 Transmit channel 6 free interrupt mask

pub fn ch5fm(&mut self) -> CH5FM_W<'_>

Bit 20 - processor 1 Transmit channel 5 free interrupt mask

pub fn ch4fm(&mut self) -> CH4FM_W<'_>

Bit 19 - processor 1 Transmit channel 4 free interrupt mask

pub fn ch3fm(&mut self) -> CH3FM_W<'_>

Bit 18 - processor 1 Transmit channel 3 free interrupt mask

pub fn ch2fm(&mut self) -> CH2FM_W<'_>

Bit 17 - processor 1 Transmit channel 2 free interrupt mask

pub fn ch1fm(&mut self) -> CH1FM_W<'_>

Bit 16 - processor 1 Transmit channel 1 free interrupt mask

pub fn ch6om(&mut self) -> CH6OM_W<'_>

Bit 5 - processor 1 Receive channel 6 occupied interrupt enable

pub fn ch5om(&mut self) -> CH5OM_W<'_>

Bit 4 - processor 1 Receive channel 5 occupied interrupt enable

pub fn ch4om(&mut self) -> CH4OM_W<'_>

Bit 3 - processor 1 Receive channel 4 occupied interrupt enable

pub fn ch3om(&mut self) -> CH3OM_W<'_>

Bit 2 - processor 1 Receive channel 3 occupied interrupt enable

pub fn ch2om(&mut self) -> CH2OM_W<'_>

Bit 1 - processor 1 Receive channel 2 occupied interrupt enable

pub fn ch1om(&mut self) -> CH1OM_W<'_>

Bit 0 - processor 1 Receive channel 1 occupied interrupt enable

impl W<u32, Reg<u32, _C1SCR>>

pub fn ch6s(&mut self) -> CH6S_W<'_>

Bit 21 - processor 1 Transmit channel 6 status set

pub fn ch5s(&mut self) -> CH5S_W<'_>

Bit 20 - processor 1 Transmit channel 5 status set

pub fn ch4s(&mut self) -> CH4S_W<'_>

Bit 19 - processor 1 Transmit channel 4 status set

pub fn ch3s(&mut self) -> CH3S_W<'_>

Bit 18 - processor 1 Transmit channel 3 status set

pub fn ch2s(&mut self) -> CH2S_W<'_>

Bit 17 - processor 1 Transmit channel 2 status set

pub fn ch1s(&mut self) -> CH1S_W<'_>

Bit 16 - processor 1 Transmit channel 1 status set

pub fn ch6c(&mut self) -> CH6C_W<'_>

Bit 5 - processor 1 Receive channel 6 status clear

pub fn ch5c(&mut self) -> CH5C_W<'_>

Bit 4 - processor 1 Receive channel 5 status clear

pub fn ch4c(&mut self) -> CH4C_W<'_>

Bit 3 - processor 1 Receive channel 4 status clear

pub fn ch3c(&mut self) -> CH3C_W<'_>

Bit 2 - processor 1 Receive channel 3 status clear

pub fn ch2c(&mut self) -> CH2C_W<'_>

Bit 1 - processor 1 Receive channel 2 status clear

pub fn ch1c(&mut self) -> CH1C_W<'_>

Bit 0 - processor 1 Receive channel 1 status clear

impl W<u32, Reg<u32, _C2CR>>

pub fn txfie(&mut self) -> TXFIE_W<'_>

Bit 16 - processor 2 Transmit channel free interrupt enable

pub fn rxoie(&mut self) -> RXOIE_W<'_>

Bit 0 - processor 2 Receive channel occupied interrupt enable

impl W<u32, Reg<u32, _C2MR>>

pub fn ch6fm(&mut self) -> CH6FM_W<'_>

Bit 21 - processor 2 Transmit channel 6 free interrupt mask

pub fn ch5fm(&mut self) -> CH5FM_W<'_>

Bit 20 - processor 2 Transmit channel 5 free interrupt mask

pub fn ch4fm(&mut self) -> CH4FM_W<'_>

Bit 19 - processor 2 Transmit channel 4 free interrupt mask

pub fn ch3fm(&mut self) -> CH3FM_W<'_>

Bit 18 - processor 2 Transmit channel 3 free interrupt mask

pub fn ch2fm(&mut self) -> CH2FM_W<'_>

Bit 17 - processor 2 Transmit channel 2 free interrupt mask

pub fn ch1fm(&mut self) -> CH1FM_W<'_>

Bit 16 - processor 2 Transmit channel 1 free interrupt mask

pub fn ch6om(&mut self) -> CH6OM_W<'_>

Bit 5 - processor 2 Receive channel 6 occupied interrupt enable

pub fn ch5om(&mut self) -> CH5OM_W<'_>

Bit 4 - processor 2 Receive channel 5 occupied interrupt enable

pub fn ch4om(&mut self) -> CH4OM_W<'_>

Bit 3 - processor 2 Receive channel 4 occupied interrupt enable

pub fn ch3om(&mut self) -> CH3OM_W<'_>

Bit 2 - processor 2 Receive channel 3 occupied interrupt enable

pub fn ch2om(&mut self) -> CH2OM_W<'_>

Bit 1 - processor 2 Receive channel 2 occupied interrupt enable

pub fn ch1om(&mut self) -> CH1OM_W<'_>

Bit 0 - processor 2 Receive channel 1 occupied interrupt enable

impl W<u32, Reg<u32, _C2SCR>>

pub fn ch6s(&mut self) -> CH6S_W<'_>

Bit 21 - processor 2 Transmit channel 6 status set

pub fn ch5s(&mut self) -> CH5S_W<'_>

Bit 20 - processor 2 Transmit channel 5 status set

pub fn ch4s(&mut self) -> CH4S_W<'_>

Bit 19 - processor 2 Transmit channel 4 status set

pub fn ch3s(&mut self) -> CH3S_W<'_>

Bit 18 - processor 2 Transmit channel 3 status set

pub fn ch2s(&mut self) -> CH2S_W<'_>

Bit 17 - processor 2 Transmit channel 2 status set

pub fn ch1s(&mut self) -> CH1S_W<'_>

Bit 16 - processor 2 Transmit channel 1 status set

pub fn ch6c(&mut self) -> CH6C_W<'_>

Bit 5 - processor 2 Receive channel 6 status clear

pub fn ch5c(&mut self) -> CH5C_W<'_>

Bit 4 - processor 2 Receive channel 5 status clear

pub fn ch4c(&mut self) -> CH4C_W<'_>

Bit 3 - processor 2 Receive channel 4 status clear

pub fn ch3c(&mut self) -> CH3C_W<'_>

Bit 2 - processor 2 Receive channel 3 status clear

pub fn ch2c(&mut self) -> CH2C_W<'_>

Bit 1 - processor 2 Receive channel 2 status clear

pub fn ch1c(&mut self) -> CH1C_W<'_>

Bit 0 - processor 2 Receive channel 1 status clear

impl W<u32, Reg<u32, _RTSR1>>

pub fn rt(&mut self) -> RT_W<'_>

Bits 0:21 - Rising trigger event configuration bit of Configurable Event input

pub fn rt_31(&mut self) -> RT_31_W<'_>

Bit 31 - Rising trigger event configuration bit of Configurable Event input

impl W<u32, Reg<u32, _FTSR1>>

pub fn ft(&mut self) -> FT_W<'_>

Bits 0:21 - Falling trigger event configuration bit of Configurable Event input

pub fn ft_31(&mut self) -> FT_31_W<'_>

Bit 31 - Falling trigger event configuration bit of Configurable Event input

impl W<u32, Reg<u32, _SWIER1>>

pub fn swi(&mut self) -> SWI_W<'_>

Bits 0:21 - Software interrupt on event

pub fn swi_31(&mut self) -> SWI_31_W<'_>

Bit 31 - Software interrupt on event

impl W<u32, Reg<u32, _PR1>>

pub fn pif(&mut self) -> PIF_W<'_>

Bits 0:21 - Configurable event inputs Pending bit

pub fn pif_31(&mut self) -> PIF_31_W<'_>

Bit 31 - Configurable event inputs Pending bit

impl W<u32, Reg<u32, _RTSR2>>

pub fn rt33(&mut self) -> RT33_W<'_>

Bit 1 - Rising trigger event configuration bit of Configurable Event input

pub fn rt40_41(&mut self) -> RT40_41_W<'_>

Bits 8:9 - Rising trigger event configuration bit of Configurable Event input

impl W<u32, Reg<u32, _FTSR2>>

pub fn ft33(&mut self) -> FT33_W<'_>

Bit 1 - Falling trigger event configuration bit of Configurable Event input

pub fn ft40_41(&mut self) -> FT40_41_W<'_>

Bits 8:9 - Falling trigger event configuration bit of Configurable Event input

impl W<u32, Reg<u32, _SWIER2>>

pub fn swi33(&mut self) -> SWI33_W<'_>

Bit 1 - Software interrupt on event

pub fn swi40_41(&mut self) -> SWI40_41_W<'_>

Bits 8:9 - Software interrupt on event

impl W<u32, Reg<u32, _PR2>>

pub fn pif33(&mut self) -> PIF33_W<'_>

Bit 1 - Configurable event inputs x+32 Pending bit.

pub fn pif40_41(&mut self) -> PIF40_41_W<'_>

Bits 8:9 - Configurable event inputs x+32 Pending bit.

impl W<u32, Reg<u32, _C1IMR1>>

pub fn im(&mut self) -> IM_W<'_>

Bits 0:31 - CPU(m) wakeup with interrupt Mask on Event input

impl W<u32, Reg<u32, _C2IMR1>>

pub fn im(&mut self) -> IM_W<'_>

Bits 0:31 - CPU(m) wakeup with interrupt Mask on Event input

impl W<u32, Reg<u32, _C1EMR1>>

pub fn em0_15(&mut self) -> EM0_15_W<'_>

Bits 0:15 - CPU(m) Wakeup with event generation Mask on Event input

pub fn em17_21(&mut self) -> EM17_21_W<'_>

Bits 17:21 - CPU(m) Wakeup with event generation Mask on Event input

impl W<u32, Reg<u32, _C2EMR1>>

pub fn em0_15(&mut self) -> EM0_15_W<'_>

Bits 0:15 - CPU(m) Wakeup with event generation Mask on Event input

pub fn em17_21(&mut self) -> EM17_21_W<'_>

Bits 17:21 - CPU(m) Wakeup with event generation Mask on Event input

impl W<u32, Reg<u32, _C1IMR2>>

pub fn im(&mut self) -> IM_W<'_>

Bits 0:16 - CPUm Wakeup with interrupt Mask on Event input

impl W<u32, Reg<u32, _C2IMR2>>

pub fn im(&mut self) -> IM_W<'_>

Bits 0:16 - CPUm Wakeup with interrupt Mask on Event input

impl W<u32, Reg<u32, _C1EMR2>>

pub fn em(&mut self) -> EM_W<'_>

Bits 8:9 - CPU(m) Wakeup with event generation Mask on Event input

impl W<u32, Reg<u32, _C2EMR2>>

pub fn em(&mut self) -> EM_W<'_>

Bits 8:9 - CPU(m) Wakeup with event generation Mask on Event input

impl W<u32, Reg<u32, _CR>>

pub fn syncokie(&mut self) -> SYNCOKIE_W<'_>

Bit 0 - SYNC event OK interrupt enable

pub fn syncwarnie(&mut self) -> SYNCWARNIE_W<'_>

Bit 1 - SYNC warning interrupt enable

pub fn errie(&mut self) -> ERRIE_W<'_>

Bit 2 - Synchronization or trimming error interrupt enable

pub fn esyncie(&mut self) -> ESYNCIE_W<'_>

Bit 3 - Expected SYNC interrupt enable

pub fn cen(&mut self) -> CEN_W<'_>

Bit 5 - Frequency error counter enable

pub fn autotrimen(&mut self) -> AUTOTRIMEN_W<'_>

Bit 6 - Automatic trimming enable

pub fn swsync(&mut self) -> SWSYNC_W<'_>

Bit 7 - Automatic trimming enable

pub fn trim(&mut self) -> TRIM_W<'_>

Bits 8:13 - HSI48 oscillator smooth trimming

impl W<u32, Reg<u32, _CFGR>>

pub fn reload(&mut self) -> RELOAD_W<'_>

Bits 0:15 - Counter reload value

pub fn felim(&mut self) -> FELIM_W<'_>

Bits 16:23 - Frequency error limit

pub fn syncdiv(&mut self) -> SYNCDIV_W<'_>

Bits 24:26 - SYNCDIV

pub fn syncsrc(&mut self) -> SYNCSRC_W<'_>

Bits 28:29 - SYNC signal source selection

pub fn syncpol(&mut self) -> SYNCPOL_W<'_>

Bit 31 - SYNC polarity selection

impl W<u32, Reg<u32, _ICR>>

pub fn syncokc(&mut self) -> SYNCOKC_W<'_>

Bit 0 - SYNC event OK clear flag

pub fn syncwarnc(&mut self) -> SYNCWARNC_W<'_>

Bit 1 - warning clear flag

pub fn errc(&mut self) -> ERRC_W<'_>

Bit 2 - Error clear flag

pub fn esyncc(&mut self) -> ESYNCC_W<'_>

Bit 3 - Expected SYNC clear flag

impl W<u16, Reg<u16, _EP0R>>

pub fn ea(&mut self) -> EA_W<'_>

Bits 0:3 - Endpoint address

pub fn stat_tx(&mut self) -> STAT_TX_W<'_>

Bits 4:5 - Status bits, for transmission transfers

pub fn dtog_tx(&mut self) -> DTOG_TX_W<'_>

Bit 6 - Data Toggle, for transmission transfers

pub fn ctr_tx(&mut self) -> CTR_TX_W<'_>

Bit 7 - Correct Transfer for transmission

pub fn ep_kind(&mut self) -> EP_KIND_W<'_>

Bit 8 - Endpoint kind

pub fn ep_type(&mut self) -> EP_TYPE_W<'_>

Bits 9:10 - Endpoint type

pub fn setup(&mut self) -> SETUP_W<'_>

Bit 11 - Setup transaction completed

pub fn stat_rx(&mut self) -> STAT_RX_W<'_>

Bits 12:13 - Status bits, for reception transfers

pub fn dtog_rx(&mut self) -> DTOG_RX_W<'_>

Bit 14 - Data Toggle, for reception transfers

pub fn ctr_rx(&mut self) -> CTR_RX_W<'_>

Bit 15 - Correct transfer for reception

impl W<u16, Reg<u16, _EP1R>>

pub fn ea(&mut self) -> EA_W<'_>

Bits 0:3 - Endpoint address

pub fn stat_tx(&mut self) -> STAT_TX_W<'_>

Bits 4:5 - Status bits, for transmission transfers

pub fn dtog_tx(&mut self) -> DTOG_TX_W<'_>

Bit 6 - Data Toggle, for transmission transfers

pub fn ctr_tx(&mut self) -> CTR_TX_W<'_>

Bit 7 - Correct Transfer for transmission

pub fn ep_kind(&mut self) -> EP_KIND_W<'_>

Bit 8 - Endpoint kind

pub fn ep_type(&mut self) -> EP_TYPE_W<'_>

Bits 9:10 - Endpoint type

pub fn setup(&mut self) -> SETUP_W<'_>

Bit 11 - Setup transaction completed

pub fn stat_rx(&mut self) -> STAT_RX_W<'_>

Bits 12:13 - Status bits, for reception transfers

pub fn dtog_rx(&mut self) -> DTOG_RX_W<'_>

Bit 14 - Data Toggle, for reception transfers

pub fn ctr_rx(&mut self) -> CTR_RX_W<'_>

Bit 15 - Correct transfer for reception

impl W<u16, Reg<u16, _EP2R>>

pub fn ea(&mut self) -> EA_W<'_>

Bits 0:3 - Endpoint address

pub fn stat_tx(&mut self) -> STAT_TX_W<'_>

Bits 4:5 - Status bits, for transmission transfers

pub fn dtog_tx(&mut self) -> DTOG_TX_W<'_>

Bit 6 - Data Toggle, for transmission transfers

pub fn ctr_tx(&mut self) -> CTR_TX_W<'_>

Bit 7 - Correct Transfer for transmission

pub fn ep_kind(&mut self) -> EP_KIND_W<'_>

Bit 8 - Endpoint kind

pub fn ep_type(&mut self) -> EP_TYPE_W<'_>

Bits 9:10 - Endpoint type

pub fn setup(&mut self) -> SETUP_W<'_>

Bit 11 - Setup transaction completed

pub fn stat_rx(&mut self) -> STAT_RX_W<'_>

Bits 12:13 - Status bits, for reception transfers

pub fn dtog_rx(&mut self) -> DTOG_RX_W<'_>

Bit 14 - Data Toggle, for reception transfers

pub fn ctr_rx(&mut self) -> CTR_RX_W<'_>

Bit 15 - Correct transfer for reception

impl W<u16, Reg<u16, _EP3R>>

pub fn ea(&mut self) -> EA_W<'_>

Bits 0:3 - Endpoint address

pub fn stat_tx(&mut self) -> STAT_TX_W<'_>

Bits 4:5 - Status bits, for transmission transfers

pub fn dtog_tx(&mut self) -> DTOG_TX_W<'_>

Bit 6 - Data Toggle, for transmission transfers

pub fn ctr_tx(&mut self) -> CTR_TX_W<'_>

Bit 7 - Correct Transfer for transmission

pub fn ep_kind(&mut self) -> EP_KIND_W<'_>

Bit 8 - Endpoint kind

pub fn ep_type(&mut self) -> EP_TYPE_W<'_>

Bits 9:10 - Endpoint type

pub fn setup(&mut self) -> SETUP_W<'_>

Bit 11 - Setup transaction completed

pub fn stat_rx(&mut self) -> STAT_RX_W<'_>

Bits 12:13 - Status bits, for reception transfers

pub fn dtog_rx(&mut self) -> DTOG_RX_W<'_>

Bit 14 - Data Toggle, for reception transfers

pub fn ctr_rx(&mut self) -> CTR_RX_W<'_>

Bit 15 - Correct transfer for reception

impl W<u16, Reg<u16, _EP4R>>

pub fn ea(&mut self) -> EA_W<'_>

Bits 0:3 - Endpoint address

pub fn stat_tx(&mut self) -> STAT_TX_W<'_>

Bits 4:5 - Status bits, for transmission transfers

pub fn dtog_tx(&mut self) -> DTOG_TX_W<'_>

Bit 6 - Data Toggle, for transmission transfers

pub fn ctr_tx(&mut self) -> CTR_TX_W<'_>

Bit 7 - Correct Transfer for transmission

pub fn ep_kind(&mut self) -> EP_KIND_W<'_>

Bit 8 - Endpoint kind

pub fn ep_type(&mut self) -> EP_TYPE_W<'_>

Bits 9:10 - Endpoint type

pub fn setup(&mut self) -> SETUP_W<'_>

Bit 11 - Setup transaction completed

pub fn stat_rx(&mut self) -> STAT_RX_W<'_>

Bits 12:13 - Status bits, for reception transfers

pub fn dtog_rx(&mut self) -> DTOG_RX_W<'_>

Bit 14 - Data Toggle, for reception transfers

pub fn ctr_rx(&mut self) -> CTR_RX_W<'_>

Bit 15 - Correct transfer for reception

impl W<u16, Reg<u16, _EP5R>>

pub fn ea(&mut self) -> EA_W<'_>

Bits 0:3 - Endpoint address

pub fn stat_tx(&mut self) -> STAT_TX_W<'_>

Bits 4:5 - Status bits, for transmission transfers

pub fn dtog_tx(&mut self) -> DTOG_TX_W<'_>

Bit 6 - Data Toggle, for transmission transfers

pub fn ctr_tx(&mut self) -> CTR_TX_W<'_>

Bit 7 - Correct Transfer for transmission

pub fn ep_kind(&mut self) -> EP_KIND_W<'_>

Bit 8 - Endpoint kind

pub fn ep_type(&mut self) -> EP_TYPE_W<'_>

Bits 9:10 - Endpoint type

pub fn setup(&mut self) -> SETUP_W<'_>

Bit 11 - Setup transaction completed

pub fn stat_rx(&mut self) -> STAT_RX_W<'_>

Bits 12:13 - Status bits, for reception transfers

pub fn dtog_rx(&mut self) -> DTOG_RX_W<'_>

Bit 14 - Data Toggle, for reception transfers

pub fn ctr_rx(&mut self) -> CTR_RX_W<'_>

Bit 15 - Correct transfer for reception

impl W<u16, Reg<u16, _EP6R>>

pub fn ea(&mut self) -> EA_W<'_>

Bits 0:3 - Endpoint address

pub fn stat_tx(&mut self) -> STAT_TX_W<'_>

Bits 4:5 - Status bits, for transmission transfers

pub fn dtog_tx(&mut self) -> DTOG_TX_W<'_>

Bit 6 - Data Toggle, for transmission transfers

pub fn ctr_tx(&mut self) -> CTR_TX_W<'_>

Bit 7 - Correct Transfer for transmission

pub fn ep_kind(&mut self) -> EP_KIND_W<'_>

Bit 8 - Endpoint kind

pub fn ep_type(&mut self) -> EP_TYPE_W<'_>

Bits 9:10 - Endpoint type

pub fn setup(&mut self) -> SETUP_W<'_>

Bit 11 - Setup transaction completed

pub fn stat_rx(&mut self) -> STAT_RX_W<'_>

Bits 12:13 - Status bits, for reception transfers

pub fn dtog_rx(&mut self) -> DTOG_RX_W<'_>

Bit 14 - Data Toggle, for reception transfers

pub fn ctr_rx(&mut self) -> CTR_RX_W<'_>

Bit 15 - Correct transfer for reception

impl W<u16, Reg<u16, _EP7R>>

pub fn ea(&mut self) -> EA_W<'_>

Bits 0:3 - Endpoint address

pub fn stat_tx(&mut self) -> STAT_TX_W<'_>

Bits 4:5 - Status bits, for transmission transfers

pub fn dtog_tx(&mut self) -> DTOG_TX_W<'_>

Bit 6 - Data Toggle, for transmission transfers

pub fn ctr_tx(&mut self) -> CTR_TX_W<'_>

Bit 7 - Correct Transfer for transmission

pub fn ep_kind(&mut self) -> EP_KIND_W<'_>

Bit 8 - Endpoint kind

pub fn ep_type(&mut self) -> EP_TYPE_W<'_>

Bits 9:10 - Endpoint type

pub fn setup(&mut self) -> SETUP_W<'_>

Bit 11 - Setup transaction completed

pub fn stat_rx(&mut self) -> STAT_RX_W<'_>

Bits 12:13 - Status bits, for reception transfers

pub fn dtog_rx(&mut self) -> DTOG_RX_W<'_>

Bit 14 - Data Toggle, for reception transfers

pub fn ctr_rx(&mut self) -> CTR_RX_W<'_>

Bit 15 - Correct transfer for reception

impl W<u16, Reg<u16, _CNTR>>

pub fn fres(&mut self) -> FRES_W<'_>

Bit 0 - Force USB Reset

pub fn pdwn(&mut self) -> PDWN_W<'_>

Bit 1 - Power down

pub fn lpmode(&mut self) -> LPMODE_W<'_>

Bit 2 - Low-power mode

pub fn fsusp(&mut self) -> FSUSP_W<'_>

Bit 3 - Force suspend

pub fn resume(&mut self) -> RESUME_W<'_>

Bit 4 - Resume request

pub fn l1resume(&mut self) -> L1RESUME_W<'_>

Bit 5 - LPM L1 Resume request

pub fn l1reqm(&mut self) -> L1REQM_W<'_>

Bit 7 - LPM L1 state request interrupt mask

pub fn esofm(&mut self) -> ESOFM_W<'_>

Bit 8 - Expected start of frame interrupt mask

pub fn sofm(&mut self) -> SOFM_W<'_>

Bit 9 - Start of frame interrupt mask

pub fn resetm(&mut self) -> RESETM_W<'_>

Bit 10 - USB reset interrupt mask

pub fn suspm(&mut self) -> SUSPM_W<'_>

Bit 11 - Suspend mode interrupt mask

pub fn wkupm(&mut self) -> WKUPM_W<'_>

Bit 12 - Wakeup interrupt mask

pub fn errm(&mut self) -> ERRM_W<'_>

Bit 13 - Error interrupt mask

pub fn pmaovrm(&mut self) -> PMAOVRM_W<'_>

Bit 14 - Packet memory area over / underrun interrupt mask

pub fn ctrm(&mut self) -> CTRM_W<'_>

Bit 15 - Correct transfer interrupt mask

impl W<u16, Reg<u16, _ISTR>>

pub fn l1req(&mut self) -> L1REQ_W<'_>

Bit 7 - LPM L1 state request

pub fn esof(&mut self) -> ESOF_W<'_>

Bit 8 - Expected start frame

pub fn sof(&mut self) -> SOF_W<'_>

Bit 9 - start of frame

pub fn reset(&mut self) -> RESET_W<'_>

Bit 10 - reset request

pub fn susp(&mut self) -> SUSP_W<'_>

Bit 11 - Suspend mode request

pub fn wkup(&mut self) -> WKUP_W<'_>

Bit 12 - Wakeup

pub fn err(&mut self) -> ERR_W<'_>

Bit 13 - Error

pub fn pmaovr(&mut self) -> PMAOVR_W<'_>

Bit 14 - Packet memory area over / underrun

impl W<u16, Reg<u16, _DADDR>>

pub fn add(&mut self) -> ADD_W<'_>

Bits 0:6 - Device address

pub fn ef(&mut self) -> EF_W<'_>

Bit 7 - Enable function

impl W<u16, Reg<u16, _BTABLE>>

pub fn btable(&mut self) -> BTABLE_W<'_>

Bits 3:15 - Buffer table

impl W<u16, Reg<u16, _COUNT0_TX>>

pub fn count0_tx(&mut self) -> COUNT0_TX_W<'_>

Bits 0:9 - Transmission byte count

impl W<u16, Reg<u16, _COUNT1_TX>>

pub fn count1_tx(&mut self) -> COUNT1_TX_W<'_>

Bits 0:9 - Transmission byte count

impl W<u16, Reg<u16, _COUNT2_TX>>

pub fn count2_tx(&mut self) -> COUNT2_TX_W<'_>

Bits 0:9 - Transmission byte count

impl W<u16, Reg<u16, _COUNT3_TX>>

pub fn count3_tx(&mut self) -> COUNT3_TX_W<'_>

Bits 0:9 - Transmission byte count

impl W<u16, Reg<u16, _COUNT4_TX>>

pub fn count4_tx(&mut self) -> COUNT4_TX_W<'_>

Bits 0:9 - Transmission byte count

impl W<u16, Reg<u16, _COUNT5_TX>>

pub fn count5_tx(&mut self) -> COUNT5_TX_W<'_>

Bits 0:9 - Transmission byte count

impl W<u16, Reg<u16, _COUNT6_TX>>

pub fn count6_tx(&mut self) -> COUNT6_TX_W<'_>

Bits 0:9 - Transmission byte count

impl W<u16, Reg<u16, _COUNT7_TX>>

pub fn count7_tx(&mut self) -> COUNT7_TX_W<'_>

Bits 0:9 - Transmission byte count

impl W<u16, Reg<u16, _ADDR0_RX>>

pub fn addr0_rx(&mut self) -> ADDR0_RX_W<'_>

Bits 1:15 - Reception buffer address

impl W<u16, Reg<u16, _ADDR1_RX>>

pub fn addr1_rx(&mut self) -> ADDR1_RX_W<'_>

Bits 1:15 - Reception buffer address

impl W<u16, Reg<u16, _ADDR2_RX>>

pub fn addr2_rx(&mut self) -> ADDR2_RX_W<'_>

Bits 1:15 - Reception buffer address

impl W<u16, Reg<u16, _ADDR3_RX>>

pub fn addr3_rx(&mut self) -> ADDR3_RX_W<'_>

Bits 1:15 - Reception buffer address

impl W<u16, Reg<u16, _ADDR4_RX>>

pub fn addr4_rx(&mut self) -> ADDR4_RX_W<'_>

Bits 1:15 - Reception buffer address

impl W<u16, Reg<u16, _ADDR5_RX>>

pub fn addr5_rx(&mut self) -> ADDR5_RX_W<'_>

Bits 1:15 - Reception buffer address

impl W<u16, Reg<u16, _ADDR6_RX>>

pub fn addr6_rx(&mut self) -> ADDR6_RX_W<'_>

Bits 1:15 - Reception buffer address

impl W<u16, Reg<u16, _ADDR7_RX>>

pub fn addr7_rx(&mut self) -> ADDR7_RX_W<'_>

Bits 1:15 - Reception buffer address

impl W<u16, Reg<u16, _COUNT0_RX>>

pub fn num_block(&mut self) -> NUM_BLOCK_W<'_>

Bits 10:14 - Number of blocks

pub fn bl_size(&mut self) -> BL_SIZE_W<'_>

Bit 15 - Block size

impl W<u16, Reg<u16, _COUNT1_RX>>

pub fn num_block(&mut self) -> NUM_BLOCK_W<'_>

Bits 10:14 - Number of blocks

pub fn bl_size(&mut self) -> BL_SIZE_W<'_>

Bit 15 - Block size

impl W<u16, Reg<u16, _COUNT2_RX>>

pub fn num_block(&mut self) -> NUM_BLOCK_W<'_>

Bits 10:14 - Number of blocks

pub fn bl_size(&mut self) -> BL_SIZE_W<'_>

Bit 15 - Block size

impl W<u16, Reg<u16, _COUNT3_RX>>

pub fn num_block(&mut self) -> NUM_BLOCK_W<'_>

Bits 10:14 - Number of blocks

pub fn bl_size(&mut self) -> BL_SIZE_W<'_>

Bit 15 - Block size

impl W<u16, Reg<u16, _COUNT4_RX>>

pub fn num_block(&mut self) -> NUM_BLOCK_W<'_>

Bits 10:14 - Number of blocks

pub fn bl_size(&mut self) -> BL_SIZE_W<'_>

Bit 15 - Block size

impl W<u16, Reg<u16, _COUNT5_RX>>

pub fn num_block(&mut self) -> NUM_BLOCK_W<'_>

Bits 10:14 - Number of blocks

pub fn bl_size(&mut self) -> BL_SIZE_W<'_>

Bit 15 - Block size

impl W<u16, Reg<u16, _COUNT6_RX>>

pub fn num_block(&mut self) -> NUM_BLOCK_W<'_>

Bits 10:14 - Number of blocks

pub fn bl_size(&mut self) -> BL_SIZE_W<'_>

Bit 15 - Block size

impl W<u16, Reg<u16, _COUNT7_RX>>

pub fn num_block(&mut self) -> NUM_BLOCK_W<'_>

Bits 10:14 - Number of blocks

pub fn bl_size(&mut self) -> BL_SIZE_W<'_>

Bit 15 - Block size

impl W<u16, Reg<u16, _LPMCSR>>

pub fn lpmen(&mut self) -> LPMEN_W<'_>

Bit 0 - LPM support enable

pub fn lpmack(&mut self) -> LPMACK_W<'_>

Bit 1 - LPM Token acknowledge enable

pub fn remwake(&mut self) -> REMWAKE_W<'_>

Bit 3 - RemoteWake value

impl W<u16, Reg<u16, _BCDR>>

pub fn bcden(&mut self) -> BCDEN_W<'_>

Bit 0 - Battery charging detector (BCD) enable

pub fn dcden(&mut self) -> DCDEN_W<'_>

Bit 1 - Data contact detection (DCD) mode enable

pub fn pden(&mut self) -> PDEN_W<'_>

Bit 2 - Primary detection (PD) mode enable

pub fn sden(&mut self) -> SDEN_W<'_>

Bit 3 - Secondary detection (SD) mode enable

pub fn dppu(&mut self) -> DPPU_W<'_>

Bit 15 - DP pull-up control

impl W<u32, Reg<u32, _CTRL>>

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 0 - Counter enable

pub fn tickint(&mut self) -> TICKINT_W<'_>

Bit 1 - SysTick exception request enable

pub fn clksource(&mut self) -> CLKSOURCE_W<'_>

Bit 2 - Clock source selection

pub fn countflag(&mut self) -> COUNTFLAG_W<'_>

Bit 16 - COUNTFLAG

impl W<u32, Reg<u32, _LOAD>>

pub fn reload(&mut self) -> RELOAD_W<'_>

Bits 0:23 - RELOAD value

impl W<u32, Reg<u32, _VAL>>

pub fn current(&mut self) -> CURRENT_W<'_>

Bits 0:23 - Current counter value

impl W<u32, Reg<u32, _CALIB>>

pub fn tenms(&mut self) -> TENMS_W<'_>

Bits 0:23 - Calibration value

pub fn skew(&mut self) -> SKEW_W<'_>

Bit 30 - SKEW flag: Indicates whether the TENMS value is exact

pub fn noref(&mut self) -> NOREF_W<'_>

Bit 31 - NOREF flag. Reads as zero

impl W<u32, Reg<u32, _STIR>>

pub fn intid(&mut self) -> INTID_W<'_>

Bits 0:8 - Software generated interrupt ID

impl W<u32, Reg<u32, _ACTRL>>

pub fn dismcycint(&mut self) -> DISMCYCINT_W<'_>

Bit 0 - DISMCYCINT

pub fn disdefwbuf(&mut self) -> DISDEFWBUF_W<'_>

Bit 1 - DISDEFWBUF

pub fn disfold(&mut self) -> DISFOLD_W<'_>

Bit 2 - DISFOLD

pub fn disfpca(&mut self) -> DISFPCA_W<'_>

Bit 8 - DISFPCA

pub fn disoofp(&mut self) -> DISOOFP_W<'_>

Bit 9 - DISOOFP

impl W<u32, Reg<u32, _CPACR>>

pub fn cp(&mut self) -> CP_W<'_>

Bits 20:23 - CP