[][src]Type Definition stm32wb_pac::rcc::pllcfgr::W

type W = W<u32, PLLCFGR>;

Writer for register PLLCFGR

Implementations

impl W[src]

pub fn pllr(&mut self) -> PLLR_W<'_>[src]

Bits 29:31 - Main PLLSYS division factor R for SYSCLK (system clock)

pub fn pllren(&mut self) -> PLLREN_W<'_>[src]

Bit 28 - Main PLLSYSR PLLCLK output enable

pub fn pllq(&mut self) -> PLLQ_W<'_>[src]

Bits 25:27 - Main PLLSYS division factor Q for PLLSYSUSBCLK

pub fn pllqen(&mut self) -> PLLQEN_W<'_>[src]

Bit 24 - Main PLLSYSQ output enable

pub fn pllp(&mut self) -> PLLP_W<'_>[src]

Bits 17:21 - Main PLL division factor P for PPLSYSSAICLK

pub fn pllpen(&mut self) -> PLLPEN_W<'_>[src]

Bit 16 - Main PLLSYSP output enable

pub fn plln(&mut self) -> PLLN_W<'_>[src]

Bits 8:14 - Main PLLSYS multiplication factor N

pub fn pllm(&mut self) -> PLLM_W<'_>[src]

Bits 4:6 - Division factor M for the main PLL and audio PLL (PLLSAI1 and PLLSAI2) input clock

pub fn pllsrc(&mut self) -> PLLSRC_W<'_>[src]

Bits 0:1 - Main PLL, PLLSAI1 and PLLSAI2 entry clock source