Struct stm32wb_pac::adc::cfgr::R

pub struct R { /* fields omitted */ }

Value read from the register

Methods

impl R

pub fn bits(&self) -> u32

Value of the register as raw bits

pub fn jqdis(&self) -> JQDISR

Bit 31 - ADC group injected contexts queue disable

pub fn awdch1ch(&self) -> AWDCH1CHR

Bits 26:30 - ADC analog watchdog 1 monitored channel selection

pub fn jauto(&self) -> JAUTOR

Bit 25 - ADC group injected automatic trigger mode

pub fn jawd1en(&self) -> JAWD1ENR

Bit 24 - ADC analog watchdog 1 enable on scope ADC group injected

pub fn awd1en(&self) -> AWD1ENR

Bit 23 - ADC analog watchdog 1 enable on scope ADC group regular

pub fn awd1sgl(&self) -> AWD1SGLR

Bit 22 - ADC analog watchdog 1 monitoring a single channel or all channels

pub fn jqm(&self) -> JQMR

Bit 21 - ADC group injected contexts queue mode

pub fn jdiscen(&self) -> JDISCENR

Bit 20 - ADC group injected sequencer discontinuous mode

pub fn discnum(&self) -> DISCNUMR

Bits 17:19 - ADC group regular sequencer discontinuous number of ranks

pub fn discen(&self) -> DISCENR

Bit 16 - ADC group regular sequencer discontinuous mode

pub fn autdly(&self) -> AUTDLYR

Bit 14 - ADC low power auto wait

pub fn cont(&self) -> CONTR

Bit 13 - ADC group regular continuous conversion mode

pub fn ovrmod(&self) -> OVRMODR

Bit 12 - ADC group regular overrun configuration

pub fn exten(&self) -> EXTENR

Bits 10:11 - ADC group regular external trigger polarity

pub fn extsel(&self) -> EXTSELR

Bits 6:9 - ADC group regular external trigger source

pub fn align(&self) -> ALIGNR

Bit 5 - ADC data alignement

pub fn res(&self) -> RESR

Bits 3:4 - ADC data resolution

pub fn dmacfg(&self) -> DMACFGR

Bit 1 - ADC DMA transfer configuration

pub fn dmaen(&self) -> DMAENR

Bit 0 - ADC DMA transfer enable