Module stm32mp1::stm32mp157::tim2
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TIM2
Modules
TIM2 auto-reload register
As the bits BK2BID, BKBID, BK2DSRM, BKDSRM, BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] can be write-locked depending on the LOCK configuration, it can be necessary to configure all of them during the first write access to the TIMx_BDTR register.
TIM2 capture/compare enable register
The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (e.g. channel 1 in input capture mode and channel 2 in output compare mode). Input capture mode:
The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (e.g. channel 1 in input capture mode and channel 2 in output compare mode). Input capture mode:
The channels 5 and 6 can only be configured in output. Output compare mode:
TIM2 capture/compare register 1
TIM2 capture/compare register 2
TIM2 capture/compare register 3
TIM2 capture/compare register 4
TIM2 capture/compare register 5
TIM2 capture/compare register 6
TIM2 counter
TIM2 control register 1
TIM2 control register 2
TIM2 DMA control register
TIM2 DMA/interrupt enable register
TIM2 DMA address for full transfer
TIM2 event generation register
TIM2 prescaler
TIM2 repetition counter register
TIM2 slave mode control register
TIM2 status register
Structs
Register block
Type Definitions
TIM2_ARR register accessor: an alias for Reg<TIM2_ARR_SPEC>
TIM2_BDTR register accessor: an alias for Reg<TIM2_BDTR_SPEC>
TIM2_CCER register accessor: an alias for Reg<TIM2_CCER_SPEC>
TIM2_CCMR1ALTERNATE2 register accessor: an alias for Reg<TIM2_CCMR1ALTERNATE2_SPEC>
TIM2_CCMR2ALTERNATE18 register accessor: an alias for Reg<TIM2_CCMR2ALTERNATE18_SPEC>
TIM2_CCMR3 register accessor: an alias for Reg<TIM2_CCMR3_SPEC>
TIM2_CCR1 register accessor: an alias for Reg<TIM2_CCR1_SPEC>
TIM2_CCR2 register accessor: an alias for Reg<TIM2_CCR2_SPEC>
TIM2_CCR3 register accessor: an alias for Reg<TIM2_CCR3_SPEC>
TIM2_CCR4 register accessor: an alias for Reg<TIM2_CCR4_SPEC>
TIM2_CCR5 register accessor: an alias for Reg<TIM2_CCR5_SPEC>
TIM2_CCR6 register accessor: an alias for Reg<TIM2_CCR6_SPEC>
TIM2_CNT register accessor: an alias for Reg<TIM2_CNT_SPEC>
TIM2_CR1 register accessor: an alias for Reg<TIM2_CR1_SPEC>
TIM2_CR2 register accessor: an alias for Reg<TIM2_CR2_SPEC>
TIM2_DCR register accessor: an alias for Reg<TIM2_DCR_SPEC>
TIM2_DIER register accessor: an alias for Reg<TIM2_DIER_SPEC>
TIM2_DMAR register accessor: an alias for Reg<TIM2_DMAR_SPEC>
TIM2_EGR register accessor: an alias for Reg<TIM2_EGR_SPEC>
TIM2_PSC register accessor: an alias for Reg<TIM2_PSC_SPEC>
TIM2_RCR register accessor: an alias for Reg<TIM2_RCR_SPEC>
TIM2_SMCR register accessor: an alias for Reg<TIM2_SMCR_SPEC>
TIM2_SR register accessor: an alias for Reg<TIM2_SR_SPEC>