Struct stm32l4xx_hal::stm32::dfsdm::dfsdm2_cr1::W

pub struct W { /* fields omitted */ }

Value to write to the register

Methods

impl W

pub fn reset_value() -> W

Reset value of the register

pub unsafe fn bits(&mut self, bits: u32) -> &mut W

Writes raw bits to the register

pub fn awfsel(&mut self) -> _AWFSELW

Bit 30 - Analog watchdog fast mode select

pub fn fast(&mut self) -> _FASTW

Bit 29 - Fast conversion mode selection for regular conversions

pub fn rch(&mut self) -> _RCHW

Bits 24:26 - Regular channel selection

pub fn rdmaen(&mut self) -> _RDMAENW

Bit 21 - DMA channel enabled to read data for the regular conversion

pub fn rsync(&mut self) -> _RSYNCW

Bit 19 - Launch regular conversion synchronously with DFSDM0

pub fn rcont(&mut self) -> _RCONTW

Bit 18 - Continuous mode selection for regular conversions

pub fn rswstart(&mut self) -> _RSWSTARTW

Bit 17 - Software start of a conversion on the regular channel

pub fn jexten(&mut self) -> _JEXTENW

Bits 13:14 - Trigger enable and trigger edge selection for injected conversions

pub fn jextsel(&mut self) -> _JEXTSELW

Bits 8:10 - Trigger signal selection for launching injected conversions

pub fn jdmaen(&mut self) -> _JDMAENW

Bit 5 - DMA channel enabled to read data for the injected channel group

pub fn jscan(&mut self) -> _JSCANW

Bit 4 - Scanning conversion mode for injected conversions

pub fn jsync(&mut self) -> _JSYNCW

Bit 3 - Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger

pub fn jswstart(&mut self) -> _JSWSTARTW

Bit 1 - Start a conversion of the injected group of channels

pub fn dfen(&mut self) -> _DFENW

Bit 0 - DFSDM enable