Struct stm32l4xx_hal::stm32::rcc::pllcfgr::W

pub struct W { /* fields omitted */ }

Value to write to the register

Methods

impl W

pub fn reset_value() -> W

Reset value of the register

pub unsafe fn bits(&mut self, bits: u32) -> &mut W

Writes raw bits to the register

pub fn pllr(&mut self) -> _PLLRW

Bits 25:26 - Main PLL division factor for PLLCLK (system clock)

pub fn pllren(&mut self) -> _PLLRENW

Bit 24 - Main PLL PLLCLK output enable

pub fn pllq(&mut self) -> _PLLQW

Bits 21:22 - Main PLL division factor for PLLUSB1CLK(48 MHz clock)

pub fn pllqen(&mut self) -> _PLLQENW

Bit 20 - Main PLL PLLUSB1CLK output enable

pub fn pllp(&mut self) -> _PLLPW

Bit 17 - Main PLL division factor for PLLSAI3CLK (SAI1 and SAI2 clock)

pub fn pllpen(&mut self) -> _PLLPENW

Bit 16 - Main PLL PLLSAI3CLK output enable

pub fn plln(&mut self) -> _PLLNW

Bits 8:14 - Main PLL multiplication factor for VCO

pub fn pllm(&mut self) -> _PLLMW

Bits 4:6 - Division factor for the main PLL and audio PLL (PLLSAI1 and PLLSAI2) input clock

pub fn pllsrc(&mut self) -> _PLLSRCW

Bits 0:1 - Main PLL, PLLSAI1 and PLLSAI2 entry clock source

pub fn pllpdiv(&mut self) -> _PLLPDIVW

Bits 27:31 - Main PLL division factor for PLLSAI2CLK