Module stm32l4x6::rcc
[−]
[src]
Reset and clock control
Modules
ahb1enr |
AHB1 peripheral clock enable register |
ahb1rstr |
AHB1 peripheral reset register |
ahb1smenr |
AHB1 peripheral clocks enable in Sleep and Stop modes register |
ahb2enr |
AHB2 peripheral clock enable register |
ahb2rstr |
AHB2 peripheral reset register |
ahb2smenr |
AHB2 peripheral clocks enable in Sleep and Stop modes register |
ahb3enr |
AHB3 peripheral clock enable register |
ahb3rstr |
AHB3 peripheral reset register |
ahb3smenr |
AHB3 peripheral clocks enable in Sleep and Stop modes register |
apb1enr1 |
APB1ENR1 |
apb1enr2 |
APB1 peripheral clock enable register 2 |
apb1rstr1 |
APB1 peripheral reset register 1 |
apb1rstr2 |
APB1 peripheral reset register 2 |
apb1smenr1 |
APB1SMENR1 |
apb1smenr2 |
APB1 peripheral clocks enable in Sleep and Stop modes register 2 |
apb2enr |
APB2ENR |
apb2rstr |
APB2 peripheral reset register |
apb2smenr |
APB2SMENR |
bdcr |
BDCR |
ccipr |
CCIPR |
cfgr |
Clock configuration register |
cicr |
Clock interrupt clear register |
cier |
Clock interrupt enable register |
cifr |
Clock interrupt flag register |
cr |
Clock control register |
csr |
CSR |
icscr |
Internal clock sources calibration register |
pllcfgr |
PLL configuration register |
pllsai1cfgr |
PLLSAI1 configuration register |
pllsai2cfgr |
PLLSAI2 configuration register |
Structs
Ahb1enr |
AHB1 peripheral clock enable register |
Ahb1rstr |
AHB1 peripheral reset register |
Ahb1smenr |
AHB1 peripheral clocks enable in Sleep and Stop modes register |
Ahb2enr |
AHB2 peripheral clock enable register |
Ahb2rstr |
AHB2 peripheral reset register |
Ahb2smenr |
AHB2 peripheral clocks enable in Sleep and Stop modes register |
Ahb3enr |
AHB3 peripheral clock enable register |
Ahb3rstr |
AHB3 peripheral reset register |
Ahb3smenr |
AHB3 peripheral clocks enable in Sleep and Stop modes register |
Apb1enr1 |
APB1ENR1 |
Apb1enr2 |
APB1 peripheral clock enable register 2 |
Apb1rstr1 |
APB1 peripheral reset register 1 |
Apb1rstr2 |
APB1 peripheral reset register 2 |
Apb1smenr1 |
APB1SMENR1 |
Apb1smenr2 |
APB1 peripheral clocks enable in Sleep and Stop modes register 2 |
Apb2enr |
APB2ENR |
Apb2rstr |
APB2 peripheral reset register |
Apb2smenr |
APB2SMENR |
Bdcr |
BDCR |
Ccipr |
CCIPR |
Cfgr |
Clock configuration register |
Cicr |
Clock interrupt clear register |
Cier |
Clock interrupt enable register |
Cifr |
Clock interrupt flag register |
Cr |
Clock control register |
Csr |
CSR |
Icscr |
Internal clock sources calibration register |
Pllcfgr |
PLL configuration register |
Pllsai1cfgr |
PLLSAI1 configuration register |
Pllsai2cfgr |
PLLSAI2 configuration register |
RegisterBlock |
Register block |