Struct stm32l4x6::dfsdm::RegisterBlock [−] [src]

#[repr(C)]

pub struct RegisterBlock {
    pub chcfg0r1: Chcfg0r1,
    pub chcfg0r2: Chcfg0r2,
    pub awscd0r: Awscd0r,
    pub chwdat0r: Chwdat0r,
    pub chdatin0r: Chdatin0r,
    pub chcfg1r1: Chcfg1r1,
    pub chcfg1r2: Chcfg1r2,
    pub awscd1r: Awscd1r,
    pub chwdat1r: Chwdat1r,
    pub chdatin1r: Chdatin1r,
    pub chcfg2r1: Chcfg2r1,
    pub chcfg2r2: Chcfg2r2,
    pub awscd2r: Awscd2r,
    pub chwdat2r: Chwdat2r,
    pub chdatin2r: Chdatin2r,
    pub chcfg3r1: Chcfg3r1,
    pub chcfg3r2: Chcfg3r2,
    pub awscd3r: Awscd3r,
    pub chwdat3r: Chwdat3r,
    pub chdatin3r: Chdatin3r,
    pub chcfg4r1: Chcfg4r1,
    pub chcfg4r2: Chcfg4r2,
    pub awscd4r: Awscd4r,
    pub chwdat4r: Chwdat4r,
    pub chdatin4r: Chdatin4r,
    pub chcfg5r1: Chcfg5r1,
    pub chcfg5r2: Chcfg5r2,
    pub awscd5r: Awscd5r,
    pub chwdat5r: Chwdat5r,
    pub chdatin5r: Chdatin5r,
    pub chcfg6r1: Chcfg6r1,
    pub chcfg6r2: Chcfg6r2,
    pub awscd6r: Awscd6r,
    pub chwdat6r: Chwdat6r,
    pub chdatin6r: Chdatin6r,
    pub chcfg7r1: Chcfg7r1,
    pub chcfg7r2: Chcfg7r2,
    pub awscd7r: Awscd7r,
    pub chwdat7r: Chwdat7r,
    pub chdatin7r: Chdatin7r,
    pub dfsdm0_cr1: Dfsdm0Cr1,
    pub dfsdm0_cr2: Dfsdm0Cr2,
    pub dfsdm0_isr: Dfsdm0Isr,
    pub dfsdm0_icr: Dfsdm0Icr,
    pub dfsdm0_jchgr: Dfsdm0Jchgr,
    pub dfsdm0_fcr: Dfsdm0Fcr,
    pub dfsdm0_jdatar: Dfsdm0Jdatar,
    pub dfsdm0_rdatar: Dfsdm0Rdatar,
    pub dfsdm0_awhtr: Dfsdm0Awhtr,
    pub dfsdm0_awltr: Dfsdm0Awltr,
    pub dfsdm0_awsr: Dfsdm0Awsr,
    pub dfsdm0_awcfr: Dfsdm0Awcfr,
    pub dfsdm0_exmax: Dfsdm0Exmax,
    pub dfsdm0_exmin: Dfsdm0Exmin,
    pub dfsdm0_cnvtimr: Dfsdm0Cnvtimr,
    pub dfsdm1_cr1: Dfsdm1Cr1,
    pub dfsdm1_cr2: Dfsdm1Cr2,
    pub dfsdm1_isr: Dfsdm1Isr,
    pub dfsdm1_icr: Dfsdm1Icr,
    pub dfsdm1_jchgr: Dfsdm1Jchgr,
    pub dfsdm1_fcr: Dfsdm1Fcr,
    pub dfsdm1_jdatar: Dfsdm1Jdatar,
    pub dfsdm1_rdatar: Dfsdm1Rdatar,
    pub dfsdm1_awhtr: Dfsdm1Awhtr,
    pub dfsdm1_awltr: Dfsdm1Awltr,
    pub dfsdm1_awsr: Dfsdm1Awsr,
    pub dfsdm1_awcfr: Dfsdm1Awcfr,
    pub dfsdm1_exmax: Dfsdm1Exmax,
    pub dfsdm1_exmin: Dfsdm1Exmin,
    pub dfsdm1_cnvtimr: Dfsdm1Cnvtimr,
    pub dfsdm2_cr1: Dfsdm2Cr1,
    pub dfsdm2_cr2: Dfsdm2Cr2,
    pub dfsdm2_isr: Dfsdm2Isr,
    pub dfsdm2_icr: Dfsdm2Icr,
    pub dfsdm2_jchgr: Dfsdm2Jchgr,
    pub dfsdm2_fcr: Dfsdm2Fcr,
    pub dfsdm2_jdatar: Dfsdm2Jdatar,
    pub dfsdm2_rdatar: Dfsdm2Rdatar,
    pub dfsdm2_awhtr: Dfsdm2Awhtr,
    pub dfsdm2_awltr: Dfsdm2Awltr,
    pub dfsdm2_awsr: Dfsdm2Awsr,
    pub dfsdm2_awcfr: Dfsdm2Awcfr,
    pub dfsdm2_exmax: Dfsdm2Exmax,
    pub dfsdm2_exmin: Dfsdm2Exmin,
    pub dfsdm2_cnvtimr: Dfsdm2Cnvtimr,
    pub dfsdm3_cr1: Dfsdm3Cr1,
    pub dfsdm3_cr2: Dfsdm3Cr2,
    pub dfsdm3_isr: Dfsdm3Isr,
    pub dfsdm3_icr: Dfsdm3Icr,
    pub dfsdm3_jchgr: Dfsdm3Jchgr,
    pub dfsdm3_fcr: Dfsdm3Fcr,
    pub dfsdm3_jdatar: Dfsdm3Jdatar,
    pub dfsdm3_rdatar: Dfsdm3Rdatar,
    pub dfsdm3_awhtr: Dfsdm3Awhtr,
    pub dfsdm3_awltr: Dfsdm3Awltr,
    pub dfsdm3_awsr: Dfsdm3Awsr,
    pub dfsdm3_awcfr: Dfsdm3Awcfr,
    pub dfsdm3_exmax: Dfsdm3Exmax,
    pub dfsdm3_exmin: Dfsdm3Exmin,
    pub dfsdm3_cnvtimr: Dfsdm3Cnvtimr,
    // some fields omitted
}

Register block

Fields

0x00 - channel configuration y register

0x04 - channel configuration y register

0x08 - analog watchdog and short-circuit detector register

0x0c - channel watchdog filter data register

0x10 - channel data input register

0x20 - CHCFG1R1

0x24 - CHCFG1R2

0x28 - AWSCD1R

0x2c - CHWDAT1R

0x30 - CHDATIN1R

0x40 - CHCFG2R1

0x44 - CHCFG2R2

0x48 - AWSCD2R

0x4c - CHWDAT2R

0x50 - CHDATIN2R

0x60 - CHCFG3R1

0x64 - CHCFG3R2

0x68 - AWSCD3R

0x6c - CHWDAT3R

0x70 - CHDATIN3R

0x80 - CHCFG4R1

0x84 - CHCFG4R2

0x88 - AWSCD4R

0x8c - CHWDAT4R

0x90 - CHDATIN4R

0xa0 - CHCFG5R1

0xa4 - CHCFG5R2

0xa8 - AWSCD5R

0xac - CHWDAT5R

0xb0 - CHDATIN5R

0xc0 - CHCFG6R1

0xc4 - CHCFG6R2

0xc8 - AWSCD6R

0xcc - CHWDAT6R

0xd0 - CHDATIN6R

0xe0 - CHCFG7R1

0xe4 - CHCFG7R2

0xe8 - AWSCD7R

0xec - CHWDAT7R

0xf0 - CHDATIN7R

0x100 - control register 1

0x104 - control register 2

0x108 - interrupt and status register

0x10c - interrupt flag clear register

0x110 - injected channel group selection register

0x114 - filter control register

0x118 - data register for injected group

0x11c - data register for the regular channel

0x120 - analog watchdog high threshold register

0x124 - analog watchdog low threshold register

0x128 - analog watchdog status register

0x12c - analog watchdog clear flag register

0x130 - Extremes detector maximum register

0x134 - Extremes detector minimum register

0x138 - conversion timer register

0x200 - control register 1

0x204 - control register 2

0x208 - interrupt and status register

0x20c - interrupt flag clear register

0x210 - injected channel group selection register

0x214 - filter control register

0x218 - data register for injected group

0x21c - data register for the regular channel

0x220 - analog watchdog high threshold register

0x224 - analog watchdog low threshold register

0x228 - analog watchdog status register

0x22c - analog watchdog clear flag register

0x230 - Extremes detector maximum register

0x234 - Extremes detector minimum register

0x238 - conversion timer register

0x300 - control register 1

0x304 - control register 2

0x308 - interrupt and status register

0x30c - interrupt flag clear register

0x310 - injected channel group selection register

0x314 - filter control register

0x318 - data register for injected group

0x31c - data register for the regular channel

0x320 - analog watchdog high threshold register

0x324 - analog watchdog low threshold register

0x328 - analog watchdog status register

0x32c - analog watchdog clear flag register

0x330 - Extremes detector maximum register

0x334 - Extremes detector minimum register

0x338 - conversion timer register

0x400 - control register 1

0x404 - control register 2

0x408 - interrupt and status register

0x40c - interrupt flag clear register

0x410 - injected channel group selection register

0x414 - filter control register

0x418 - data register for injected group

0x41c - data register for the regular channel

0x420 - analog watchdog high threshold register

0x424 - analog watchdog low threshold register

0x428 - analog watchdog status register

0x42c - analog watchdog clear flag register

0x430 - Extremes detector maximum register

0x434 - Extremes detector minimum register

0x438 - conversion timer register